CN116525432B - Etching method and preparation method of semiconductor device - Google Patents
Etching method and preparation method of semiconductor device Download PDFInfo
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- CN116525432B CN116525432B CN202310780992.3A CN202310780992A CN116525432B CN 116525432 B CN116525432 B CN 116525432B CN 202310780992 A CN202310780992 A CN 202310780992A CN 116525432 B CN116525432 B CN 116525432B
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- 238000005530 etching Methods 0.000 title claims abstract description 125
- 239000004065 semiconductor Substances 0.000 title claims abstract description 125
- 238000000034 method Methods 0.000 title claims abstract description 69
- 238000002360 preparation method Methods 0.000 title abstract description 14
- 229910021417 amorphous silicon Inorganic materials 0.000 claims abstract description 88
- WGTYBPLFGIVFAS-UHFFFAOYSA-M tetramethylammonium hydroxide Chemical compound [OH-].C[N+](C)(C)C WGTYBPLFGIVFAS-UHFFFAOYSA-M 0.000 claims abstract description 44
- 239000000758 substrate Substances 0.000 claims abstract description 40
- 238000003475 lamination Methods 0.000 claims abstract description 17
- 230000001590 oxidative effect Effects 0.000 claims abstract description 7
- 239000000243 solution Substances 0.000 claims description 92
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 claims description 17
- 239000007788 liquid Substances 0.000 claims description 16
- 238000004519 manufacturing process Methods 0.000 claims description 15
- VHUUQVKOLVNVRT-UHFFFAOYSA-N Ammonium hydroxide Chemical compound [NH4+].[OH-] VHUUQVKOLVNVRT-UHFFFAOYSA-N 0.000 claims description 10
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 claims description 10
- 239000000908 ammonium hydroxide Substances 0.000 claims description 8
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 6
- 239000011259 mixed solution Substances 0.000 claims description 6
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 6
- 230000003647 oxidation Effects 0.000 claims description 5
- 238000007254 oxidation reaction Methods 0.000 claims description 5
- 239000004973 liquid crystal related substance Substances 0.000 claims 2
- 239000000463 material Substances 0.000 description 23
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 14
- 235000011114 ammonium hydroxide Nutrition 0.000 description 8
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 5
- 239000012212 insulator Substances 0.000 description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 230000005540 biological transmission Effects 0.000 description 4
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 3
- 238000000231 atomic layer deposition Methods 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 3
- 238000002513 implantation Methods 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 238000005240 physical vapour deposition Methods 0.000 description 3
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 238000002474 experimental method Methods 0.000 description 2
- QPJSUIGXIBEQAC-UHFFFAOYSA-N n-(2,4-dichloro-5-propan-2-yloxyphenyl)acetamide Chemical compound CC(C)OC1=CC(NC(C)=O)=C(Cl)C=C1Cl QPJSUIGXIBEQAC-UHFFFAOYSA-N 0.000 description 2
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- CHYRFIXHTWWYOX-UHFFFAOYSA-N [B].[Si].[Ge] Chemical compound [B].[Si].[Ge] CHYRFIXHTWWYOX-UHFFFAOYSA-N 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 230000003139 buffering effect Effects 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000012938 design process Methods 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- QOSATHPSBFQAML-UHFFFAOYSA-N hydrogen peroxide;hydrate Chemical compound O.OO QOSATHPSBFQAML-UHFFFAOYSA-N 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- RPQDHPTXJYYUPQ-UHFFFAOYSA-N indium arsenide Chemical compound [In]#[As] RPQDHPTXJYYUPQ-UHFFFAOYSA-N 0.000 description 1
- 230000007774 longterm Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000010453 quartz Substances 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 125000006850 spacer group Chemical group 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/30604—Chemical etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
- H01L21/32134—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by liquid etching only
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
Abstract
The application relates to an etching method of a semiconductor device and a preparation method of the semiconductor device, wherein the semiconductor device comprises a substrate, a first buffer layer, an amorphous silicon layer, a side wall lamination and an oxide layer, the oxide layer is positioned on the amorphous silicon layer, and the oxide layer is a film layer formed by oxidizing the amorphous silicon layer on the surface in a natural state, and the etching method of the semiconductor device comprises the following steps: the APM solution and the tetramethyl ammonium hydroxide solution are mixed to prepare etching solution, and then the etching solution is used for etching the semiconductor device to remove the oxide layer and the amorphous silicon layer of the semiconductor device.
Description
Technical Field
The application relates to the technical field of semiconductors, in particular to an etching method and a preparation method of a semiconductor device.
Background
In the current process of 28nm semiconductor, an amorphous silicon (a-Si) process is required to remove a-Si (amorphous silicon) in the semiconductor device, so as to fill metal to form a metal gate (metal gate) later. In the process (recipe) stage of the design process, the step of removing the native oxide layer is increased to improve the efficiency of removing the amorphous silicon by considering the time (Q-time) required between the different process steps.
Conventionally, a hydrofluoric acid process (HF process) is added, and the natural oxide layer is removed by using hydrofluoric acid (HF), and then amorphous silicon is removed. Since hydrofluoric acid corrodes the sidewalls of the amorphous silicon, the pattern is damaged, and the integrity of the semiconductor device cannot be maintained.
Disclosure of Invention
Based on this, it is necessary to provide a method for etching a semiconductor device and a method for manufacturing the same, which can remove the oxide layer and ensure the integrity of the semiconductor device pattern.
In order to achieve the above object, in one aspect, the present application provides an etching method of a semiconductor device. The etching method of the semiconductor device comprises the following steps:
preparing etching liquid which is a mixed liquid comprising APM solution and tetramethyl ammonium hydroxide solution;
etching the semiconductor device by using the etching liquid with the preset temperature to remove the oxide layer and the amorphous silicon layer of the semiconductor device; the semiconductor device comprises a substrate, a first buffer layer, the amorphous silicon layer, a side wall lamination layer and the oxide layer; the first buffer layer is positioned on the substrate, the amorphous silicon layer is positioned on the first buffer layer, the side wall lamination is positioned on two sides of the first buffer layer and the amorphous silicon layer, the oxidation layer is positioned on the amorphous silicon layer, and the oxidation layer is a film layer formed by oxidizing the amorphous silicon layer on the surface in a natural state.
In one embodiment, in the mixed solution, the volume ratio of the APM solution to the tetramethyl ammonium hydroxide solution is 1:5-1:10.
In one embodiment, the volume ratio of ammonium hydroxide, hydrogen peroxide and water in the APM solution is 1:4:20 to 1:8:60.
In one embodiment, the temperature range of the preset temperature is 30 ℃ to 90 ℃.
In one embodiment, the preset temperature is 70 ℃, so that the etching rate of the etching solution on the oxide layer is maximized.
In one embodiment, when the preset temperature is less than or equal to 40 ℃, the etching rate of the etching solution on the oxide layer is 0-0.35 a/min.
In one embodiment, the etching rate of the etching solution to the oxide layer is 0-2 a/min.
The method for etching the semiconductor device comprises the steps of forming a substrate, a first buffer layer, an amorphous silicon layer, a side wall lamination and an oxide layer; the first buffer layer is positioned on the substrate, the amorphous silicon layer is positioned on the first buffer layer, the side wall lamination is positioned on two sides of the first buffer layer and the amorphous silicon layer, the oxide layer is positioned on the amorphous silicon layer, and the oxide layer is a film layer formed by oxidizing the amorphous silicon layer on the surface in a natural state, so that the etching method for the semiconductor device with the structure comprises the following steps: the APM solution and the tetramethyl ammonium hydroxide solution are mixed to prepare etching solution, and then the etching solution is used for etching the semiconductor device to remove the oxide layer and the amorphous silicon layer of the semiconductor device.
On the other hand, the application also provides a preparation method of the semiconductor device. The preparation method of the semiconductor device comprises the following steps:
providing a substrate;
forming a first buffer layer on the substrate;
forming an amorphous silicon layer on the first buffer layer;
forming a side wall lamination on the substrate, two sides of the first buffer layer and two sides of the amorphous silicon layer;
removing the oxide layer and the amorphous silicon layer by adopting the etching method of the semiconductor device in any embodiment; the oxide layer is positioned on the amorphous silicon layer, and the oxide layer is a film layer formed by oxidizing the surface of the amorphous silicon layer in a natural state.
In one embodiment, forming a sidewall stack on the substrate, on both sides of the first buffer layer, and on both sides of the amorphous silicon layer includes:
forming outer side wall layers on the inclined planes at two sides of the first buffer layer and two sides of the amorphous silicon layer;
forming a second buffer layer on the inclined planes at two sides of the first buffer layer and the outer side of the outer side wall layer, wherein the second buffer layer is in contact with the first buffer layer;
forming side walls on the substrate and the outer side of the second buffer layer;
and forming a contact etching stop layer on the substrate and on the outer side of the side wall to form the side wall lamination comprising the outer side wall layer, the second buffer layer, the side wall and the contact etching stop layer.
In one embodiment, the materials of the first buffer layer and the second buffer layer are both oxides, and the materials of the outer sidewall layer and the sidewall are both silicon nitride.
According to the preparation method of the semiconductor device, the mixed solution of the APM solution and the tetramethyl ammonium hydroxide solution is used as the etching solution, the semiconductor device with the amorphous silicon layer and the oxide layer is etched, the oxide layer and the amorphous silicon layer can be effectively removed, other components of the semiconductor device are not damaged, the integrity of the etched semiconductor device graph is guaranteed, and the preparation process of the semiconductor device is accelerated.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments or the conventional techniques of the present application, the drawings required for the descriptions of the embodiments or the conventional techniques will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present application, and other drawings may be obtained according to the drawings without inventive effort for those skilled in the art.
Fig. 1 is a schematic cross-sectional structure of a semiconductor device provided in an embodiment;
fig. 2 is a schematic cross-sectional structure of a semiconductor device after removing an oxide layer and removing an amorphous silicon layer using hydrofluoric acid;
FIG. 3 is a flow chart illustrating a method of etching a semiconductor device according to an embodiment;
FIG. 4 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present application;
fig. 5 is a flow chart illustrating a method for etching a semiconductor device according to another embodiment;
fig. 6 is a schematic flow chart of a method for manufacturing a semiconductor device according to an embodiment;
fig. 7a is a schematic cross-sectional structure of a structure obtained by performing step S610 in the method for etching a semiconductor device according to an embodiment;
fig. 7b is a schematic cross-sectional structure of the structure obtained by performing step S620 in the method for etching a semiconductor device according to an embodiment;
fig. 7c is a schematic cross-sectional structure of the structure obtained in step S630 in the method for etching a semiconductor device according to an embodiment;
FIG. 8 is a flow chart of a method for forming a sidewall stack according to an embodiment;
FIG. 9a is a schematic cross-sectional view of a structure obtained by performing step S631 in a method for forming a sidewall stack according to an embodiment;
FIG. 9b is a schematic cross-sectional view of the structure obtained by performing step S632 in the method for forming a sidewall stack according to one embodiment;
FIG. 9c is a schematic cross-sectional view of a structure obtained by performing step S633 in a method of forming a sidewall stack according to an embodiment;
FIG. 9d is a schematic cross-sectional view of a structure obtained by performing step S634 in the method for forming a sidewall stack according to one embodiment;
fig. 9e is a schematic cross-sectional structure of a semiconductor device according to an embodiment;
FIG. 9f is a schematic cross-sectional view of the semiconductor device of FIG. 9e after etching according to one embodiment;
fig. 10 is a schematic flow chart of a method for manufacturing a semiconductor device according to an embodiment;
FIG. 11 is a schematic diagram of a transmission electron microscope scanning structure of a semiconductor device according to an embodiment;
fig. 12 is a schematic diagram of a scanning structure of a transmission electron microscope after etching the semiconductor device shown in fig. 11 according to an embodiment.
Reference numerals illustrate:
10-substrate, 20-first buffer layer, 30-amorphous silicon layer, 40-sidewall stack, 401-outer sidewall layer, 402-second buffer layer, 403-sidewall, 404-contact etch stop layer, 50-oxide layer.
Detailed Description
In order that the application may be readily understood, a more complete description of the application will be rendered by reference to the appended drawings. Embodiments of the application are illustrated in the accompanying drawings. This application may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the description of the application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.
It will be understood that when an element or layer is referred to as being "on," "adjacent," "connected to," or "coupled to" another element or layer, it can be directly on, adjacent, connected, or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types and/or sections, these elements, components, regions, layers, doping types and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type or section from another element, component, region, layer, doping type or section. Thus, a first element, component, region, layer, doping type or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present application; for example, the first doping type may be made the second doping type, and similarly, the second doping type may be made the first doping type; the first doping type and the second doping type are different doping types, for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.
Spatially relative terms, such as "under", "below", "beneath", "under", "above", "over" and the like, may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements or features described as "under" or "beneath" other elements would then be oriented "on" the other elements or features. Thus, the exemplary terms "below" and "under" may include both an upper and a lower orientation. Furthermore, the device may also include an additional orientation (e.g., rotated 90 degrees or other orientations) and the spatial descriptors used herein interpreted accordingly.
As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," and/or the like, specify the presence of stated features, integers, steps, operations, elements, components, or groups thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, or groups thereof. Also, in this specification, the term "and/or" includes any and all combinations of the associated listed items.
Embodiments of the application are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the application, such that variations of the illustrated shapes due to, for example, manufacturing techniques and/or tolerances are to be expected. Thus, embodiments of the present application should not be limited to the particular shapes of the regions illustrated herein, but rather include deviations in shapes that result, for example, from manufacturing techniques. For example, an implanted region shown as a rectangle typically has rounded or curved features and/or implant concentration gradients at its edges rather than a binary change from implanted to non-implanted regions. Also, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface over which the implantation is performed. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the application.
As shown in fig. 1, a semiconductor device is provided. The semiconductor device includes a substrate 10, a first buffer layer 20, an amorphous silicon layer 30, a sidewall stack 40, and an oxide layer 50. Wherein the first buffer layer 20 is located on the substrate 10, the amorphous silicon layer 30 is located on the first buffer layer 20, and the sidewall stack 40 is located on the substrate 10 and located on both sides of the first buffer layer 20 and the amorphous silicon layer 30. Due to the natural oxidation, the amorphous silicon layer 30 is oxidized to form a natural oxide layer (native oxide), abbreviated as an oxide layer 50, on the surface in a natural state, and the oxide layer 50 may prevent the amorphous silicon layer 30 from being removed, so that the oxide layer 50 may be removed before the amorphous silicon layer 30 is removed in order to accelerate the process.
As to the background art, for the semiconductor device shown in fig. 1, before removing the amorphous silicon layer 30, hydrofluoric acid is generally used to remove the oxide layer 50, and the hydrofluoric acid has a certain etching property on the sidewall stack 40, so that the overall pattern of the semiconductor device is damaged, as shown in fig. 2, so that the pattern of the semiconductor device cannot be kept complete, and the performance of the semiconductor device is seriously affected. In this regard, the present application provides a method for etching a semiconductor device and a method for manufacturing a semiconductor device, in which the amorphous silicon layer 30 is removed while the oxide layer 50 in the structure shown in fig. 1 is removed, so that the integrity of the pattern of the semiconductor device is ensured, and the manufacturing efficiency of the semiconductor device is improved.
In one embodiment, an etching method of a semiconductor device is provided, which is applied to the semiconductor device shown in fig. 1. As shown in fig. 3, the etching method of the semiconductor device may include the following steps S310 to S320.
S310: preparing etching liquid which is mixed liquid comprising APM solution and tetramethyl ammonium hydroxide solution.
The APM solution is a mixed solution including ammonium hydroxide (NH 4 OH), hydrogen peroxide (H2O 2), and water, and is used to remove the oxide layer 50 of the semiconductor device. The tetramethyl ammonium hydroxide solution, also known as TMAH (Tetramethylammonium hydroxide) solution, is used to remove the amorphous silicon layer 30 of the semiconductor device.
S320: and etching the semiconductor device by using an etching liquid with a preset temperature to remove the oxide layer and the amorphous silicon layer of the semiconductor device.
The preset temperature is a preset temperature, and can be set according to experiments and specific application scenes, and is not limited in any way. In practical application, the semiconductor device to be etched may be etched in the etching solution after the etching solution prepared in step S310 is heated to a preset temperature. The structure of the semiconductor device shown in fig. 1 after the oxide layer 50 and the amorphous silicon layer 30 are removed by using the etching liquid disposed in step S310 is shown in fig. 4.
In the etching method of the semiconductor device provided in the above embodiment, the APM solution and the tetramethylammonium hydroxide solution are mixed to prepare the etching solution, and then the semiconductor device is etched by using the etching solution, so as to remove the oxide layer 50 and the amorphous silicon layer 30 of the semiconductor device. Because the APM solution has etching property to the oxide layer 50, but does not have etching property to the sidewall stack 40, the oxide layer 50 and the amorphous silicon layer 30 can be effectively removed by etching the semiconductor device with the etching solution, without damaging the sidewall stack 40 in the semiconductor device, thus ensuring the integrity of the pattern of the semiconductor device and improving the manufacturing efficiency of the semiconductor device.
In one embodiment, for the etching solution prepared in step S310, the volume ratio of the APM solution to the tetramethylammonium hydroxide solution in the mixed solution may be 1:5 to 1:10, for example, the volume ratio may be 1:6, 1:6.8, 1:7.5, 1:85, 1:9, or any other ratio between 1:5 to 1:10. And are not intended to be limiting in any way. The etching solution prepared by mixing the APM solution and the tetramethyl ammonium hydroxide solution based on the volume ratio has certain etching property on the oxide layer 50, and the oxide layer 50 and the amorphous silicon layer 30 can be effectively removed by using the etching solution without damaging the side wall lamination 40 of the semiconductor device, so that the integrity of the graph of the semiconductor device is ensured, and the preparation efficiency of the semiconductor device is improved.
In one embodiment, the volume ratio of ammonium hydroxide, hydrogen peroxide and water in the APM solution may be 1:4:20 to 1:8:60, for example, 1:5:30,1:6:50,1:7:40, or may be 1 (4 to 8): 20 to 60, which is not limited in any way. The APM solution formulated based on this volume ratio has a certain etching property for the oxide layer 50, and can be used to remove the oxide layer 50 of the semiconductor device without damaging the semiconductor device sidewall stack 40.
In one embodiment, when the volume ratio of ammonium hydroxide, hydrogen peroxide and water in the APM solution is 1:4:20 to 1:8:60, the temperature range of the preset temperature of the etching solution may be set to 30 ℃ to 90 ℃ to increase the etching rate of removing the oxide layer 50. The preset temperature may be set at 45 ℃, 60 ℃, 73 ℃, or the like, or any other value between 30 ℃ and 90 ℃ as an example, and is not limited in any way.
In one embodiment, based on the above embodiment, it is known through experiments and tests that the etching rate of the etching solution to the oxide layer 50 is maximized when the preset temperature of the etching solution is 70 ℃, and the etching rate of the etching solution to the oxide layer 50 is reduced compared with the etching rate at 70 ℃ when the preset temperature of the etching solution is lower than or higher than 70 ℃. Therefore, the preset temperature of the etching solution can be set at 70 ℃ to improve the etching rate of the etching solution on the oxide layer 50 and accelerate the process.
In one embodiment, when the volume ratio of ammonium hydroxide, hydrogen peroxide and water in the APM solution is 1:4:20-1:8:60, if the preset temperature of the etching solution is set to be less than or equal to 40 ℃, the etching rate of the APM solution on the oxide layer 50 is 0-0.35 a/min correspondingly. Thus, the etching solution prepared by using the APM solution and the tetramethylammonium hydroxide solution can remove the oxide layer 50 and the amorphous silicon layer 30 of the semiconductor device, ensure the integrity of the graph of the semiconductor device and improve the preparation efficiency of the semiconductor device.
In one embodiment, when the volume ratio of ammonium hydroxide, hydrogen peroxide and water in the APM solution is 1:4:20-1:8:60 and the temperature range of the preset temperature of the etching solution is 30-90 ℃, the etching rate of the APM solution in the etching solution to the oxide layer 50 is 0-2 a/min. In the actual etching process, the limit of heating of the machine is 80 ℃, so that the parts are prevented from being damaged in advance due to the fact that the machine works at the limit temperature of the machine for a long time, the preset temperature of etching liquid can be limited below 70 ℃, long-term effective operation of the machine is guaranteed, and the stability and reliability of the etching process are improved.
For better understanding, another method of etching a semiconductor device is provided in conjunction with fig. 1 and 4. As shown in fig. 5, the etching method of the semiconductor device includes the following steps S510 to S530.
S510: preparing an APM solution, wherein the volume ratio of NH4OH, H2O2 and H2O in the APM solution is 1:5:30.
S520: and preparing etching solution by mixing the APM solution and the TMAH solution, wherein the volume ratio of the APM solution to the TMAH solution in the etching solution is 1:7.
S530: and etching the semiconductor device by using the etching liquid with the temperature of 70 ℃ to remove the oxide layer and the amorphous silicon layer of the semiconductor device. Illustratively, the semiconductor device shown in fig. 1 is etched, and a semiconductor device as shown in fig. 4 can be obtained.
According to the etching method of the semiconductor device, the etching solution is prepared by mixing the APM solution and the tetramethyl ammonium hydroxide solution, and then the semiconductor device is etched by using the etching solution, so that the oxide layer and the amorphous silicon layer of the semiconductor device are removed. The APM solution has etching property to the oxide layer, but does not have etching property to the sidewall lamination, so that the oxide layer and the amorphous silicon layer can be effectively removed by etching the semiconductor device by using the etching solution, the sidewall lamination in the semiconductor device can not be damaged, the integrity of the graph of the semiconductor device is ensured, and the preparation efficiency of the semiconductor device is also improved.
In one embodiment, the application further provides a preparation method of the semiconductor device. As shown in fig. 6, the method of manufacturing the semiconductor device may include the following steps S610 to S660.
S610: a substrate is provided.
As shown in fig. 7a, the material of the substrate 10 may be any suitable substrate material, for example, at least one of the following mentioned materials may be used: silicon (Si), germanium (Ge), red phosphorus, silicon germanium (SiGe), silicon carbide (SiC), silicon germanium carbide (SiGeC), indium arsenide (InAs), gallium arsenide (GaAs), indium phosphide (InP), or other III/V compound semiconductors, and also include multilayer structures made of these semiconductors, or are not limited in this regard, silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-on-insulator (S-SiGeOI), silicon-on-insulator (SiGeOI), and germanium-on-insulator (GeOI), or may be a Double polished silicon wafer (Double Side PolishedWafers, DSP), or may be a ceramic substrate such as alumina, quartz, or glass substrate.
S620: a first buffer layer is formed on a substrate.
As shown in fig. 7b, the first buffer layer (buffer) 20 plays a role of buffering, and the material of the first buffer layer 20 may be any suitable material, which is not limited herein. The method of forming the first buffer layer 20 may be a deposition method or other suitable method, such as an atomic layer deposition (Atomic Layer Deposition, ALD) process, a physical vapor deposition (Physical Vapor Deposition, PVD) process, a chemical vapor deposition (Chemical Vapor Deposition, CVD) process, a plasma enhanced chemical vapor deposition (Plasma EnhancedChemical Vapor Deposition, PECVD) process, or a low pressure chemical vapor deposition (Low Pressure Chemical Vapor Deposition, LPCVD) process, etc., without any limitation. The thickness of the first buffer layer 20 may be set according to the product requirement, and is not limited herein.
S630: an amorphous silicon layer is formed on the first buffer layer.
As shown in fig. 7c, the material of the amorphous silicon layer 30 may be any suitable doped amorphous material, such as silicon boride (sibs), silicon germanium (SiGe), silicon carbide (SiC), silicon boron germanium (SiGeB), and the like, and is not limited in any way. The method of forming the amorphous silicon layer 30 may use a conventional technique such as a chemical vapor deposition method, and the amorphous silicon layer 30 may be formed by a low pressure chemical vapor deposition process or a Furnace process (Furnace process) or the like, for example, without any limitation.
S640: and forming a side wall layer stack (side wall) on the substrate, on two sides of the first buffer layer and on two sides of the amorphous silicon layer. See fig. 1.
S650: preparing etching liquid which is mixed liquid comprising APM solution and tetramethyl ammonium hydroxide solution. Step S650 is the same as step S310 in the above embodiments, and the etching method of the semiconductor device provided in each of the above embodiments may be referred to specifically, and will not be described herein again.
S660: and etching the semiconductor device by using an etching liquid with a preset temperature to remove the oxide layer and the amorphous silicon layer of the semiconductor device. The oxide layer is positioned on the amorphous silicon layer, and the oxide layer is a film layer formed by oxidizing the amorphous silicon layer on the surface in a natural state. Step S660 is the same as step S320 in the above embodiments, and the etching method of the semiconductor device provided in each of the above embodiments may be referred to specifically, and will not be described herein again.
According to the preparation method of the semiconductor device, the mixed solution of the APM solution and the tetramethyl ammonium hydroxide solution is used as the etching solution, the semiconductor device with the amorphous silicon layer and the oxide layer is etched, the oxide layer and the amorphous silicon layer can be effectively removed, other components of the semiconductor device are not damaged, the integrity of the etched semiconductor device graph is guaranteed, and the preparation process of the semiconductor device is accelerated.
In one embodiment, as shown in fig. 8, step S640, forming a sidewall stack on the substrate, on both sides of the first buffer layer and on both sides of the amorphous silicon layer, may include the following steps S631 to S634.
S631: and forming an outer side wall layer on the inclined planes at two sides of the first buffer layer and two sides of the amorphous silicon layer.
As shown in fig. 9a, the material of the outer sidewall layer (OSW) 401 may be any suitable material, and is not limited herein. Illustratively, the thickness of the outer sidewall layer 401 is greater than the sum of the thickness of the first buffer layer 20 and the thickness of the amorphous silicon layer 30, and may be specifically set according to the need, without any limitation.
S632: and forming a second buffer layer on the inclined planes at two sides of the first buffer layer and the outer side of the outer side wall layer.
As shown in fig. 9b, the material of the second buffer layer 402 may be any suitable material, which is not limited herein. The second buffer layer 402 is disposed in contact with the first buffer layer 20. Specifically, the second buffer layer 402 is the same material as the first buffer layer 20. Illustratively, the thickness of the second buffer layer 402 is greater than the sum of the thickness of the first buffer layer 20 and the thickness of the amorphous silicon layer 30, for example, in fig. 9b, the upper surface of the second buffer layer 402 may be flush with the upper surface of the outer sidewall layer 401, where no limitation is placed on the thickness of the second buffer layer 402.
S633: and forming side walls on the substrate and the outer side of the second buffer layer.
As shown in fig. 9c, the material of the sidewall (Spacer) 403 may be any suitable material, which is not limited in this regard. Illustratively, the thickness of the sidewall 403 is greater than the sum of the thickness of the first buffer layer 20 and the thickness of the amorphous silicon layer 30, for example, in fig. 9c, the upper surface of the sidewall 403 may be flush with the upper surface of the second buffer layer 402, where the thickness of the sidewall 403 is not limited.
S634: and forming a contact etching stop layer on the substrate and outside the side wall to form a side wall lamination comprising an outer side wall layer, a second buffer layer, the side wall and the contact etching stop layer.
As shown in fig. 9d, the material contacting the etch stop layer (contact etching stop layer, CESL) 404 may be any suitable material, and is not limited in this regard. Illustratively, the thickness of the contact etch stop layer 404 is greater than the sum of the thickness of the first buffer layer 20 and the thickness of the amorphous silicon layer 30, for example, in fig. 9d, the upper surface of the contact etch stop layer 404 may be flush with the upper surface of the sidewall 403, where the thickness of the contact etch stop layer 404 is not limited.
According to the method for manufacturing the semiconductor device, the outer side wall layer, the second buffer layer, the side wall and the contact etching stop layer are sequentially formed on the substrate, on the two sides of the first buffer layer and on the two sides of the amorphous silicon layer, so that the side wall lamination comprising the outer side wall layer, the second buffer layer, the side wall and the contact etching stop layer is formed.
In one embodiment, the first buffer layer and the second buffer layer are both made of oxide, and the outer sidewall layer and the sidewall are made of silicon nitride (SiN).
For better understanding, another method of fabricating a semiconductor device is provided. As shown in fig. 10, the etching method of the semiconductor device includes the following steps S1001 to S1010.
S1001: a substrate is provided. As shown in fig. 7a, the substrate 10 is a silicon substrate.
S1002: a first buffer layer is formed on a substrate. As shown in fig. 7b, the material of the first buffer layer 20 is an oxide.
S1003: an amorphous silicon layer is formed on the first buffer layer. As shown in fig. 7 c.
S1004: and forming an outer side wall layer on the inclined planes at two sides of the first buffer layer and two sides of the amorphous silicon layer. As shown in fig. 9a, the material of the outer sidewall layer 401 is silicon nitride.
S1005: and forming a second buffer layer on the inclined planes at two sides of the first buffer layer and the outer side of the outer side wall layer. As shown in fig. 9b, the second buffer layer 402 is the same material as the first buffer layer 20, and is also oxide.
S1006: and forming side walls on the substrate and the outer side of the second buffer layer. As shown in fig. 9c, the material of the sidewall 403 is silicon nitride.
S1007: and forming a contact etching stop layer on the substrate and outside the side wall to form a side wall lamination comprising an outer side wall layer, a second buffer layer, the side wall and the contact etching stop layer. As shown in fig. 9d, the semiconductor device shown in fig. 9d is oxidized on the amorphous silicon layer 30 in a natural state to form an oxide layer 50, as shown in fig. 9e or fig. 11.
S1008: preparing an APM solution, wherein the volume ratio of NH4OH, H2O2 and H2O in the APM solution is 1:6:40.
S1009: and preparing etching solution by mixing the APM solution and the TMAH solution, wherein the volume ratio of the APM solution to the TMAH solution in the etching solution is 1:8.
S1010: and etching the semiconductor device by using an etching liquid with the temperature of 70 ℃ to remove the oxide layer and the amorphous silicon layer of the semiconductor device. For example, the semiconductor device shown in fig. 9e and 11 is etched, and the resulting semiconductor device is shown in fig. 9f and 12. From the sectional views of the transmission electron microscope (Transmission Electron Microscope, TEM) sections shown in fig. 11 and 12, 22.1nm thick a-Si in fig. 11 has been completely removed after the process.
It should be understood that, although the steps in the respective flowcharts are shown in order as indicated by the arrows, the steps are not necessarily performed in order as indicated by the arrows. The steps are not strictly limited to the order of execution unless explicitly recited herein, and the steps may be executed in other orders. Moreover, at least a portion of the steps in the respective flowcharts may include a plurality of steps or stages, which are not necessarily performed at the same time, but may be performed at different times, and the order of the execution of the steps or stages is not necessarily sequential, but may be performed alternately or alternately with at least a portion of the steps or stages in other steps or other steps.
In the description of the present specification, reference to the terms "some embodiments," "other embodiments," "desired embodiments," and the like, means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the application. In this specification, schematic descriptions of the above terms do not necessarily refer to the same embodiment or example.
The technical features of the above embodiments may be arbitrarily combined, and for brevity, all of the possible combinations of the technical features of the above embodiments are not described, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.
The above examples illustrate only a few embodiments of the application, which are described in detail and are not to be construed as limiting the scope of the claims. It should be noted that it will be apparent to those skilled in the art that several variations and modifications can be made without departing from the spirit of the application, which are all within the scope of the application. Accordingly, the scope of protection of the present application is to be determined by the appended claims.
Claims (10)
1. A method of etching a semiconductor device, comprising:
preparing etching liquid which is a mixed liquid comprising APM solution and tetramethyl ammonium hydroxide solution;
etching the semiconductor device by using the etching liquid with the preset temperature to remove the oxide layer and the amorphous silicon layer of the semiconductor device; the semiconductor device comprises a substrate, a first buffer layer, the amorphous silicon layer, a side wall lamination layer and the oxide layer; the first buffer layer is positioned on the substrate, the amorphous silicon layer is positioned on the first buffer layer, the side wall lamination is positioned on two sides of the first buffer layer and the amorphous silicon layer, the oxidation layer is positioned on the amorphous silicon layer, and the oxidation layer is a film layer formed by oxidizing the amorphous silicon layer on the surface in a natural state; wherein, the liquid crystal display device comprises a liquid crystal display device,
in the mixed solution, the volume ratio of the APM solution to the tetramethyl ammonium hydroxide solution is 1:5-1:10;
the volume ratio of ammonium hydroxide, hydrogen peroxide and water in the APM solution is 1:4:20-1:8:60; the temperature range of the preset temperature is 30-90 ℃.
2. The method for etching a semiconductor device according to claim 1, wherein a volume ratio of ammonium hydroxide, hydrogen peroxide and water in the APM solution is 1:5:30 to 1:7:40.
3. The method of claim 1, wherein the predetermined temperature is 70 ℃ to maximize an etching rate of the oxide layer by the etching solution.
4. The method according to claim 1, wherein the etching rate of the etching solution to the oxide layer is 0-0.35 a/min when the preset temperature is less than or equal to 40 ℃.
5. The method according to claim 1, wherein an etching rate of the oxide layer by the etching solution is 0-2 a/min.
6. The method for etching a semiconductor device according to claim 1, wherein the temperature range of the preset temperature is 60 ℃ to 90 ℃.
7. A method of manufacturing a semiconductor device, comprising:
providing a substrate;
forming a first buffer layer on the substrate;
forming an amorphous silicon layer on the first buffer layer;
forming a side wall lamination on the substrate, two sides of the first buffer layer and two sides of the amorphous silicon layer;
removing the oxide layer and the amorphous silicon layer by an etching method of the semiconductor device according to any one of claims 1 to 6; the oxide layer is positioned on the amorphous silicon layer, and the oxide layer is a film layer formed by oxidizing the surface of the amorphous silicon layer in a natural state.
8. The method of manufacturing a semiconductor device according to claim 7, wherein forming a sidewall stack on the substrate, on both sides of the first buffer layer, and on both sides of the amorphous silicon layer, comprises:
forming outer side wall layers on the inclined planes at two sides of the first buffer layer and two sides of the amorphous silicon layer;
forming a second buffer layer on the inclined planes at two sides of the first buffer layer and the outer side of the outer side wall layer, wherein the second buffer layer is in contact with the first buffer layer;
forming side walls on the substrate and the outer side of the second buffer layer;
and forming a contact etching stop layer on the substrate and on the outer side of the side wall to form the side wall lamination comprising the outer side wall layer, the second buffer layer, the side wall and the contact etching stop layer.
9. The method of manufacturing a semiconductor device according to claim 8, wherein the first buffer layer and the second buffer layer are both made of oxide, and the outer sidewall layer and the sidewall are both made of silicon nitride.
10. The method for manufacturing a semiconductor device according to claim 8, wherein a thickness of the contact etch stop layer is larger than a sum of a thickness of the first buffer layer and a thickness of the amorphous silicon layer.
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| JP2001007072A (en) * | 1999-04-20 | 2001-01-12 | Nec Corp | Cleaning liquid |
| CN101379597A (en) * | 2006-02-01 | 2009-03-04 | 国立大学法人东北大学 | Semiconductor device manufacturing method and method for reducing microroughness of semiconductor surface |
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