CN116524975A - Quick reading circuit for memory chip, memory chip and electronic equipment - Google Patents
Quick reading circuit for memory chip, memory chip and electronic equipment Download PDFInfo
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- CN116524975A CN116524975A CN202310804372.9A CN202310804372A CN116524975A CN 116524975 A CN116524975 A CN 116524975A CN 202310804372 A CN202310804372 A CN 202310804372A CN 116524975 A CN116524975 A CN 116524975A
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/4074—Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4091—Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4096—Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Abstract
The application relates to the technical field of memory chips, and specifically provides a quick reading circuit for a memory chip, the memory chip and electronic equipment, wherein the circuit comprises: an operational amplifier; the source electrode of the first MOS tube is connected with the power supply voltage, the drain electrode of the first MOS tube is connected with the output end of the operational amplifier, and the grid electrode of the first MOS tube is connected with the enabling signal; the source electrode of the second MOS tube is connected with the power supply voltage, the drain electrode of the second MOS tube is connected with the inverting input end of the operational amplifier, and the grid electrode of the second MOS tube is connected with the output end of the operational amplifier; the negative power end of the operational amplifier is connected with the common ground end through the bias current source; the switch module is connected with the output end of the operational amplifier and the enabling signal; the temporary grounding module is connected with the enabling signal, the public grounding end and the grid electrode of the second MOS tube and is used for temporarily connecting the grid electrode of the second MOS tube with the public grounding end when the enabling signal is opened; the circuit can effectively improve the data reading speed of the memory chip.
Description
Technical Field
The present disclosure relates to the field of memory chips, and in particular, to a fast reading circuit for a memory chip, and an electronic device.
Background
When the memory chip performs a read operation, a read voltage is applied to a word line of the memory cell and a clamp voltage is applied to a bit line of the memory cell, the read voltage is used to put the memory cell in an on state, the clamp voltage is used to cause a voltage difference between a drain and a source of the memory cell to generate a memory current flowing through the memory cell, and the comparator generates output data according to the memory current and a reference current (iref in fig. 1).
Fig. 1 is a schematic circuit diagram of a conventional memory chip, fig. 2 is a timing chart of a read operation of the memory chip in a standby state in the prior art, vref in fig. 1 is a reference voltage, and vss in fig. 1 is a common ground. In order to reduce power consumption when the memory chip is in a standby (standby) state, the reference current is in an off state when the memory chip is in a standby state. If a read operation is required to be performed on the memory chip, the enable signal (en in fig. 1 and 2) is turned on at the first rising edge of the clock Signal (SCLK), and the bias current (ibias in fig. 1) charges the bias voltage (vbias in fig. 1 and 2) to charge the bias voltage from 0 to about the target voltage (0.5V) (0.5V in fig. 2). After the bias voltage is charged to the vicinity of the target voltage, since the inverting input terminal (fb in fig. 1) of the operational amplifier is 0, the current flowing through the NMOS transistor mn1 is equal to the tail current (tail current in fig. 1), the current flowing through the PMOS transistor mp1 is equal to 0, which corresponds to discharging the output terminal (pbias in fig. 1 and 2) of the operational amplifier with the tail current to discharge the voltage of the output terminal of the operational amplifier from vcc to the operating voltage (about vcc-1V), and the PMOS transistor mp2 is turned on at this time, and the reference current is established. Since the bias current charges the bias voltage from 0 to the target voltage at a slow speed, and when the bias voltage is near the target voltage, the tail current discharges the voltage at the output end of the operational amplifier to the working voltage at a slow speed, and only after the establishment of the gate voltage of the PMOS transistor mp2 is completed (the gate voltage of the PMOS transistor mp2 is discharged from vcc to the working voltage), the data reading can be started, so that the existing reference current establishment method has the problem of slow establishment speed of the reference current, thereby resulting in slow data reading speed of the memory chip.
In view of the above problems, no effective technical solution is currently available.
Disclosure of Invention
The invention aims to provide a quick reading circuit for a memory chip, a reading circuit and the memory chip, which can effectively improve the data reading speed of the memory chip.
In a first aspect, the present application provides a fast read circuit for a memory chip, comprising:
the non-inverting input end of the operational amplifier is connected with the reference voltage, and the positive power end of the operational amplifier is connected with the power supply voltage;
the source electrode of the first MOS tube is connected with the power supply voltage, the drain electrode of the first MOS tube is connected with the output end of the operational amplifier, and the grid electrode of the first MOS tube is connected with the enabling signal;
the source electrode of the second MOS tube is connected with the power supply voltage, the drain electrode of the second MOS tube is connected with the inverting input end of the operational amplifier, the grid electrode of the second MOS tube is connected with the output end of the operational amplifier, and the drain electrode of the second MOS tube is a reference current output end;
the negative power end of the operational amplifier is connected with the common ground end through the bias current source;
the switch module is connected with the output end of the operational amplifier and the enabling signal and is used for conducting or cutting off the output end of the operational amplifier according to the enabling signal;
the temporary grounding module is connected with the enabling signal, the public grounding end and the grid electrode of the second MOS tube and is used for temporarily connecting the grid electrode of the second MOS tube with the public grounding end when the enabling signal is opened.
According to the quick reading circuit for the memory chip, when the enabling signal is opened, the output end of the operational amplifier is conducted, the grid voltage of the second MOS tube is pulled down in advance by the temporary grounding module, so that the establishment of the grid voltage of the second MOS tube is accelerated.
Optionally, the temporary grounding module comprises a third MOS tube, a first NOT gate, a capacitor, a first resistor, a NAND gate and a second NOT gate, wherein the input end of the first NOT gate and one of the input ends of the NAND gate are connected with an enabling signal, one end of the first resistor is connected with the output end of the first NOT gate, the other end of the first resistor is connected with the other input end of the NAND gate through the capacitor, the output end of the NAND gate is connected with the input end of the second NOT gate, the output end of the second NOT gate is connected with the grid electrode of the third MOS tube, the drain electrode of the third MOS tube is connected with the grid electrode of the second MOS tube, and the source electrode of the third MOS tube is connected with the public ground.
The technical scheme is equivalent to arranging a switch between the grid electrode of the second MOS tube and the public grounding end, and because the technical scheme selects the third MOS tube as the switch and the MOS tube has the advantage of small volume, the technical scheme can effectively reduce the volume of the temporary grounding module.
Optionally, the operational amplifier includes a fourth MOS tube, a fifth MOS tube, a sixth MOS tube and a seventh MOS tube, a source electrode of the fourth MOS tube is connected with a supply voltage, a gate electrode of the fourth MOS tube is connected with a drain electrode of the fourth MOS tube and a drain electrode of the sixth MOS tube, a source electrode of the fifth MOS tube is connected with the supply voltage, a gate electrode of the fifth MOS tube is connected with a drain electrode of the fifth MOS tube and a drain electrode of the seventh MOS tube, a gate electrode of the sixth MOS tube is connected with a reference voltage, a source electrode of the sixth MOS tube is connected with a source electrode of the seventh MOS tube and a current mirror module, and a gate electrode of the seventh MOS tube is connected with a drain electrode of the second MOS tube.
Optionally, the switch module includes an eighth MOS tube, a ninth MOS tube, a tenth MOS tube, an eleventh MOS tube, a twelfth MOS tube, a thirteenth MOS tube and a fourteenth MOS tube, a source electrode of the eighth MOS tube is connected with a power supply voltage, a gate electrode of the eighth MOS tube is connected with a drain electrode of the ninth MOS tube, a drain electrode of the eighth MOS tube is connected with a drain electrode of the twelfth MOS tube and a gate electrode of the twelfth MOS tube, a source electrode of the ninth MOS tube is connected with the power supply voltage, a gate electrode of the ninth MOS tube is connected with an enable signal, a source electrode of the tenth MOS tube is connected with the power supply voltage, a gate electrode of the tenth MOS tube is connected with a gate electrode of the eleventh MOS tube, a source electrode of the eleventh MOS tube is connected with a drain electrode of the fourteenth MOS tube, a source electrode of the twelfth MOS tube is connected with a source electrode of the thirteenth MOS tube and a source electrode of the fourteenth MOS tube, a drain electrode of the thirteenth MOS tube is connected with a gate electrode of the thirteenth MOS tube and a gate electrode of the thirteenth MOS tube, a source electrode of the thirteenth MOS tube is connected with an inverted signal of the thirteenth MOS tube.
Optionally, the bias current source comprises a current mirror module, the current mirror module comprises a negative power end, a common ground end and an enabling signal which are connected with the bias current and the operational amplifier, the current mirror module comprises a bias current output end and a mirror current output end, and the bias current output end and the mirror current output end are controlled to be on-off based on the enabling signal.
Optionally, the bias current source includes a current mirror module, the current mirror module is connected with the bias current, the negative power end of the operational amplifier, the common ground end, the enabling delay signal and the enabling signal, the current mirror module includes a bias current output end and a mirror current output end, the bias current output end controls on-off based on the enabling delay signal, and the mirror current output end controls on-off based on the enabling signal.
The time node of the enable delay signal is opened later than the time node of the enable signal, so that the bias current can quickly charge the bias voltage to the supply voltage in the time period of the enable signal being opened and the enable delay signal being closed, and the tail current is positively correlated with the bias voltage due to the fact that the bias voltage in the time period is larger than the target voltage, the tail current can be effectively increased, and the second MOS tube is conducted after the output end of the operational amplifier is discharged to the working voltage, and the reference current output end outputs the reference current.
Optionally, the current mirror module includes a fifteenth MOS transistor, a sixteenth MOS transistor, a seventeenth MOS transistor, and an eighteenth MOS transistor, a drain of the fifteenth MOS transistor is connected to a bias current, a source of the fifteenth MOS transistor is connected to a drain of the seventeenth MOS transistor, a gate of the fifteenth MOS transistor is connected to a drain of the fifteenth MOS transistor and a gate of the sixteenth MOS transistor, a drain of the sixteenth MOS transistor is connected to an operational amplifier, a source of the sixteenth MOS transistor is connected to a drain of the eighteenth MOS transistor, a gate of the seventeenth MOS transistor is connected to an enable delay signal, both sources of the seventeenth MOS transistor and the eighteenth MOS transistor are connected to a common ground terminal, a gate of the eighteenth MOS transistor is connected to an enable signal, a source of the seventeenth MOS transistor is a bias current output terminal, and a source of the eighteenth MOS transistor is a mirror current output terminal.
Optionally, the fast reading circuit for the memory chip further includes a second resistor, one end of the second resistor is connected with the drain electrode of the second MOS transistor and the inverting input terminal of the operational amplifier, and the other end of the second resistor is connected with the common ground terminal.
In a second aspect, the present application also provides a memory chip comprising a fast read circuit for a memory chip as provided in the first aspect above.
According to the memory chip, the output end of the operational amplifier is conducted when the enabling signal is opened, the grid voltage of the second MOS tube is pulled down in advance by the temporary grounding module so as to accelerate the establishment of the grid voltage of the second MOS tube, because the memory chip can improve the establishment speed of the grid voltage of the second MOS tube by pulling down the grid voltage of the second MOS tube in advance by the temporary grounding module, the memory chip can only conduct data reading after the establishment of the grid voltage of the second MOS tube is completed, and therefore the memory chip can effectively improve the data reading speed of the memory chip by improving the establishment speed of the grid voltage of the second MOS tube.
In a third aspect, the present application also provides an electronic device comprising a memory chip comprising a fast read circuit for a memory chip as provided in the first aspect above.
According to the electronic equipment, the output end of the operational amplifier is conducted when the enabling signal is opened, the grid voltage of the second MOS tube is pulled down in advance by the temporary grounding module so as to accelerate the establishment of the grid voltage of the second MOS tube, because the establishment speed of the grid voltage of the second MOS tube is improved by the electronic equipment through the mode that the grid voltage of the second MOS tube is pulled down in advance by the temporary grounding module, the electronic equipment can conduct data reading only after the establishment of the grid voltage of the second MOS tube is completed, and therefore the data reading speed of a memory chip can be effectively improved by the electronic equipment through the mode that the establishment speed of the grid voltage of the second MOS tube is improved.
Therefore, the quick reading circuit for the memory chip, the memory chip and the electronic equipment provided by the application are capable of conducting the output end of the operational amplifier when the enabling signal is opened and utilizing the temporary grounding module to pull down the grid voltage of the second MOS tube in advance so as to accelerate the establishment of the grid voltage of the second MOS tube.
Drawings
Fig. 1 is a schematic circuit diagram of a conventional memory chip.
Fig. 2 is a timing chart of a read operation of a memory chip in a standby state in the prior art.
Fig. 3 is a schematic circuit diagram of a fast read circuit for a memory chip according to a first embodiment of the present application.
Fig. 4 is a timing diagram of a fast read circuit for a memory chip according to a first embodiment of the present application.
Fig. 5 is a schematic circuit diagram of a fast read circuit for a memory chip according to a second embodiment of the present application.
Fig. 6 is a timing diagram of a fast read circuit for a memory chip according to a second embodiment of the present application.
Reference numerals: 1. an operational amplifier; 2. a current mirror module; 3. a switch module; 4. a temporary grounding module; m1, a first MOS tube; m2, a second MOS tube; m3, a third MOS tube; m4, a fourth MOS tube; m5, a fifth MOS tube; m6, a sixth MOS tube; m7, a seventh MOS tube; m8, an eighth MOS tube; m9, a ninth MOS tube; m10, a tenth MOS tube; m11, eleventh MOS tube; m12, a twelfth MOS tube; m13, thirteenth MOS tube; m14, a fourteenth MOS tube; m15, a fifteenth MOS tube; m16, sixteenth MOS tube; m17, seventeenth MOS tube; m18, eighteenth MOS tube; r1, a first resistor; r2, a second resistor; NG1, a first NOT gate; C. a capacitor; ANG, nand gate; NG2, a second NOT gate; VCC, supply voltage; VSS, common ground; EN, enable signal; en_delay, enable delay signal.
Detailed Description
The following description of the embodiments of the present application will be made clearly and completely with reference to the drawings in the embodiments of the present application, and it is apparent that the described embodiments are only some embodiments of the present application, not all embodiments. The components of the embodiments of the present application, which are generally described and illustrated in the figures herein, may be arranged and designed in a wide variety of different configurations. Thus, the following detailed description of the embodiments of the present application, as provided in the accompanying drawings, is not intended to limit the scope of the application, as claimed, but is merely representative of selected embodiments of the application. All other embodiments, which can be made by those skilled in the art based on the embodiments of the present application without making any inventive effort, are intended to be within the scope of the present application.
It should be noted that: like reference numerals and letters denote like items in the following figures, and thus once an item is defined in one figure, no further definition or explanation thereof is necessary in the following figures. Meanwhile, in the description of the present application, the terms "first", "second", and the like are used only to distinguish the description, and are not to be construed as indicating or implying relative importance.
As shown in fig. 3-6, in a first aspect, the present application provides a fast read circuit for a memory chip, comprising:
the non-inverting input end of the operational amplifier 1 is connected with a reference voltage, and the positive power end of the operational amplifier 1 is connected with a power supply voltage VCC;
the source electrode of the first MOS tube M1 is connected with the power supply voltage VCC, the drain electrode of the first MOS tube M1 is connected with the output end of the operational amplifier 1, and the grid electrode of the first MOS tube M1 is connected with the enable signal EN;
the source electrode of the second MOS tube M2 is connected with the power supply voltage VCC, the drain electrode of the second MOS tube M2 is connected with the inverting input end of the operational amplifier 1, the grid electrode of the second MOS tube M2 is connected with the output end of the operational amplifier 1, and the drain electrode of the second MOS tube M is a reference current output end;
the negative power supply end of the operational amplifier 1 is connected with the common ground end VSS through the bias current source;
the switch module 3 is connected with the output end of the operational amplifier 1 and the enable signal EN and is used for conducting or cutting off the output end of the operational amplifier 1 according to the enable signal EN;
and the temporary grounding module 4 is connected with the enable signal EN, the common grounding end VSS and the grid electrode of the second MOS tube M2 and is used for temporarily connecting the grid electrode of the second MOS tube M2 with the common grounding end when the enable signal EN is opened.
The operational amplifier 1 is an existing device, the working principle of which is not discussed in detail, and the operational amplifier 1 includes five ports, which are a non-inverting input terminal, an inverting input terminal, a positive power supply terminal, a negative power supply terminal, and an output terminal, respectively, the non-inverting input terminal of the operational amplifier 1 is connected with a reference voltage (VREF in fig. 3 and 5), and the positive power supply terminal of the operational amplifier 1 is connected with a supply voltage VCC. The source electrode of the first MOS tube M1 is connected with the power supply voltage VCC, the drain electrode of the first MOS tube M1 is connected with the output end of the operational amplifier 1, and the grid electrode of the first MOS tube M1 is connected with the enable signal EN. The source electrode of the second MOS tube M2 is connected with the power supply voltage VCC, the drain electrode of the second MOS tube M2 is connected with the inverting input end of the operational amplifier 1, the grid electrode of the second MOS tube M2 is connected with the output end of the operational amplifier 1, and the drain electrode of the second MOS tube M2 is a reference current output end. The first MOS transistor M1 and the second MOS transistor M2 of this embodiment may be PMOS transistors or NMOS transistors, and the first MOS transistor M1 and the second MOS transistor M2 of this embodiment are preferably PMOS transistors, that is, the first MOS transistor M1 and the second MOS transistor M2 are both turned on when the gate is connected to the low level. The negative power supply terminal of the operational amplifier 1 is connected to the common ground terminal VSS through a bias current source for supplying a bias current and charging a bias voltage with the bias current when the enable signal EN is turned on. The switch module 3 is connected to the output terminal of the operational amplifier 1 and the enable signal EN, and the switch module 3 is configured to turn on or off the output terminal of the operational amplifier 1 according to the enable signal EN, specifically, when the enable signal EN is turned off, the switch module 3 cuts off the output terminal of the operational amplifier 1, and when the enable signal EN is turned on, the switch module 3 turns on the output terminal of the operational amplifier 1. The temporary grounding module 4 is connected to the enable signal EN, the common ground terminal VSS and the gate of the second MOS transistor M2, and the temporary grounding module 4 is configured to temporarily connect the gate of the second MOS transistor M2 to the common ground terminal VSS when the enable signal EN is turned on (corresponding to temporarily grounding the gate of the second MOS transistor M2), specifically, when the enable signal EN is turned on, the temporary grounding module 4 may generate a temporary grounding signal (refer to en_pulse in fig. 4 and 6, which is a signal at a point C in fig. 3 and 5), the grounding signal connects the gate of the second MOS transistor M2 to the common ground terminal VSS, and when the enable signal EN is turned on, the output terminal of the operational amplifier 1 is turned on, and the temporary grounding module 4 temporarily grounds the gate of the second MOS transistor M2, and when the enable signal EN is turned on, the output terminal of the operational amplifier 1 is discharged, and when the enable signal EN is turned on, the current technology needs to be advanced by a period of time to establish a voltage corresponding to the current-accelerating voltage of the second MOS transistor M2, compared with the prior art that the current technology can establish a voltage of the second MOS transistor M2 by pulling up the voltage of the output terminal of the operational amplifier M1. It should be understood that, since the first MOS transistor M1 is a PMOS transistor, and the gate of the first MOS transistor M1 is connected to the enable signal EN, when the enable signal EN is turned off, the first MOS transistor M1 is turned on, the voltage at the output end of the operational amplifier 1 (Pbias in fig. 4, the voltage being the voltage at the point a in fig. 3) is charged to the supply voltage VCC, and the second MOS transistor M2 is turned off, so that the output of the reference current output end at this time is 0, that is, the reference current is in the off state. It should also be appreciated that this embodiment corresponds to discharging the output of the operational amplifier 1 with tail current after the bias current charges the bias voltage to around the target voltage.
The working principle of the embodiment is as follows: according to the quick reading circuit for the memory chip, when the enable signal EN is opened, the output end of the operational amplifier 1 is conducted, the grid voltage of the second MOS tube M2 is pulled down in advance by the temporary grounding module 4, so that the establishment of the grid voltage of the second MOS tube M2 is accelerated, the establishment speed of the grid voltage of the second MOS tube M2 is improved in a mode that the grid voltage of the second MOS tube M2 is pulled down in advance by the temporary grounding module 4, and the circuit can only conduct data reading after the establishment of the grid voltage of the second MOS tube M2 is completed, so that the circuit can effectively improve the data reading speed of the memory chip in a mode that the establishment speed of the grid voltage of the second MOS tube M2 is improved. This embodiment corresponds to assisting in discharging the voltage at the output of the operational amplifier 1 to the operating voltage by temporarily grounding the output of the operational amplifier 1 when the enable signal EN is turned on.
In some embodiments, the temporary grounding module 4 includes a third MOS transistor M3, a first non-gate NG1, a capacitor C, a first resistor R1, a nand gate ANG and a second non-gate NG2, where an input end of the first non-gate NG1 and one of input ends of the nand gate ANG are connected to an enable signal EN, one end of the first resistor R1 is connected to an output end of the first non-gate NG1, another end of the first resistor R1 is connected to another input end of the nand gate ANG through the capacitor C, an output end of the nand gate ANG is connected to an input end of the second non-gate NG2, an output end of the second non-gate NG2 is connected to a gate of the third MOS transistor M3, a drain electrode of the third MOS transistor M3 is connected to a gate of the second MOS transistor M2, and a source electrode of the third MOS transistor M3 is connected to the common ground terminal VSS. The third MOS transistor M3 of this embodiment is an NMOS transistor, and the working principle of this embodiment is as follows: when the enable signal EN is closed, the output end of the first NOT gate NG1 outputs a high level, the capacitor C is charged, the two input ends of the NAND gate ANG are respectively connected with the high level and the low level, the output end of the NAND gate ANG outputs the high level, the output end of the second NOT gate NG2 outputs the low level, and as the NMOS tube is conducted when the grid is connected with the high level, the third MOS tube M3 is in a cut-off state when the enable signal EN is closed; when the enable signal EN is turned on, the output end of the first NOT gate NG1 outputs a low level, at this time, the capacitor C discharges, and both input ends of the NAND gate ANG are connected with a high level, so that the third MOS transistor M3 is turned on, and the gate of the second MOS transistor M2 is connected with the common ground terminal VSS (i.e., the second MOS transistor M2 is grounded). It should be understood that, since one of the input ends of the nand gate ANG is connected to the low level after the capacitor C finishes discharging, the third MOS transistor M3 is cut off after the capacitor C finishes discharging, and the gate of the second MOS transistor M2 is not connected to the common ground terminal VSS, so as to generate a temporary ground signal, so that the gate of the second MOS transistor M2 is temporarily grounded. The embodiment is equivalent to arranging a switch between the gate of the second MOS transistor M2 and the common ground terminal VSS, and because the embodiment selects the third MOS transistor M3 as the switch, the MOS transistor has the advantage of small volume, the embodiment can effectively reduce the volume of the temporary grounding module 4.
In some embodiments, the operational amplifier 1 includes a fourth MOS transistor M4, a fifth MOS transistor M5, a sixth MOS transistor M6, and a seventh MOS transistor M7, the source of the fourth MOS transistor M4 is connected to the supply voltage VCC, the gate of the fourth MOS transistor M4 is connected to the drain of the fourth MOS transistor M4 and the drain of the sixth MOS transistor M6, the source of the fifth MOS transistor M5 is connected to the supply voltage VCC, the gate of the fifth MOS transistor M5 is connected to the drain of the fifth MOS transistor M5 and the drain of the seventh MOS transistor M7, the gate of the sixth MOS transistor M6 is connected to the reference voltage, the source of the sixth MOS transistor M6 and the source of the seventh MOS transistor M7 are connected to the current mirror module 2, and the gate of the seventh MOS transistor M7 is connected to the drain of the second MOS transistor M2. The fourth MOS transistor M4 and the fifth MOS transistor M5 in this embodiment are PMOS transistors, and the sixth MOS transistor M6 and the seventh MOS transistor M7 in this embodiment are NMOS transistors. Specifically, the source electrode of the fourth MOS transistor M4 and the source electrode of the fifth MOS transistor M5 are positive power supply terminals of the operational amplifier 1, the gate electrode of the sixth MOS transistor M6 is a positive input terminal of the operational amplifier 1, the gate electrode of the seventh MOS transistor M7 is an inverted input terminal of the operational amplifier 1, the source electrode of the sixth MOS transistor M6 and the source electrode of the seventh MOS transistor M7 are negative power supply terminals of the operational amplifier 1, and the gate electrode of the fifth MOS transistor M5 is an output terminal of the operational amplifier 1.
In some embodiments, the switch module 3 includes an eighth MOS transistor M8, a ninth MOS transistor M9, a tenth MOS transistor M10, an eleventh MOS transistor M11, a twelfth MOS transistor M12, a thirteenth MOS transistor M13, and a fourteenth MOS transistor M14, the source of the eighth MOS transistor M8 is connected to the supply voltage VCC, the gate of the eighth MOS transistor M8 is connected to the drain of the ninth MOS transistor M9, the drain of the eighth MOS transistor M8 is connected to the drain of the twelfth MOS transistor M12 and the gate of the twelfth MOS transistor M12, the source of the ninth MOS transistor M9 is connected to the supply voltage VCC, the gate of the ninth MOS transistor M9 is connected to the enable signal EN, the source of the tenth MOS transistor M10 is connected to the supply voltage VCC, the gate of the tenth MOS transistor M10 is connected to the enable signal EN, the drain of the eleventh MOS transistor M11 is connected to the gate of the supply voltage VCC, the drain of the eleventh MOS transistor M11 is connected to the drain of the fourteenth MOS transistor M9, the drain of the thirteenth MOS transistor M12 is connected to the drain of the thirteenth MOS transistor M14, and the drain of the thirteenth MOS transistor M13 is connected to the gate of the thirteenth MOS transistor M13 in the thirteenth transistor M13 and the thirteenth transistor M14. The eighth MOS transistor M8, the ninth MOS transistor M9, the tenth MOS transistor M10, and the eleventh MOS transistor M11 of the embodiment are PMOS transistors, and the twelfth MOS transistor M12, the thirteenth MOS transistor M13, and the fourteenth MOS transistor M14 of the embodiment are NMOS transistors, specifically, if the enable signal EN is turned on, the ninth MOS transistor M9, the tenth MOS transistor M10, and the thirteenth MOS transistor M13 are cut off, and the eighth MOS transistor M8, the eleventh MOS transistor M11, the twelfth MOS transistor M12, and the fourteenth MOS transistor M14 are turned on; if the enable signal EN is turned off, the ninth MOS transistor M9, the tenth MOS transistor M10, and the thirteenth MOS transistor M13 are turned on, the eighth MOS transistor M8, the eleventh MOS transistor M11, the twelfth MOS transistor M12, and the fourteenth MOS transistor M14 are turned off, and the thirteenth MOS transistor M13 of this embodiment is configured to completely release the voltage generated by the internal current when the switching module 3 cuts off the output terminal of the operational amplifier 1.
As shown in fig. 5, in some embodiments, the bias current source includes a current mirror module 2, where the current mirror module 2 is connected to the bias current, the negative power supply terminal of the operational amplifier 1, the common ground terminal VSS, and the enable signal EN, and the current mirror module 2 includes a bias current output terminal and a mirror current output terminal, where the bias current output terminal and the mirror current output terminal both control on-off based on the enable signal EN. Specifically, the bias current output terminal is connected to the bias current, the enable signal EN, and the common ground terminal VSS, and the mirror current output terminal is connected to the negative power supply terminal of the operational amplifier, the enable signal EN, and the common ground terminal VSS. When a read operation is required for the memory chip, the enable signal EN is turned on at the first rising edge of the clock signal, both the bias current output terminal and the mirror current output terminal are turned on, and the bias current charges the bias voltage to around the target voltage (refer to fig. 6).
The bias current of the above embodiment only charges the bias voltage to the vicinity of the target voltage (0.5V) (0.5V in fig. 4 and 6), and since the parasitic capacitance of the output terminal of the operational amplifier 1 is large, the above embodiment cannot realize the rapid discharge of the output terminal of the operational amplifier 1 only by discharging the output terminal of the operational amplifier 1 in advance, thereby affecting the data reading speed of the memory chip.
To solve this problem, as shown in fig. 3, in some embodiments, the bias current source includes a current mirror module 2, where the current mirror module 2 is connected to the bias current, a negative power supply terminal of the operational amplifier 1, a common ground terminal VSS, an enable delay signal en_delay, and an enable signal EN, and the current mirror module 2 includes a bias current output terminal and a mirror current output terminal, where the bias current output terminal controls on/off based on the enable delay signal en_delay, and the mirror current output terminal controls on/off based on the enable signal EN. Specifically, the bias current output terminal is connected to the bias current, the enable delay signal en_delay, and the common ground terminal VSS, and the mirror current output terminal is connected to the negative power supply terminal of the operational amplifier, the enable signal EN, and the common ground terminal VSS. When a read operation is required on the memory chip, the enable signal EN is turned on at the first rising edge of the clock signal, and the enable delay signal en_delay is turned on after the first rising edge of the clock signal, i.e. the time node of the enable delay signal en_delay is turned on later than the time node of the enable signal EN, the current mirror module 2 is used for mirroring the current when both the enable delay signal en_delay and the enable signal EN are turned on, specifically, during the period of time when the enable signal EN is turned on and the enable delay signal en_delay is turned off, the mirroring current output terminal is turned off, the current mirror module 2 will not mirror the current, so the biasing current (Ibias in fig. 3) will rapidly charge the biasing voltage (Vbias in fig. 4, the biasing voltage is the voltage at point B in fig. 3) to charge the biasing voltage from 0 to the vicinity of the power supply voltage (VCC in fig. 4), and after the enable delay signal en_delay is turned on, the mirroring current output terminal is turned on, the mirroring current mirror module 2 will not mirror the current, and the biasing voltage is started to discharge from the vicinity of the VCC module. Since the time node of the enable delay signal en_delay is turned on later than the time node of the enable signal EN, the bias current rapidly charges the bias voltage to the supply voltage VCC in the period of the enable signal EN being turned on and the enable delay signal en_delay being turned off, and since the bias voltage in the period is greater than the target voltage and the magnitude of the tail current is positively correlated with the magnitude of the bias voltage, the embodiment can effectively increase the tail current, and since the magnitude of the tail current is positively correlated with the discharge rate of the output terminal of the operational amplifier 1, the second MOS transistor M2 is turned on after the output terminal of the operational amplifier 1 is discharged to the operating voltage, and the reference current output terminal outputs the reference current, that is, the embodiment is equivalent to gradually establishing the reference current by the enable signal EN and the enable delay signal en_delay, the embodiment can effectively increase the discharge rate of the output terminal of the operational amplifier 1 by increasing the tail current, so that the voltage of the output terminal of the operational amplifier 1 is rapidly discharged to the operating voltage, thereby effectively increasing the read speed of the reference current, and further effectively increasing the read speed of the data. This embodiment corresponds to a rapid discharge of the output of the operational amplifier 1 by increasing the tail current and starting the discharge of the output of the operational amplifier 1 in advance.
In some embodiments, the current mirror module 2 includes a fifteenth MOS transistor M15, a sixteenth MOS transistor M16, a seventeenth MOS transistor M17, and an eighteenth MOS transistor M18, the drain of the fifteenth MOS transistor M15 is connected to the bias current, the source of the fifteenth MOS transistor M15 is connected to the drain of the seventeenth MOS transistor M17, the gate of the fifteenth MOS transistor M15 is connected to the drain of the fifteenth MOS transistor M15 and the gate of the sixteenth MOS transistor M16, the drain of the sixteenth MOS transistor M16 is connected to the operational amplifier 1, the source of the sixteenth MOS transistor M16 is connected to the drain of the eighteenth MOS transistor M18, the gates of the seventeenth MOS transistor M17 and the eighteenth MOS transistor M18 are both connected to the common ground terminal VSS, the gate of the eighteenth MOS transistor M18 is connected to the enable signal EN, the source of the seventeenth MOS transistor M17 is the bias current output terminal, and the source of the eighteenth MOS transistor M18 is the mirror current output terminal. The fifteenth MOS transistor M15, the sixteenth MOS transistor M16, the seventeenth MOS transistor M17, and the eighteenth MOS transistor M18 of this embodiment are all NMOS transistors. In this embodiment, if the enable signal EN is turned off, the eighteenth MOS transistor M18 is turned off, and the mirror current output terminal is turned off, i.e., the output of the mirror current output terminal is 0; if the enable signal EN is turned on, the eighteenth MOS transistor M18 is turned on, and the mirror current output end is turned on, namely the output of the mirror current output end is not 0; if the enable delay signal EN_delay is closed, the seventeenth MOS tube M17 is cut off, and the bias current output end is cut off, namely the output of the bias current output end is 0; if the enable delay signal en_delay is turned on, the seventeenth MOS transistor M17 is turned on, and the bias current output terminal is turned on, that is, the output of the bias current output terminal is not 0.
In some embodiments, the fast read circuit for a memory chip further includes a second resistor R2, one end of the second resistor R2 is connected to the drain of the second MOS transistor M2 and the inverting input terminal of the operational amplifier 1, and the other end of the second resistor R2 is connected to the common ground terminal VSS.
As can be seen from the above, the fast read circuit for a memory chip provided by the present application turns on the output end of the operational amplifier 1 and pulls down the gate voltage of the second MOS transistor M2 in advance by using the temporary grounding module 4 when the enable signal EN is turned on, so as to accelerate the establishment of the gate voltage of the second MOS transistor M2.
In a second aspect, the present application also provides a memory chip, the read circuit comprising a fast read circuit for a memory chip as provided in the first aspect above.
The working principle of the memory chip of the embodiment is the same as that of the fast reading circuit for a memory chip provided in the first aspect, and will not be discussed in detail here.
As can be seen from the above, according to the memory chip provided by the present application, when the enable signal EN is turned on, the output end of the operational amplifier 1 is turned on, and the gate voltage of the second MOS transistor M2 is pulled down in advance by the temporary grounding module 4, so as to accelerate the establishment of the gate voltage of the second MOS transistor M2, because the memory chip increases the establishment speed of the gate voltage of the second MOS transistor M2 by pulling down the gate voltage of the second MOS transistor M2 in advance by the temporary grounding module 4, the memory chip can perform data reading only after the establishment of the gate voltage of the second MOS transistor M2 is completed, and therefore the memory chip can effectively increase the data reading speed of the memory chip by increasing the establishment speed of the gate voltage of the second MOS transistor M2.
In a third aspect, the present application also provides an electronic device comprising a memory chip comprising a fast read circuit for a memory chip as provided in the first aspect above.
An embodiment of the present application provides an electronic device, where the electronic device includes a memory chip, where the memory chip includes a fast reading circuit for a memory chip provided in the first aspect, and an operating principle of the electronic device of the embodiment is the same as an operating principle of the fast reading circuit for a memory chip provided in the first aspect, and will not be discussed in detail herein.
As can be seen from the above, according to the electronic device provided by the present application, when the enable signal EN is turned on, the output end of the operational amplifier 1 is turned on, and the gate voltage of the second MOS transistor M2 is pulled down in advance by using the temporary grounding module 4, so as to accelerate the establishment of the gate voltage of the second MOS transistor M2, because the electronic device increases the establishment speed of the gate voltage of the second MOS transistor M2 by pulling down the gate voltage of the second MOS transistor M2 in advance by using the temporary grounding module 4, the electronic device can only perform data reading after the establishment of the gate voltage of the second MOS transistor M2 is completed, and therefore the electronic device can effectively increase the data reading speed of the memory chip by increasing the establishment speed of the gate voltage of the second MOS transistor M2.
As can be seen from the above, according to the fast reading circuit for a memory chip, the memory chip and the electronic device provided by the application, when the enable signal EN is turned on, the output end of the operational amplifier 1 is turned on, and the gate voltage of the second MOS transistor M2 is pulled down in advance by the temporary grounding module 4, so as to accelerate the establishment of the gate voltage of the second MOS transistor M2, because the circuit increases the establishment speed of the gate voltage of the second MOS transistor M2 by pulling down the gate voltage of the second MOS transistor M2 in advance by the temporary grounding module 4, the circuit can perform data reading only after the establishment of the gate voltage of the second MOS transistor M2 is completed, and therefore, the circuit can effectively increase the data reading speed of the memory chip by increasing the establishment speed of the gate voltage of the second MOS transistor M2.
In the embodiments provided in the present application, it should be understood that the disclosed apparatus and method may be implemented in other manners. The device embodiments described above are merely illustrative and the coupling or direct coupling or communication connection shown or discussed with each other may be through some communication interface, indirect coupling or communication connection of devices or units, electrical, mechanical or otherwise.
In this document, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions.
The foregoing is merely exemplary embodiments of the present application and is not intended to limit the scope of the present application, and various modifications and variations may be suggested to one skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principles of the present application should be included in the protection scope of the present application.
Claims (10)
1. A fast read circuit for a memory chip, the fast read circuit for a memory chip comprising:
the non-inverting input end of the operational amplifier is connected with the reference voltage, and the positive power end of the operational amplifier is connected with the power supply voltage;
the source electrode of the first MOS tube is connected with the power supply voltage, the drain electrode of the first MOS tube is connected with the output end of the operational amplifier, and the grid electrode of the first MOS tube is connected with an enabling signal;
the source electrode of the second MOS tube is connected with the power supply voltage, the drain electrode of the second MOS tube is connected with the inverting input end of the operational amplifier, the grid electrode of the second MOS tube is connected with the output end of the operational amplifier, and the drain electrode of the second MOS tube is a reference current output end;
the negative power end of the operational amplifier is connected with the common ground end through the bias current source;
the switch module is connected with the output end of the operational amplifier and the enabling signal and is used for conducting or cutting off the output end of the operational amplifier according to the enabling signal;
the temporary grounding module is connected with the enabling signal, the public grounding end and the grid electrode of the second MOS tube and is used for temporarily connecting the grid electrode of the second MOS tube with the public grounding end when the enabling signal is opened.
2. The fast read circuit for a memory chip according to claim 1, wherein the temporary grounding module comprises a third MOS transistor, a first not gate, a capacitor, a first resistor, a nand gate, and a second not gate, wherein an input terminal of the first not gate and one input terminal of the nand gate are connected to the enable signal, one end of the first resistor is connected to an output terminal of the first not gate, the other end of the first resistor is connected to another input terminal of the nand gate through the capacitor, an output terminal of the nand gate is connected to an input terminal of the second not gate, an output terminal of the second not gate is connected to a gate of the third MOS transistor, a drain terminal of the third MOS transistor is connected to a gate of the second MOS transistor, and a source terminal of the third MOS transistor is connected to a common ground terminal.
3. The fast read circuit for a memory chip according to claim 1, wherein the operational amplifier comprises a fourth MOS transistor, a fifth MOS transistor, a sixth MOS transistor and a seventh MOS transistor, a source of the fourth MOS transistor is connected to the power supply voltage, a gate of the fourth MOS transistor is connected to a drain of the fourth MOS transistor and a drain of the sixth MOS transistor, a source of the fifth MOS transistor is connected to the power supply voltage, a gate of the fifth MOS transistor is connected to a drain of the fifth MOS transistor and a drain of the seventh MOS transistor, a gate of the sixth MOS transistor is connected to the reference voltage, a source of the sixth MOS transistor and a source of the seventh MOS transistor are connected to the current mirror module, and a gate of the seventh MOS transistor is connected to a drain of the second MOS transistor.
4. The fast read circuit for a memory chip according to claim 1, wherein the switch module includes an eighth MOS transistor, a ninth MOS transistor, a tenth MOS transistor, an eleventh MOS transistor, a twelfth MOS transistor, a thirteenth MOS transistor, and a fourteenth MOS transistor, a source of the eighth MOS transistor is connected to the power supply voltage, a gate of the eighth MOS transistor is connected to a drain of the ninth MOS transistor, a drain of the eighth MOS transistor is connected to a drain of the twelfth MOS transistor and a gate of the twelfth MOS transistor, a source of the ninth MOS transistor is connected to the power supply voltage, a gate of the ninth MOS transistor is connected to the enable signal, a source of the tenth MOS transistor is connected to the power supply voltage, a gate of the tenth MOS transistor is connected to the enable signal, a drain of the tenth MOS transistor is connected to a gate of the eleventh MOS transistor, a source of the eleventh MOS transistor is connected to the power supply voltage, a drain of the eleventh MOS transistor is connected to the drain of the thirteenth MOS transistor, a source of the thirteenth MOS transistor is connected to the drain of the thirteenth MOS transistor.
5. The fast read circuit for a memory chip of claim 1, wherein the bias current source comprises a current mirror module, the current mirror module comprising a connection to a bias current, a negative supply terminal of an operational amplifier, a common ground, and an enable signal, the current mirror module comprising a bias current output and a mirror current output, the bias current output and the mirror current output each controlling on and off based on the enable signal.
6. The fast read circuit for a memory chip of claim 1, wherein the bias current source comprises a current mirror module connected to a bias current, a negative supply terminal of the operational amplifier, a common ground terminal, an enable delay signal, and an enable signal, the current mirror module comprising a bias current output terminal and a mirror current output terminal, the bias current output terminal controlling on-off based on the enable delay signal, the mirror current output terminal controlling on-off based on the enable signal.
7. The fast read circuit for a memory chip according to claim 6, wherein the current mirror module comprises a fifteenth MOS transistor, a sixteenth MOS transistor, a seventeenth MOS transistor, and an eighteenth MOS transistor, wherein a drain of the fifteenth MOS transistor is connected to a bias current, a source of the fifteenth MOS transistor is connected to a drain of the seventeenth MOS transistor, a gate of the fifteenth MOS transistor is connected to a drain of the fifteenth MOS transistor and a gate of the sixteenth MOS transistor, a drain of the sixteenth MOS transistor is connected to the operational amplifier, a source of the sixteenth MOS transistor is connected to a drain of the eighteenth MOS transistor, a gate of the seventeenth MOS transistor is connected to the enable delay signal, a source of the seventeenth MOS transistor and a source of the eighteenth MOS transistor are both connected to a common ground terminal, a gate of the eighteenth MOS transistor is connected to the enable signal, a source of the seventeenth MOS transistor is a bias current output terminal, and a source of the eighteenth MOS transistor is a mirror current output terminal.
8. The fast read circuit for a memory chip according to claim 1, further comprising a second resistor, wherein one end of the second resistor is connected to the drain of the second MOS transistor and the inverting input terminal of the operational amplifier, and the other end of the second resistor is connected to the common ground terminal.
9. A memory chip comprising a fast read circuit for a memory chip according to any one of claims 1-8.
10. An electronic device comprising a memory chip comprising a fast read circuit for a memory chip according to any of claims 1-8.
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