CN116520633A - Method for accelerating OPC correction speed of chip layout - Google Patents

Method for accelerating OPC correction speed of chip layout Download PDF

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Publication number
CN116520633A
CN116520633A CN202310473250.6A CN202310473250A CN116520633A CN 116520633 A CN116520633 A CN 116520633A CN 202310473250 A CN202310473250 A CN 202310473250A CN 116520633 A CN116520633 A CN 116520633A
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layout
pattern
accelerating
value
corrected
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夏明�
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Shanghai Huali Integrated Circuit Manufacturing Co Ltd
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Shanghai Huali Integrated Circuit Manufacturing Co Ltd
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Priority to CN202310473250.6A priority Critical patent/CN116520633A/en
Publication of CN116520633A publication Critical patent/CN116520633A/en
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    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
    • G03F1/36—Masks having proximity correction features; Preparation thereof, e.g. optical proximity correction [OPC] design processes
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
    • G03F1/38—Masks having auxiliary features, e.g. special coatings or marks for alignment or testing; Preparation thereof
    • G03F1/42—Alignment or registration features, e.g. alignment marks on the mask substrates
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
    • G03F1/38—Masks having auxiliary features, e.g. special coatings or marks for alignment or testing; Preparation thereof
    • G03F1/44—Testing or measuring features, e.g. grid patterns, focus monitors, sawtooth scales or notched scales
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/20—Exposure; Apparatus therefor
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70—Microphotolithographic exposure; Apparatus therefor
    • G03F7/70425—Imaging strategies, e.g. for increasing throughput or resolution, printing product fields larger than the image field or compensating lithography- or non-lithography errors, e.g. proximity correction, mix-and-match, stitching or double patterning
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70—Microphotolithographic exposure; Apparatus therefor
    • G03F7/70425—Imaging strategies, e.g. for increasing throughput or resolution, printing product fields larger than the image field or compensating lithography- or non-lithography errors, e.g. proximity correction, mix-and-match, stitching or double patterning
    • G03F7/70433—Layout for increasing efficiency or for compensating imaging errors, e.g. layout of exposure fields for reducing focus errors; Use of mask features for increasing efficiency or for compensating imaging errors
    • G03F7/70441—Optical proximity correction [OPC]
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70—Microphotolithographic exposure; Apparatus therefor
    • G03F7/70483—Information management; Active and passive control; Testing; Wafer monitoring, e.g. pattern monitoring
    • G03F7/70491—Information management, e.g. software; Active and passive control, e.g. details of controlling exposure processes or exposure tool monitoring processes
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70—Microphotolithographic exposure; Apparatus therefor
    • G03F7/70483—Information management; Active and passive control; Testing; Wafer monitoring, e.g. pattern monitoring
    • G03F7/70605—Workpiece metrology
    • G03F7/70616—Monitoring the printed patterns
    • G03F7/70625—Dimensions, e.g. line width, critical dimension [CD], profile, sidewall angle or edge roughness
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P90/00—Enabling technologies with a potential contribution to greenhouse gas [GHG] emissions mitigation
    • Y02P90/02—Total factory control, e.g. smart factories, flexible manufacturing systems [FMS] or integrated manufacturing systems [IMS]

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  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Preparing Plates And Mask In Photomechanical Process (AREA)

Abstract

The invention provides a method for accelerating OPC correction speed of a chip layout, which provides a design layout, wherein the design layout consists of a plurality of types of graphs, and line segments consisting of a plurality of sampling points are arranged according to the outline of the design layout; classifying the features of different types of graphics to form a plurality of sets, wherein each set is provided with a corresponding pre-compensation value; forming a corrected layout according to the pre-complement value iteration sampling points corresponding to different types of patterns, so that the error value between the developed pattern of the corrected layout and the design layout is smaller than or equal to a target value; and (5) checking the accuracy of the corrected layout, and if no error exists, manufacturing a photomask by using the corrected layout. According to the invention, the specific graph of the design chip layout is subjected to value pre-compensation according to the model data, so that the convergence speed of optical proximity correction is increased, the number of calculation iterations of sampling points is reduced, the running time is reduced, and the correction speed of the mask is increased.

Description

Method for accelerating OPC correction speed of chip layout
Technical Field
The invention relates to the technical field of semiconductors, in particular to a method for accelerating OPC correction speed of a chip layout.
Background
As the nodes of semiconductor chips become more advanced, the critical dimensions of the designed chips become smaller and smaller, the minimum dimensions are already close to the resolution limit of the lithography light source, optical diffraction phenomenon occurs when light passes through Mask patterns, distortion phenomenon occurs when patterns are formed by lithography, and the performance and yield of the chips are compromised. In order to reduce diffraction effects of the reticle, optical Proximity Correction (OPC) is required to be performed on the chip design layout prior to reticle fabrication.
The OPC correction Mask (Mask) is an OPC model based on a photoetching process, light intensity of each pattern (pattern) of a chip layout is calculated at a segmented sampling point, a pattern imaged on a photoresist by the Mask is obtained by adopting a threshold value, then the pattern is differenced with a design demand pattern (ADI Target), offset of each sampling point and the design demand pattern is obtained, the offset is multiplied by a coefficient, and the translation amount of the Mask in the vertical direction of the sampling point along each pattern edge of the chip layout is calculated for the sampling point, and the photoetching imaging pattern of the Mask on the silicon chip accords with the design demand pattern through multiple rounds of calculation and translation iteration.
Therefore, the design graph needs to be fully sampled in a segmentation way during OPC correction, and the light intensity of the sampling point is calculated and translated in multiple rounds. For advanced nodes, the critical dimension of a design chip is reduced, the density of patterns is increased, and the number of layout sampling points during OPC correction is very large. And each sampling point needs to be subjected to multiple rounds of calculation iteration to obtain a final mask correction result. The method has huge consumption of computing resources, and can seriously increase layout OPC correction time and influence product progress.
In order to solve the above problems, a novel method for accelerating the OPC correction speed of the chip layout is required.
Disclosure of Invention
In view of the above-mentioned drawbacks of the prior art, the present invention aims to provide a method for accelerating the OPC correction speed of a chip layout, which is used for solving the problem that in the prior art, the design graph needs to be fully sampled in a segmented manner during OPC correction, and the light intensity of a sampling point is calculated and translated in multiple rounds. For advanced nodes, the critical dimension of a design chip is reduced, the density of patterns is increased, and the number of layout sampling points during OPC correction is very large. And each sampling point needs to be subjected to multiple rounds of calculation iteration to obtain a final mask correction result. The method has huge consumption of computing resources, and can seriously increase layout OPC correction time and influence the progress of products.
To achieve the above and other related objects, the present invention provides a method for accelerating OPC correction speed of a chip layout, including:
step one, providing a design layout, wherein the design layout consists of a plurality of types of graphs, and line segments consisting of a plurality of sampling points are arranged according to the outline of the design layout;
classifying the features of the graphics of different types to form a plurality of sets, wherein each set is provided with a corresponding pre-compensation value;
iterating the sampling points according to the pre-complement values corresponding to the patterns of different types to form a corrected layout, so that an error value between the developed pattern of the corrected layout and the design layout is smaller than or equal to a target value;
and step four, checking the accuracy of the corrected layout, and if no error exists, manufacturing a photomask by using the corrected layout.
Preferably, the pattern type in the design layout in the first step includes a line pattern, a hole pattern, a two-dimensional pattern with regular shape, and a two-dimensional pattern with irregular shape.
Preferably, in the second step, the classification is performed according to the difference of the densities of the surrounding environments of the graph to form a plurality of sets.
Preferably, in the second step, the dense pattern, the semi-sparse pattern and the sparse pattern are formed by classifying according to the different densities of the surrounding environments of the patterns.
Preferably, the method for obtaining the pre-complement value in the second step includes: optical proximity correction model anchor, optical proximity correction model simulation, and manufacturing data for a wafer.
Preferably, the sampling points are iterated N times in the third step, and the sampling points are used for any iteration.
Preferably, the method for iterating the sampling points according to the pre-complement values corresponding to the graphics of different types in the third step includes: sequentially performing first to N iterations on the sampling point, wherein in the iterations from X-1 to X, a correction value Y= [ (Z1-Z2) +Z3 ]. Times.K of the sampling point; wherein (Z1-Z2) is the error value between the developed pattern of the X-1 th corrected pattern and the design pattern, Z3 is the pre-complement value, K is the correction coefficient, N is an integer greater than or equal to 2, X is an integer greater than or equal to 2 and X is less than or equal to N.
Preferably, the method for iterating the sampling points according to the pre-complement values corresponding to the graphics of different types in the third step includes: sequentially performing first to N iterations on the sampling point, wherein in the iterations from X-1 to X, the correction value Y= [ (Z1-Z2) ]. Times.K of the sampling point; wherein (Z1-Z2) is the error value between the developed pattern of the X-1 th corrected pattern and the design pattern, K is a correction coefficient, N is an integer greater than or equal to 2, X is an integer greater than or equal to 3 and X is less than or equal to N.
Preferably, the third step further comprises forming the corrected layout by inserting resolution auxiliary patterns.
As described above, the method for accelerating the OPC correction speed of the chip layout has the following beneficial effects:
according to the invention, the specific graph of the design chip layout is subjected to value pre-compensation according to the model data, so that the convergence speed of optical proximity correction is increased, the number of calculation iterations of sampling points is reduced, the running time is reduced, and the correction speed of the mask is increased.
Drawings
FIG. 1 is a schematic diagram of an OPC correction process in accordance with the present invention;
FIG. 2 is a graphical illustration of a selected required pre-compensation value for one embodiment;
FIG. 3 is a schematic diagram of a layout for performing the pre-compensation and SRAF addition, according to one embodiment;
FIG. 4 is a schematic diagram showing the relationship between the difference between the X direction of the mask and the target mask and the iteration number according to two correction methods of an embodiment;
FIG. 5 is a schematic diagram showing the relationship between the difference value between the Y direction of the mask and the target mask and the iteration number according to two correction methods of one embodiment;
FIG. 6 is a graph showing the relationship between the difference between the square hole diameter and the target and the iteration number for two correction methods according to one embodiment.
Detailed Description
Other advantages and effects of the present invention will become apparent to those skilled in the art from the following disclosure, which describes the embodiments of the present invention with reference to specific examples. The invention may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present invention.
Referring to fig. 1, the invention provides a method for accelerating OPC correction speed of a chip layout, comprising the following steps:
providing a design layout, wherein the design layout consists of a plurality of types of graphs (patterns), and a line segment (segment) consisting of a plurality of sampling points is arranged according to the outline of the design layout, and the line segment is usually formed by cutting edges of the design layout;
preferably, the pattern type in the design layout in the first step includes a line pattern, a hole pattern, a two-dimensional pattern with regular shape, and a two-dimensional pattern with irregular shape.
Classifying the features of the graphics of different types to form a plurality of sets, wherein each set is provided with a corresponding pre-compensation value;
preferably, in the second step, the classification is performed according to the difference of the densities of the surrounding environments of the graph to form a plurality of sets.
Preferably, in the second step, the dense pattern, the semi-sparse pattern and the sparse pattern are formed by classifying according to the different densities of the surrounding environments of the patterns.
Preferably, the method for obtaining the pre-complement value in the second step includes: optical proximity correction model anchor, optical proximity correction model simulation, and manufacturing data for a wafer.
Iterating the sampling points according to the pre-complement values corresponding to the patterns of different types to form a corrected layout, so that an error value between the developed pattern of the corrected layout and the design layout is smaller than or equal to a target value;
preferably, the sampling points are iterated N times in the third step, and the sampling points are used for any iteration.
Preferably, the method for iterating the sampling points according to the pre-complement values corresponding to the graphics of different types in the third step includes: sequentially performing first to N iterations on the sampling point, wherein in the iterations from X-1 to X, a correction value Y= [ (Z1-Z2) +Z3 ]. Times.K of the sampling point; wherein (Z1-Z2) is the error value between the developed pattern of the X-1 th corrected pattern and the design pattern, Z3 is the pre-complement value, K is the correction coefficient, N is an integer greater than or equal to 2, X is an integer greater than or equal to 2 and X is less than or equal to N.
By classifying the design layout, the invention sets a specific pre-compensation value for a specific graph in the first iteration period of OPC correction, thereby effectively reducing the iteration times of calculation and movement of the sampling point mask, accelerating the convergence speed of mask correction, finally reducing the OPC correction time of the whole layout, reducing the mask manufacturing period and accelerating the development progress of products. It should be noted that, the iteration value may be used in the subsequent iteration process according to the magnitude of the deviation, and not only in the first iteration.
Preferably, the method for iterating the sampling points according to the pre-complement values corresponding to the graphics of different types in the third step includes: sequentially performing first to N iterations on the sampling point, wherein in the iterations from X-1 to X, the correction value Y= [ (Z1-Z2) ]. Times.K of the sampling point; wherein (Z1-Z2) is the error value between the developed pattern of the X-1 th corrected pattern and the design pattern, K is a correction coefficient, N is an integer greater than or equal to 2, X is an integer greater than or equal to 3 and X is less than or equal to N.
Preferably, the third step further comprises forming the corrected layout by inserting resolution auxiliary patterns.
And step four, checking the accuracy of the corrected layout, and if no error exists, manufacturing a photomask by using the corrected layout.
Illustratively, take advanced node product M0P layer as an example:
in advanced node products, the M0P layer is used for connecting the PO layer, the M0A layer and the V0 layer, and the pattern is rectangular holes with square holes and fixed length-width ratio. Square holes occupy the major part of all patterns, and can be classified into a compact (density) pattern, a SEMI-Sparse (SEMI) pattern and a sparse (ISO) pattern according to the density of the surrounding environment of the patterns. Because the SEMI/ISO square hole is far away from other patterns, the influence of the adjacent patterns is small, and enough space is available for pre-compensation, the embodiment adopts the SEMI/ISO square hole to perform the OPC correction based on the model data value, and provides the result of the OPC correction without the invention as a comparison.
OPC correction of the pre-compensation value is carried out on the specific graph by adopting the patent:
1. and determining a pre-complement value of a specific pattern, wherein the M0P is based on an Anchor of an OPC model of a photoetching process, the square hole array is 58nm on the side, and the X/Y direction Pitch (period) is 108nm. After exposure, holes with the diameter of 50nm, namely square holes with the mask size of 58nm, are formed on the silicon wafer, wherein the diameter of the silicon wafer is 50nm, namely the mask size and the time exposure hole diameter are 8nm, and each side is 4nm different. The pre-complement value was set to 4nm per side.
2. Reading in the design layout of the chip, and screening out SEMI/ISO square holes. And selecting all square holes with the side length of 50nm of the layer design layout. Taking the center of a 50nm square hole as the center of a circle (circle 1 in fig. 2) with the radius of 250nm, selecting a square hole with no other graph contact in the circle, such as square hole A in fig. 1, of the design layout.
3. Referring to fig. 3, the layout is pre-complemented and SRAF (resolution assist feature) is added to conform to and increase the process window. The black solid graph is a chip design layout, and the black hollow graph is SRAF.
4. And 3, performing OPC correction on the chip design layout after the step 3 is completed, and forming a set 1 by the SEMI/ISO square holes selected in the step 2 and forming a set 2 by the rest graphics. To ensure that the OPC corrections are satisfactory, the number of graphic OPC correction iterations for all sets is 16. And in the first iteration, carrying out unilateral pre-compensation value 4nm on all graphs of the set 1, carrying out normal OPC correction on all graphs of the set 2, carrying out normal OPC correction on the set 1 and the set 2 in the 2 nd-16 th iteration, finally obtaining an OPC corrected mask, and outputting the OPC corrected mask and a corresponding simulation value.
5. And checking the correction result, and completing OPC correction of the chip layout without errors.
OPC correction of the pre-complement value for the specific graph is not adopted in the patent:
1. and performing pre-compensation and SRAF addition on the chip layout to be designed.
2. And (3) performing OPC correction on the chip design layout after the step 1, and outputting mask plates subjected to OPC iterative correction each time and simulation values corresponding to the mask plates in order to ensure that OPC correction meets the requirements, wherein the iteration times of the OPC correction of all the graphics are 16.
3. And (5) checking an OPC correction result, and completing OPC correction of the chip layout without errors.
The comparison of the OPC correction of the pre-compensation value for the specific graph by the patent and the OPC correction of the pre-compensation value for the specific graph without the patent is shown in fig. 4 to 6, so that the OPC correction of the pre-compensation value for the specific graph by the patent can be seen, the iteration required times are reduced, and the correction speed of the mask plate is accelerated.
It should be noted that, the illustrations provided in the present embodiment merely illustrate the basic concept of the present invention by way of illustration, and only the components related to the present invention are shown in the drawings and are not drawn according to the number, shape and size of the components in actual implementation, and the form, number and proportion of the components in actual implementation may be arbitrarily changed, and the layout of the components may be more complex.
In summary, the method and the device for correcting the mask plate have the advantages that the convergence speed of optical proximity correction is increased, the number of calculation iterations of sampling points is reduced, the running time is reduced, and the correction speed of the mask plate is increased by carrying out the value complementation on the specific graph of the design chip layout according to the model data. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The above embodiments are merely illustrative of the principles of the present invention and its effectiveness, and are not intended to limit the invention. Modifications and variations may be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the invention. Accordingly, it is intended that all equivalent modifications and variations of the invention be covered by the claims, which are within the ordinary skill of the art, be within the spirit and scope of the present disclosure.

Claims (9)

1. A method for accelerating OPC correction speed of chip layout is characterized by at least comprising the following steps:
step one, providing a design layout, wherein the design layout consists of a plurality of types of graphs, and line segments consisting of a plurality of sampling points are arranged according to the outline of the design layout;
classifying the features of the graphics of different types to form a plurality of sets, wherein each set is provided with a corresponding pre-compensation value;
iterating the sampling points according to the pre-complement values corresponding to the patterns of different types to form a corrected layout, so that an error value between the developed pattern of the corrected layout and the design layout is smaller than or equal to a target value;
and step four, checking the accuracy of the corrected layout, and if no error exists, manufacturing a photomask by using the corrected layout.
2. The method for accelerating the OPC correction speed of the chip layout as claimed in claim 1, wherein the method comprises the steps of: the pattern types in the design layout in the first step comprise line patterns, hole patterns, two-dimensional patterns with regular shapes and two-dimensional patterns with irregular shapes.
3. The method for accelerating the OPC correction speed of the chip layout as claimed in claim 1, wherein the method comprises the steps of: and step two, classifying according to the different densities of the surrounding environments of the graph to form a plurality of sets.
4. The method for accelerating OPC correction of chip layout as claimed in claim 3, wherein: and step two, classifying according to the different densities of the surrounding environments of the patterns to form a compact pattern, a semi-sparse pattern and a sparse pattern.
5. The method for accelerating the OPC correction speed of the chip layout as claimed in claim 1, wherein the method comprises the steps of: the method for acquiring the pre-compensation value in the second step comprises the following steps: optical proximity correction model anchor, optical proximity correction model simulation, and manufacturing data for a wafer.
6. The method for accelerating the OPC correction speed of the chip layout as claimed in claim 1, wherein the method comprises the steps of: and step three, iterating the sampling points for N times, wherein the sampling points are used for iterating at any time.
7. The method for accelerating the OPC correction speed of a chip layout as claimed in claim 5, wherein: the method for iterating the sampling points according to the pre-complement values corresponding to the graphics of different types in the third step comprises the following steps: sequentially performing first to N iterations on the sampling point, wherein in the iterations from X-1 to X, a correction value Y= [ (Z1-Z2) +Z3 ]. Times.K of the sampling point; wherein (Z1-Z2) is the error value between the developed pattern of the X-1 th corrected pattern and the design pattern, Z3 is the pre-complement value, K is the correction coefficient, N is an integer greater than or equal to 2, X is an integer greater than or equal to 2 and X is less than or equal to N.
8. The method for accelerating the OPC correction speed of a chip layout as claimed in claim 5, wherein: the method for iterating the sampling points according to the pre-complement values corresponding to the graphics of different types in the third step comprises the following steps: sequentially performing first to N iterations on the sampling point, wherein in the iterations from X-1 to X, the correction value Y= [ (Z1-Z2) ]. Times.K of the sampling point; wherein (Z1-Z2) is the error value between the developed pattern of the X-1 th corrected pattern and the design pattern, K is a correction coefficient, N is an integer greater than or equal to 2, X is an integer greater than or equal to 3 and X is less than or equal to N.
9. The method for accelerating the OPC correction speed of the chip layout as claimed in claim 1, wherein the method comprises the steps of: and step three, forming the corrected layout by a method of inserting a resolution auxiliary graph.
CN202310473250.6A 2023-04-27 2023-04-27 Method for accelerating OPC correction speed of chip layout Pending CN116520633A (en)

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