CN112415864B - Method for determining OPC minimum segmentation length - Google Patents

Method for determining OPC minimum segmentation length Download PDF

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CN112415864B
CN112415864B CN202011325662.8A CN202011325662A CN112415864B CN 112415864 B CN112415864 B CN 112415864B CN 202011325662 A CN202011325662 A CN 202011325662A CN 112415864 B CN112415864 B CN 112415864B
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opc
test pattern
length
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CN112415864A (en
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牛东华
张辰明
何大权
魏芳
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Shanghai Huali Integrated Circuit Manufacturing Co Ltd
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Shanghai Huali Integrated Circuit Manufacturing Co Ltd
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    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70—Microphotolithographic exposure; Apparatus therefor
    • G03F7/70425—Imaging strategies, e.g. for increasing throughput or resolution, printing product fields larger than the image field or compensating lithography- or non-lithography errors, e.g. proximity correction, mix-and-match, stitching or double patterning
    • G03F7/70433—Layout for increasing efficiency or for compensating imaging errors, e.g. layout of exposure fields for reducing focus errors; Use of mask features for increasing efficiency or for compensating imaging errors
    • G03F7/70441—Optical proximity correction [OPC]
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
    • G03F1/36—Masks having proximity correction features; Preparation thereof, e.g. optical proximity correction [OPC] design processes
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70—Microphotolithographic exposure; Apparatus therefor
    • G03F7/70483—Information management; Active and passive control; Testing; Wafer monitoring, e.g. pattern monitoring
    • G03F7/70491—Information management, e.g. software; Active and passive control, e.g. details of controlling exposure processes or exposure tool monitoring processes
    • G03F7/70508—Data handling in all parts of the microlithographic apparatus, e.g. handling pattern data for addressable masks or data transfer to or from different components within the exposure apparatus

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Abstract

The invention provides a method for determining OPC minimum dividing length, which is characterized in that different graph side dividing lengths are respectively set for a series of test graphs, the difference between model-based OPC simulation values of the test graphs and wafer optical resistance CD data is calculated, then root mean square is calculated, and when the root mean square has a minimum value, the corresponding graph dividing length is the test graph side minimum dividing length. The method solves the problem that the OPC correction precision is not high due to the fact that target layout graphs cannot be reasonably segmented in model-based OPC, and improves the product yield.

Description

Method for determining OPC minimum segmentation length
Technical Field
The invention relates to the technical field of semiconductors, in particular to a method for determining an OPC minimum division length.
Background
With the continuous reduction of process nodes, OPC (Optical Proximity Correction) has become an indispensable link for improving yield in the semiconductor manufacturing process. In the layout publishing process, in order to eliminate the figure distortion phenomenon caused by the optical proximity effect, OPC correction needs to be carried out on the layout, and then the influence of the optical proximity effect on the figure is compensated. Currently, there are two main ways for OPC correction: rule-based OPC and model-based OPC. Model-based OPC correction has been widely applied in the process of publishing a mask and enables the finally obtained graph on the silicon wafer to be as consistent as possible with the design layout.
In consideration of the continuous reduction of the size of the graph and the gradual increase of the complexity of the graph, the model-based OPC correction precision needs to be higher and higher to further meet the process requirement, so that the original design layout is presented on a silicon chip as much as possible, and process weaknesses such as disconnection, connection or Edge Placement Error (common EPE, edge correction Error) and the like cannot occur. At this time, it is an indispensable loop to reasonably cut or segment the edge of the target layout graph, which is an important step in the model-based OPC correction process, and moreover, the reasonable cutting or segmentation of the edge of the target layout graph also has a great influence on the OPC correction accuracy. Ideally, if the mask making capability allows, it is best to reduce the pattern edge cutting length as much as possible, so that the obtained OPC correction accuracy is sufficient to meet the process requirements of smaller nodes. Considering the limitation of mask making capacity, the division length is not limited, but the mask can deviate from the original OPC correction result, so the minimum division length of the pattern edge must be limited.
Disclosure of Invention
In view of the above-mentioned shortcomings of the prior art, the present invention aims to provide a method for determining the minimum division length of OPC, which is used to solve the problem that the model-based OPC in the prior art cannot reasonably segment the target layout pattern, thereby resulting in low OPC correction accuracy.
To achieve the above and other related objects, the present invention provides a method for determining an OPC minimum partition length, the method comprising at least the steps of:
step one, determining a target layer and an ADI target value corresponding to the target layer as an ADI target;
step two, obtaining the value range of the length segment value and the value range of the width or space segment value based on the test graph after OPC treatment according to the ADI target value; obtaining m length segmentation values of the test pattern by changing x step length within the value range of the length segmentation values; obtaining n width or spacing segment values of the test pattern by y step change in the value range of the width or spacing segment value;
step three, using the m length segment values and the n width or spacing segment values to form m × n test patterns, and performing model-based OPC simulation on the m × n test patterns to obtain a CD simulation value of each segmented area of each test pattern;
fourthly, obtaining a test pattern mask according to the m x n test patterns;
fifthly, exposing and developing the wafer by using the test pattern mask to obtain the CD values of the photoresist patterns on the m × n wafers;
step six, respectively calculating the difference between the CD simulation value of each test pattern in the m x n test patterns and the corresponding CD value of the photoresist pattern on the wafer; obtaining m + n CD difference values, and calculating a root mean square according to the m + n CD difference values; and the length segmentation value of the test pattern corresponding to the minimum root mean square is the minimum segmentation length of the test pattern.
Preferably, the ADI target value in the first step is a pattern line width.
Preferably, the ADI target value in step one is a pattern pitch.
Preferably, the value range of the length segment value of the test pattern in the second step is 1/2ADI target-3/4 ADI target; the value range of the width segment value of the test pattern is 1/4ADI target-3/2 ADI target.
Preferably, the value range of the length segment value of the test pattern in the second step is 1/2ADI target-3/4 ADI target; the range of the interval segmentation value of the test pattern is 1/4ADI target-3/2 ADI target.
Preferably, the CD simulation value obtained in step three for each segmented region of the test pattern is a line width simulation value of each segmented region of the test pattern.
Preferably, the CD simulation value obtained in step three for each segmented region of the test pattern is a pattern pitch simulation value for each segmented region of the test pattern.
Preferably, the CD value of the photoresist patterns on the m × n wafers obtained in the fifth step is the line width value of the photoresist patterns on the m × n wafers.
Preferably, the CD value of the photoresist patterns on the m × n wafers obtained in the fifth step is a pitch value of the photoresist patterns on the m × n wafers.
Preferably, said ADI target value ADI target in step one is 81nm.
Preferably, the segmentation value of the length of the test pattern obtained in the second step based on the OPC treatment ranges from 40nm to 60nm.
Preferably, the value range of the width segment value of the test pattern obtained in the second step based on the OPC treatment is 20nm to 120nm.
Preferably, the pitch segmentation value based on the test pattern after OPC processing obtained in the second step has a value range of 20nm to 120nm.
Preferably, the step size of x in the value range of the length segment value in the step two is 2nm.
Preferably, the y step size in the value range of the width segment value in the second step is 5nm.
Preferably, the y step size in the value range of the spacing segmentation value in the second step is 5nm.
As described above, the method for determining the OPC minimum partition length according to the present invention has the following advantages: the invention sets different graph edge dividing lengths for a series of test graphs respectively, calculates the difference between the model-based OPC simulation value of the test graphs and the wafer optical resistance CD data, and then calculates the root mean square, wherein the corresponding graph dividing length is the minimum dividing length of the test graph edge when the root mean square has the minimum value. The method solves the problem that the OPC correction precision is not high due to the fact that target layout graphs cannot be reasonably segmented in model-based OPC, and improves the product yield.
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FIG. 1a and FIG. 1b are schematic diagrams showing two different test patterns according to a first embodiment of the present invention;
FIG. 2a is a graph illustrating model-based OPC simulation of the test pattern of FIG. 1a according to the present invention;
FIG. 2b is a graph illustrating model-based OPC simulation of the test pattern of FIG. 1b in accordance with the present invention;
FIGS. 3a and 3b are schematic diagrams showing two different test patterns according to a second embodiment of the present invention;
FIG. 4a is a graph illustrating model-based OPC simulation of the test pattern of FIG. 3a according to the present invention;
FIG. 4b shows a model-based OPC simulation of the test pattern of FIG. 3b in accordance with the present invention;
FIG. 5 is a linear graph showing the difference between the CD simulation value of the test pattern corresponding to the length segment value of 48nm and the CD value of the photoresist pattern on the wafer corresponding to the test pattern;
FIG. 6 is a graphical representation of RMS values for different length segment values according to the present invention;
FIG. 7 is a flowchart illustrating a method for determining an OPC minimum segmentation length according to the present invention.
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
Please refer to fig. 1a to fig. 7. It should be noted that the drawings provided in this embodiment are only for schematically illustrating the basic idea of the present invention, and the components related to the present invention are only shown in the drawings and not drawn according to the number, shape and size of the components in actual implementation, and the form, quantity and proportion of each component in actual implementation may be arbitrarily changed, and the component layout may be more complicated.
Example one
Referring to fig. 7, fig. 7 is a flowchart illustrating a method for determining an OPC minimum segment length according to the present invention. The method at least comprises the following steps:
step one, determining an object layer and an ADI target value (CD of a developed photoresistance pattern) corresponding to the object layer as an ADI target; further, the ADI target value in the first step of this embodiment is a line width of a pattern (line width of a developed photoresist pattern). Still further, the ADI target value ADI target in the first step of this embodiment is 81nm.
Step two, obtaining the value range of the length segment value and the value range of the width or space segment value based on the test graph after OPC treatment according to the ADI target value; obtaining m length segment values of the test pattern by changing x step length within the value range of the length segment value; obtaining n width or spacing segment values of the test pattern by y step change in the value range of the width or spacing segment value; further, in the second step of this embodiment, a value range of a length segment value and a value range of a width segment value based on the test pattern after the OPC processing are obtained according to the ADI target value. The test pattern in the second step refers to a test pattern formed after the original pattern is subjected to OPC treatment.
Further, the value range of the length segment value of the test pattern in the second step of this embodiment is 1/2ADI target-3/4 ADI target; the value range of the width segment value of the test pattern is 1/4ADI target-3/2 ADI target. Further, the value range of the length segmentation value of the test pattern based on the OPC processing obtained in step two of this embodiment is 40nm to 60nm. Further, the value range of the width segment value of the test pattern obtained in the second step of this embodiment based on the OPC processing is 20nm to 120nm. Further, the step size of x in the value range of the length segment value in step two of this embodiment is 2nm. Further, the y step length in the value range of the width segment value in the second step of this embodiment is 5nm. Therefore, in the second step of this embodiment, the length segment values of 11 test patterns are obtained within the range of the length segment values with a 2nm step change; and obtaining 21 width segmentation values of the test pattern by changing the width or spacing segmentation values in 5nm steps within the value range of the width or spacing segmentation values.
Step three, using the m length segment values and the n width or spacing segment values to form m × n test patterns, and performing model-based OPC simulation on the m × n test patterns to obtain a CD simulation value of each segmented area of each test pattern; further, the m length segment values and the n width segment values are used for forming m × n test patterns, and model-based OPC simulation is performed on the m × n test patterns to obtain a CD simulation value of a segmented area of each test pattern; in the third step of this embodiment, the CD simulation value obtained for the segmented region of each test pattern is the line width simulation value of the segmented region of each test pattern.
As shown in fig. 1a and 1b, fig. 1a and 1b are schematic structural diagrams of two different test patterns according to a first embodiment of the present invention, respectively. Wherein, the line Width (Width) of the graph 1a becomes smaller 201L after the graph is segmented min And 202L min The lengths of the two lines represent the length-segmented value of the graph, while the width-segmented value of the graph (segmented region, i.e., 201L) min And 202L min Width between two lines) becomes smaller than that of the original pattern. In FIG. 1b, the line Width (Width) becomes larger after the graph is segmented, and 201L in FIG. 1b min And 202L min The length of the two lines represents the length-segmented value of the graph, while the width-segmented value of the graph (segmented region, i.e., 201L) min And 202L min Width between two lines) becomes larger than the Width of the original figure.
FIG. 2a is a graph illustrating model-based OPC simulation of the test pattern of FIG. 1a according to the present invention, as shown in FIGS. 2a and 2 b; FIG. 2b shows a model-based OPC simulation of the test pattern of FIG. 1b in accordance with the present invention. In the third step of this embodiment, the CD simulation value obtained for each segmented region of the test pattern is the line width simulation value of each segmented region of the test pattern. The simulated linewidth value Sim CD in fig. 2a corresponds to the Width of the segmented area of the test pattern in fig. 1 a; the simulated value of the line Width Sim CD in fig. 2b corresponds to the Width of the segmented area of the test pattern in fig. 1 b.
Fourthly, obtaining a test pattern mask according to the m x n test patterns; fig. 1a and fig. 1b are the obtained test patterns, and the present invention exemplarily shows 2 test patterns. And then, manufacturing m-n test patterns on a mask plate to form the test pattern mask plate.
Fifthly, exposing and developing the wafer by using the test pattern mask to obtain the CD values of the photoresist patterns on the m × n wafers; further, the CD value of the photoresist patterns on m × n wafers obtained in step five of this embodiment is the line width value (the width of the segmented region pattern) of the photoresist patterns on m × n wafers. Step six, respectively calculating each test in the m x n test patternsThe difference between the CD simulation value of the pattern and the corresponding CD value of the photoresist pattern on the wafer; obtaining m × n CD differences, where the CD differences are CD error as shown in fig. 5, fig. 5 is a linear graph of the difference between the CD simulation value of the test pattern corresponding to the length segment value of 48nm and the CD value of the photoresist pattern on the Wafer corresponding to the test pattern, where CD error = Wafer CD-Sim CD, where Wafer CD is the CD value of the photoresist pattern on the Wafer, and Sim CD is the CD simulation value of the test pattern corresponding to the Wafer CD. Then, a root-mean-square RMS is calculated according to the m-n CD difference values (CD error), when each m takes a different value, n CD errors (a CD error graph) are obtained, a root-mean-square is calculated, finally m RMS values can be obtained, and m corresponding to the minimum value is taken.
Figure BDA0002794191770000051
When the root mean square RMS is minimum, the corresponding length segment value of the test pattern is the minimum segmentation length of the test pattern. As shown in fig. 6, fig. 6 is a graphical representation of RMS values corresponding to different length segment values in the present invention. As can be seen from fig. 6, in this embodiment, when the root mean square RMS is minimum, the length segment value of the corresponding test pattern is 48nm, which is the minimum segment length of the test pattern.
Example two
The present invention provides a method for determining the minimum OPC segmentation length, as shown in fig. 7, and fig. 7 is a flowchart illustrating the method for determining the minimum OPC segmentation length according to the present invention. The method at least comprises the following steps:
step one, determining an object layer and an ADI target value (CD of a developed photoresistance pattern) corresponding to the object layer as an ADI target; further, the ADI target value in the first step of this embodiment is a pattern pitch (a distance between two adjacent photoresist patterns after development). Further, the ADI target value ADI target in the first step of this embodiment is 81nm.
Step two, obtaining the value range of the length segment value and the value range of the width or space segment value based on the test graph after OPC treatment according to the ADI target value; obtaining m length segment values of the test pattern by changing x step length within the value range of the length segment value; obtaining n width or spacing segment values of the test pattern by y step change in the value range of the width or spacing segment value; further, in the present embodiment, a second step obtains a value range of a length segment value and a value range of a space segment value based on the test pattern after the OPC processing according to the ADI target value. The test pattern in the second step refers to a test pattern formed after the original pattern is subjected to OPC treatment.
Further, the value range of the length segment value of the test pattern in the second step of this embodiment is 1/2ADI target-3/4 ADI target; the range of the interval segmentation value of the test pattern is 1/4ADI target-3/2 ADI target. Further, the value range of the length segmentation value of the test pattern based on the OPC processing obtained in step two of this embodiment is 40nm to 60nm. Further, the pitch segmentation value of the test pattern obtained in the second step of this embodiment based on the OPC processing ranges from 20nm to 120nm. Further, the step size of x in the value range of the length segment value in step two of this embodiment is 2nm. Further, the y step size in the value range of the pitch segmentation value in the second step of this embodiment is 5nm. Therefore, in the second step of this embodiment, the length segment values of 11 test patterns are obtained within the range of the length segment values with a 2nm step change; and obtaining the spacing segmentation values of 21 test patterns in a 5nm step change within the value range of the width or spacing segmentation values.
Thirdly, the m length segmentation values and the n spacing segmentation values are used for forming m x n test patterns, and model-based OPC simulation is carried out on the m x n test patterns to obtain a CD simulation value of each segmented area of the test patterns; further, the CD simulation value obtained in the third step of this embodiment for the segmented region of each test pattern is a simulation value of an interval between two adjacent patterns in each test pattern.
As shown in fig. 3a and fig3b, fig. 3a and 3b are schematic structural diagrams respectively illustrating two different test patterns according to a second embodiment of the present invention. In FIG. 3a, the line width of the pattern becomes larger after the pattern is segmented, 203L min And 204L min The length of the two lines represents the length segmentation value of the pattern, while the pitch segmentation value of the pattern (segmented region, 203L min And 204L min The Space between two lines) becomes smaller than the Space of the original figure. In FIG. 3b, the line width of the pattern becomes smaller after the pattern is segmented, and 203L in FIG. 3b min And 204L min The lengths of the two lines represent the length segment values of the pattern, while the pitch segment values of the pattern (segmented regions, i.e., 203L) min And 204L min The Space between two lines) becomes larger than the Space of the original figure.
FIG. 4a is a graph illustrating model-based OPC simulations of the test patterns of FIG. 3a in accordance with the present invention, as shown in FIGS. 4a and 4 b; FIG. 4b shows a model-based OPC simulation of the test pattern of FIG. 3b in accordance with the present invention. In the third step of this embodiment, the CD simulation value obtained for the segmented region of each test pattern is a pattern pitch simulation value of the segmented region of each test pattern. The simulation value of pattern pitch SimCD in fig. 4a corresponds to the pattern pitch Space of the segmented region of the test pattern in fig. 3 a; the simulation value of pattern pitch SimCD in fig. 4b corresponds to the pattern pitch Space of the segmented region of the test pattern in fig. 3 b.
Fourthly, obtaining a test pattern mask plate according to the m x n test patterns; fig. 3a and 3b are the obtained test patterns, and the present invention exemplarily presents 2 test patterns. And then, manufacturing m-n test patterns on a mask plate to form the test pattern mask plate.
Fifthly, exposing and developing the wafer by using the test pattern mask to obtain the CD values of the photoresist patterns on the m × n wafers; further, the CD value of the photoresist patterns on the m × n wafers obtained in the fifth step of this embodiment is the pitch value of the photoresist patterns on the m × n wafers (i.e., the pitch between two adjacent stripe structures in the photoresist patterns on the wafers).
Step six, respectively calculating the m x n test patternsThe difference between the CD simulation value of each test pattern and the corresponding CD value of the photoresist pattern on the wafer; obtaining m × n CD differences, where the CD differences are CD error values as shown in fig. 5, where fig. 5 is a linear graph showing the difference between a CD simulation value of a test pattern corresponding to the present invention when a length segment value is equal to 48nm and a CD value of a photoresist pattern on a Wafer corresponding to the test pattern, and CD error = Wafer CD-Sim CD, where Wafer CD is a CD value of a photoresist pattern on a Wafer, and Sim CD is a CD simulation value of a test pattern corresponding to the Wafer CD. Then calculating a root mean square RMS from the m x n CD difference values (CD error),
Figure BDA0002794191770000071
when the root mean square RMS is minimum, the corresponding length segment value of the test pattern is the minimum segmentation length of the test pattern. As shown in fig. 6, fig. 6 is a graphical representation of RMS values corresponding to different length segment values in the present invention. As can be seen from fig. 6, in this embodiment, when the root mean square RMS is minimum, the length segment value of the corresponding test pattern is 48nm, which is the minimum segment length of the test pattern.
In summary, the present invention sets different graph edge dividing lengths for a series of test graphs, calculates the difference between model-based OPC simulation values of the test graphs and on-wafer photo-resist CD data, and then finds the root mean square, where the graph dividing length corresponding to the minimum value of the root mean square is the minimum dividing length of the test graph edge. The method solves the problem that the OPC correction precision is not high due to the fact that target layout graphs cannot be reasonably segmented in model-based OPC, and improves the product yield. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Those skilled in the art can modify or change the above-described embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.

Claims (14)

1. A method for determining an OPC minimum segmentation length, the method comprising at least the steps of:
step one, determining a target layer and an ADI target value corresponding to the target layer as an ADI target; the ADI target value is a pattern line width or a pattern interval;
step two, obtaining the value range of the length segment value and the value range of the width or space segment value based on the test graph after OPC treatment according to the ADI target value; obtaining m length segment values of the test pattern by changing x step length within the value range of the length segment value; obtaining n width or spacing segment values of the test pattern by y step change in the value range of the width or spacing segment value;
step three, using the m length segment values and the n width or spacing segment values to form m × n test patterns, and performing model-based OPC simulation on the m × n test patterns to obtain a CD simulation value of each segmented area of each test pattern;
fourthly, obtaining a test pattern mask according to the m x n test patterns;
fifthly, exposing and developing the wafer by using the test pattern mask to obtain the CD values of the photoresist patterns on the m × n wafers;
step six, respectively calculating the difference between the CD simulation value of each test pattern in the m x n test patterns and the corresponding CD value of the photoresist pattern on the wafer; obtaining m + n CD difference values, and calculating a root mean square according to the m + n CD difference values; and the length segmentation value of the test pattern corresponding to the minimum root mean square is the minimum segmentation length of the test pattern.
2. The method for determining OPC minimum partition lengths according to claim 1, wherein: the value range of the length segment value of the test pattern in the second step is 1/2ADI target-3/4 ADI target; the value range of the width segmentation value of the test pattern is 1/4ADI target-3/2 ADI target.
3. The method of determining OPC minimum partition lengths according to claim 1, wherein: the value range of the length segmentation value of the test pattern in the second step is 1/2ADI target-3/4 ADI target; the range of the interval segmentation values of the test pattern is 1/4ADI target-3/2 ADI target.
4. The method for determining OPC minimum partition lengths according to claim 2, wherein: and in the third step, the CD simulation value of the segmented area of each test pattern is obtained as a line width simulation value of the segmented area of each test pattern.
5. The method of determining OPC minimum partition lengths according to claim 3, wherein: and in the third step, the obtained CD simulation value of the segmented area of each test pattern is a pattern pitch simulation value of the segmented area of each test pattern.
6. The method of determining OPC minimum partition lengths according to claim 4, wherein: and fifthly, obtaining the CD values of the photoresist patterns on the m × n wafers as the line width values of the photoresist patterns on the m × n wafers.
7. The method of determining OPC minimum partition lengths according to claim 5, wherein: and fifthly, obtaining the CD values of the photoresist patterns on the m × n wafers as the spacing values of the photoresist patterns on the m × n wafers.
8. The method of determining OPC minimum partition lengths according to claim 1, wherein: the ADI target value ADI target in step one is 81nm.
9. The method of determining OPC minimum partition lengths according to claim 1, wherein: and the value range of the length segmentation value of the test graph after the OPC treatment is 40nm to 60nm.
10. The method for determining OPC minimum partition lengths according to claim 9, wherein: and the value range of the width segmentation value of the test pattern obtained in the second step after the OPC treatment is from 20nm to 120nm.
11. The method of determining OPC minimum cut lengths according to claim 10, wherein: and the value range of the interval segmentation value of the test graph obtained in the second step based on the OPC treatment is from 20nm to 120nm.
12. The method of determining OPC minimum cut lengths according to claim 11, wherein: and in the second step, the step length of x in the value range of the length segment value is 2nm.
13. The method of determining OPC minimum cut lengths according to claim 12, wherein: and in the second step, the y step length in the value range of the width segmentation value is 5nm.
14. The method of determining the OPC minimum partition length of claim 13, wherein: and the y step length in the value range of the interval segmentation value in the second step is 5nm.
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