CN116504821A - High electron mobility transistor and preparation method thereof - Google Patents
High electron mobility transistor and preparation method thereof Download PDFInfo
- Publication number
- CN116504821A CN116504821A CN202310530111.2A CN202310530111A CN116504821A CN 116504821 A CN116504821 A CN 116504821A CN 202310530111 A CN202310530111 A CN 202310530111A CN 116504821 A CN116504821 A CN 116504821A
- Authority
- CN
- China
- Prior art keywords
- metal
- layer
- magnetic medium
- medium layer
- opening
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000002360 preparation method Methods 0.000 title abstract description 7
- 239000002184 metal Substances 0.000 claims abstract description 124
- 229910052751 metal Inorganic materials 0.000 claims abstract description 124
- 230000005291 magnetic effect Effects 0.000 claims abstract description 108
- 239000000758 substrate Substances 0.000 claims abstract description 33
- 238000005530 etching Methods 0.000 claims abstract description 26
- 238000001704 evaporation Methods 0.000 claims abstract description 7
- 238000002161 passivation Methods 0.000 claims description 37
- 238000000034 method Methods 0.000 claims description 23
- 230000008569 process Effects 0.000 claims description 11
- 230000004888 barrier function Effects 0.000 claims description 8
- 239000000919 ceramic Substances 0.000 claims description 7
- 238000000231 atomic layer deposition Methods 0.000 claims description 6
- 238000000151 deposition Methods 0.000 claims description 6
- 238000004519 manufacturing process Methods 0.000 claims description 6
- 238000005468 ion implantation Methods 0.000 claims description 5
- 229910005900 GeTe Inorganic materials 0.000 claims description 4
- 238000004518 low pressure chemical vapour deposition Methods 0.000 claims description 4
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 claims description 4
- 238000012546 transfer Methods 0.000 claims description 4
- 238000002955 isolation Methods 0.000 claims description 3
- 238000001451 molecular beam epitaxy Methods 0.000 claims description 2
- 238000003980 solgel method Methods 0.000 claims 1
- 239000006185 dispersion Substances 0.000 abstract description 9
- 230000006835 compression Effects 0.000 abstract description 6
- 238000007906 compression Methods 0.000 abstract description 6
- 230000009467 reduction Effects 0.000 abstract description 5
- 239000004065 semiconductor Substances 0.000 abstract description 5
- 230000001105 regulatory effect Effects 0.000 abstract description 4
- 238000004904 shortening Methods 0.000 abstract description 2
- 238000010586 diagram Methods 0.000 description 6
- 229920002120 photoresistant polymer Polymers 0.000 description 6
- 229910002601 GaN Inorganic materials 0.000 description 5
- 230000000694 effects Effects 0.000 description 5
- 230000005684 electric field Effects 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 238000007740 vapor deposition Methods 0.000 description 4
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 230000005764 inhibitory process Effects 0.000 description 3
- 150000002739 metals Chemical class 0.000 description 3
- PXHVJJICTQNCMI-UHFFFAOYSA-N nickel Substances [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 3
- 229910002704 AlGaN Inorganic materials 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 239000010408 film Substances 0.000 description 2
- 238000003780 insertion Methods 0.000 description 2
- 230000037431 insertion Effects 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 239000007788 liquid Substances 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 238000005240 physical vapour deposition Methods 0.000 description 2
- 239000010409 thin film Substances 0.000 description 2
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 1
- 230000009471 action Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 229910052797 bismuth Inorganic materials 0.000 description 1
- JCXGWMGPZLAOME-UHFFFAOYSA-N bismuth atom Chemical compound [Bi] JCXGWMGPZLAOME-UHFFFAOYSA-N 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000005294 ferromagnetic effect Effects 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 230000002401 inhibitory effect Effects 0.000 description 1
- 229910052741 iridium Inorganic materials 0.000 description 1
- GKOZUEZYRPOHIO-UHFFFAOYSA-N iridium atom Chemical compound [Ir] GKOZUEZYRPOHIO-UHFFFAOYSA-N 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 229910052594 sapphire Inorganic materials 0.000 description 1
- 239000010980 sapphire Substances 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
- 230000001629 suppression Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/51—Insulating materials associated therewith
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28264—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being a III-V compound
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
- H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
- H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
Abstract
The invention provides a high electron mobility transistor and a preparation method thereof, which relate to the technical field of semiconductors and comprise the following steps: forming a drift layer and a magnetic medium layer on a substrate in sequence; etching the magnetic medium layer to form a source electrode opening and a drain electrode opening respectively, evaporating metal on the drift layer in the source electrode opening and the drain electrode opening to form source electrode metal and drain electrode metal respectively, wherein the source electrode metal and the drain electrode metal are in ohmic contact with the drift layer respectively. And forming a gate metal on the magnetic medium layer between the source metal and the drain metal, namely, the magnetic medium layer is positioned under the gate metal, so that the magnetic medium layer can be regulated and controlled by the voltage of the gate metal to generate induced current, and a micro-conductive channel is formed to regulate and control the current reduction phenomenon caused by a trap state, thereby effectively shortening the gate delay time, improving the power compression and high-frequency dispersion in the radio frequency application and improving the performance and the stability of the HEMT device.
Description
This application is a divisional application of the following applications: filing date: 2021, 06, 29; application number: 202110729642.5; the invention discloses a high electron mobility transistor and a preparation method thereof.
Technical Field
The invention relates to the technical field of semiconductors, in particular to a transistor with high electron mobility and a preparation method thereof.
Background
The third generation semiconductor material gallium nitride has large forbidden bandwidth (3.4 eV), high electron saturation rate (2X 107 cm/s), high breakdown electric field (1X 1010-3X 1010V/cm), higher heat conductivity, corrosion resistance and radiation resistance, becomes a current research hot spot, and has wide application prospect. In High Electron Mobility Transistor (HEMT) device applications, it was found that when the HEMT source drain voltage is high, the output current of the device is greatly reduced; the output power of the device under the RF signal is obviously reduced (RF power compression), and meanwhile, the output power density and the power additional efficiency are also reduced (RF dispersion), and the performance degradation of the device caused by the current collapse phenomenon limits the exertion of the device performance.
In order to inhibit current collapse of a GaN HEMT device and power compression in RF application, one method is to grow a SiN passivation layer to improve an interface between AlGaN and the passivation layer to regulate a trap state, the other method is to regulate a buffer layer doping state under a channel layer to regulate off-state leakage current to regulate the trap state of epitaxial growth in an epitaxial material, and a method for manufacturing a micro-leakage channel is used to regulate current reduction caused by the trap state so as to inhibit the current collapse phenomenon. However, both methods have limited current collapse inhibition effect and do not significantly inhibit high frequency dispersion.
Disclosure of Invention
The invention aims to overcome the defects in the prior art and provide a high electron mobility transistor and a preparation method thereof, so as to solve the problems that the existing transistor has poor current collapse inhibition effect and has insignificant inhibition effect on high-frequency dispersion of devices.
In order to achieve the above purpose, the technical scheme adopted by the embodiment of the invention is as follows:
in one aspect of the embodiments of the present invention, a method for preparing a transistor with high electron mobility is provided, including: forming a drift layer and a magnetic medium layer on a substrate in sequence; etching the magnetic medium layer to form a source electrode opening and a drain electrode opening respectively; evaporating metal on the drift layer in the source electrode opening and the drain electrode opening to form source electrode metal and drain electrode metal respectively, wherein the source electrode metal and the drain electrode metal are in ohmic contact with the drift layer respectively; a gate metal is formed on the magnetic dielectric layer between the source metal and the drain metal.
Optionally, etching the magnetic medium layer to form a source opening and a drain opening respectively includes: forming a passivation layer on the magnetic medium layer; the passivation layer and the magnetic medium layer are sequentially etched to form a source electrode opening and a drain electrode opening.
Optionally, after etching the magnetic medium layer to form the source opening and the drain opening, the method further includes: forming a passivation layer covering the magnetic medium layer, the source electrode opening and the drain electrode opening on the magnetic medium layer; and etching the passivation layer to form a first opening positioned in the source electrode opening and a second opening positioned in the drain electrode opening respectively, wherein the orthographic projection area of the first opening on the substrate is smaller than that of the source electrode opening on the substrate, and the orthographic projection area of the second opening on the substrate is smaller than that of the drain electrode opening on the substrate.
Optionally, forming the gate metal on the magnetic medium layer between the source metal and the drain metal includes: etching the passivation layer and terminating at the magnetic medium layer to form a gate groove on the passivation layer; and evaporating metal on the magnetic medium layer in the grid groove to form grid metal.
Optionally, sequentially forming the drift layer and the magnetic medium layer on the substrate includes: depositing a drift layer on a substrate; an active region and a passive region are defined on the drift layer through a mesa isolation process or an insulating ion implantation process; and depositing a magnetic medium layer in the active region of the drift layer.
Optionally, the magnetic medium layer has a thickness of 10nm to 100nm.
Optionally, the drift layer includes a channel layer and a barrier layer.
Optionally, the magnetic medium layer is Cr 2 Ge 2 Te 6 、Fe 3 GeTe 2 、CrI 3 One of a Bi-based ceramic film and an Ir-based ceramic film.
In another aspect of an embodiment of the present invention, there is provided a high electron mobility transistor including: a substrate; a drift layer disposed on the substrate; a magnetic medium layer disposed on the drift layer, the magnetic medium layer including a source opening and a drain opening; source and drain metals disposed within the source and drain openings, the source and drain metals being in ohmic contact with the drift layer, respectively; and a gate metal disposed on the magnetic medium layer between the source metal and the drain metal.
The beneficial effects of the invention include:
the invention provides a high electron mobility transistor and a preparation method thereof, comprising the following steps: forming a drift layer and a magnetic medium layer on a substrate in sequence; etching the magnetic medium layer to form a source electrode opening and a drain electrode opening respectively, evaporating metal on the drift layer in the source electrode opening and the drain electrode opening to form source electrode metal and drain electrode metal respectively, wherein the source electrode metal and the drain electrode metal are in ohmic contact with the drift layer respectively. And forming gate metal on the magnetic medium layer between the source metal and the drain metal, so that the magnetic medium layer can be regulated and controlled by the voltage of the gate metal to generate induced current, and a micro-conductive channel is formed to regulate and control the current reduction phenomenon caused by a trap state, thereby effectively shortening the gate delay time, improving the power compression and high-frequency dispersion in the radio frequency application and improving the performance and the stability of the HEMT device.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are needed in the embodiments will be briefly described below, it being understood that the following drawings only illustrate some embodiments of the present invention and therefore should not be considered as limiting the scope, and other related drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic flow chart of a method for preparing a high electron mobility transistor according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of a state of a high electron mobility transistor according to an embodiment of the present invention;
FIG. 3 is a schematic diagram showing a second state of a HEMT according to an embodiment of the present invention;
FIG. 4 is a third schematic diagram illustrating a state of a HEMT according to an embodiment of the invention;
FIG. 5 is a schematic diagram showing a state of a high electron mobility transistor according to an embodiment of the present invention;
fig. 6 is a schematic structural diagram of a high electron mobility transistor according to an embodiment of the present invention;
fig. 7 is a schematic diagram of a second embodiment of a high electron mobility transistor according to the present invention.
Icon: 100-a substrate; 210-a buffer layer; 220-a channel layer; 230-an interposer; 240-a barrier layer; 310-a magnetic medium layer; 410-a passivation layer; 500-inactive region; 610-source metal; 620-drain metal; 630-gate metal.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are some embodiments of the present invention, but not all embodiments of the present invention. The embodiments of the invention generally described and illustrated in the figures herein may be arranged and designed in a wide variety of different configurations.
Thus, the following detailed description of the embodiments of the invention, as presented in the figures, is not intended to limit the scope of the invention, as claimed, but is merely representative of selected embodiments of the invention. It should be noted that, under the condition of no conflict, the features of the embodiments of the present invention may be combined with each other, and the combined embodiments still fall within the protection scope of the present invention.
It should be noted that: like reference numerals and letters denote like items in the following figures, and thus once an item is defined in one figure, no further definition or explanation thereof is necessary in the following figures. In the description of the present application, it should be noted that the terms "first," "second," "third," and the like are used merely to distinguish between descriptions and are not to be construed as indicating or implying relative importance.
In one aspect of the embodiments of the present invention, a method for manufacturing a High Electron Mobility Transistor (HEMT) is provided, which can improve the current collapse effect and the high frequency dispersion suppression effect of the HEMT device through a magnetic medium layer, as shown in fig. 1, and the method includes:
s010: a drift layer and a magnetic medium layer are sequentially formed on a substrate.
As shown in fig. 3, a substrate 100 is first provided, and the substrate 100 may be a base material for carrying semiconductor integrated circuit components, such as Si, siC, sapphire, or the like. Then, a drift layer is deposited on the substrate 100, where the deposition may be performed by a Chemical Vapor Deposition (CVD), a Physical Vapor Deposition (PVD), an Atomic Layer Deposition (ALD), or the like, and the magnetic medium layer 310 is deposited on the drift layer, where the magnetic medium layer 310 may be fabricated by one or a combination of any two or three of ALD, PECVD, LPCVD, other CVD, MBE, transfer (tearing, electrochemical transfer), sol-gel, or the like, which is not limited in this application, and may be specifically and reasonably selected according to practical requirements. The drift layer may be two or more layers, which should be reasonably selected in connection with device requirements, and is not limited by the present application, and of course, those skilled in the art should appreciate that the drift layer should include at least the channel layer 220 and the barrier layer 240, so that a conductive channel having a heterojunction can be formed.
S020: and etching the magnetic medium layer to form a source electrode opening and a drain electrode opening respectively.
As shown in fig. 5, the magnetic medium layer 310 is etched by dry etching, which may be to open two openings on the magnetic medium layer 310 to serve as a source opening and a drain opening, respectively, so that the drift layer under the magnetic medium layer 310 is exposed in the source opening and the drain opening, respectively.
S030: and evaporating metal on the drift layer in the source electrode opening and the drain electrode opening to form source electrode metal and drain electrode metal respectively, wherein the source electrode metal and the drain electrode metal are in ohmic contact with the drift layer respectively.
As shown in fig. 5, metal is deposited in the source opening and the drain opening on the magnetic medium layer 310, so that a source metal 610 in ohmic contact with the drift layer is formed in the source opening, and a drain metal 620 in ohmic contact with the drift layer is formed in the drain opening, and when the source metal 610 and the drain metal 620 are formed in the same step, the source metal 610 and the drain metal 620 may be stacked metals, for example, ti/Au.
S040: a gate metal is formed on the magnetic dielectric layer between the source metal and the drain metal.
As shown in fig. 6 or fig. 7, after the source metal 610 and the drain metal 620 are fabricated in S030, the magnetic dielectric layer 310 is located between the source metal 610 and the drain metal 620, and in order to form a device with a gate control function, a gate is fabricated on the magnetic dielectric layer 310 between the source metal 610 and the drain metal 620, at this time, the source metal 610, the drain metal 620 and the gate metal 630 may be effectively isolated by using the magnetic dielectric layer 310, that is, a stacked structure of the drift layer/the magnetic dielectric layer 310/the gate metal 630 is formed, so that the magnetic dielectric layer 310 is located between the drift layer and the gate metal 630, and in this state, the magnetic dielectric layer 310 may be subjected to the control of the gate voltage, that is, it operates in an environment of a variable electric field. When the radio frequency magnetic field is introduced, the magnetic medium layer 310 generates induced current under the magnetic field, so that a micro-conductive channel is formed, current collapse caused by the inherent trap state of the device is counteracted, the current reduction phenomenon caused by the trap state is regulated and controlled, the gate delay time is effectively shortened, the power compression and high-frequency dispersion in radio frequency application are improved, and the performance and stability of the HEMT device are improved.
In embodiments of the present application, magnetic medium layer 310 may be Cr 2 Ge 2 Te 6 Ferromagnetic thin film of Fe 3 GeTe 2 、CrI 3 Or bismuth Bi-based or iridium Ir-based ceramic thin films, the thickness of the magnetic medium layer 310 can be 10nm to 100nm, such as 30nm, 50nm, 70nm, 90nm, etc., so that when a radio frequency signal is introduced, an alternating electric field is generated, a magnetic field is further generated, the magnetic medium layer 310 generates induced current under the action of the magnetic field, and current collapse caused by the inherent trap state of a GaN device is counteracted, thereby achieving the effect of inhibiting high-frequency dispersion and power collapse of the device.
Further, the gate metal 630 may be reasonably selected based on the barrier layer 240 and the channel layer 220 in the drift layer, which should have a larger work function relative to the barrier layer 240 and the channel layer 220 to ensure that electrons in the channel of the gate region can be depleted by the difference in work functions between the two. For example, the gate metal 630 may be Ni, nickel-based oxide, or other material, and may be low or high temperature or formed by oxidizing a metal material.
Alternatively, as shown in fig. 2 to 7, the drift layer may include a buffer layer 210, a channel layer 220, an insertion layer 230, and a barrier layer 240 sequentially formed on the substrate 100, wherein the buffer layer 210 may be GaN, the channel layer 220 may be GaN, the insertion layer 230 may be AlN, and the barrier layer 240 may be AlGaN.
Optionally, in order to make the semiconductor device have better performance, when the drift layer and the magnetic medium layer 310 are fabricated through S010, as shown in fig. 2, the drift layer is deposited on the substrate 100, then the passive region 500 is formed on the drift layer through a mesa isolation process or an insulating ion implantation process, and meanwhile, an active region is also defined, where the passive region 500 may be located at the periphery of the active region, and then, when the magnetic medium layer 310 is fabricated, may be fabricated in the active region, and at the same time, the corresponding source metal 610, drain metal 620 and gate metal 630 are also located in the active region.
The following will take an insulating ion implantation process as an example:
as shown in fig. 2, a photoresist may be coated on the drift layer, in order to make the coating more uniform, spin coating may be further adopted, then the device coated with the photoresist is subjected to soft baking, edge photoresist removing, alignment, exposure, development, hard baking, and other steps, an opening is opened on the photoresist, at this time, the drift layer located below the photoresist is correspondingly leaked out of the opening, and then insulating ions are implanted into the drift layer in the opening by adopting an insulating ion implantation process, so that a passive region 500 is formed in the region of the drift layer into which the insulating ions are implanted, and meanwhile, the region which is shielded by the photoresist and is not implanted is used as an active region.
Alternatively, in order to provide good protection for the device, the passivation layer 410 may be further fabricated on the magnetic medium layer 310, where the passivation layer 410 may be fabricated in various forms, and two embodiments thereof will be schematically illustrated by way of example below:
one of them is: when the source opening and the drain opening are formed by etching the magnetic medium layer 310 through S020, as shown in fig. 4, the passivation layer 410 may be deposited on the magnetic medium layer 310, then two openings are formed on the passivation layer 410 by etching the passivation layer 410, the magnetic medium layer 310 is exposed in the two openings, and then the exposed magnetic medium layer 310 is etched in the two openings, so that two openings are formed on the magnetic medium layer 310, the two openings on the passivation layer 410 and the two openings on the magnetic medium layer 310 are respectively in one-to-one correspondence, so that the source opening and the drain opening shown in fig. 5 are formed, so that the source metal 610 is conveniently manufactured in the source opening and the drain metal 620 is conveniently manufactured in the drain opening through S030. The passivation layer 410 may be deposited using one or a combination of any two or three processes in ALD, PECVD, LPCVD.
In this embodiment, as shown in fig. 6, the passivation layer 410 may be continuously etched and terminated at the magnetic dielectric layer 310 when the gate metal 630 is fabricated, so that a reasonable etching liquid or etching gas should be selected during etching in order to have a high etching selectivity when the passivation layer 410 is etched and terminated at the magnetic dielectric layer 310. A gate trench is formed on the passivation layer 410 by etching, the magnetic dielectric layer 310 under the passivation layer 410 is exposed in the gate trench, and then a gate metal 630 is formed in the gate trench by photolithography, vapor deposition of metal, lift-off of metal, or the like, thereby forming a device structure in which the passivation layer 410 is located above the magnetic dielectric layer 310.
Another of them is: before depositing the passivation layer 410 on the magnetic medium layer 310, as shown in fig. 7, a source opening and a drain opening are formed on the magnetic medium layer 310 through an etching process, and then the passivation layer 410 is deposited on the magnetic medium layer 310, and the passivation layer 410 covers the magnetic medium layer 310, the source opening and the drain opening. A first opening is formed on the passivation layer 410 located in the source opening by etching, a second opening is formed on the passivation layer 410 located in the drain opening such that an opening area of the first opening is smaller than an opening area of the source opening, an opening area of the second opening is smaller than an opening area of the drain opening, that is, an orthographic projection area of the first opening on the substrate 100 is smaller than an orthographic projection area of the source opening on the substrate 100, an orthographic projection area of the second opening on the substrate 100 is smaller than an orthographic projection area of the drain opening on the substrate 100, and then metal is evaporated in the first opening and the second opening, respectively, to form the source metal 610 and the drain metal 620. The passivation layer 410 may be deposited using one or a combination of any two or three processes in ALD, PECVD, LPCVD.
In this embodiment, as shown in fig. 7, when the gate metal 630 is fabricated, the passivation layer 410 above the magnetic dielectric layer 310 may be etched and terminated at the magnetic dielectric layer 310, so that a reasonable etching liquid or etching gas should be selected during etching to enable a higher etching selectivity when the passivation layer 410 is etched and terminated at the magnetic dielectric layer 310. A gate trench is formed on the passivation layer 410 by etching, the magnetic dielectric layer 310 under the passivation layer 410 is exposed in the gate trench, and then a gate metal 630 is formed in the gate trench by photolithography, vapor deposition of metal, lift-off of metal, or the like, thereby forming a device structure in which the passivation layer 410 is located above the magnetic dielectric layer 310.
In another aspect of an embodiment of the present invention, there is provided a high electron mobility transistor, as shown in fig. 6 or 7, including: a substrate 100; the drift layer and the magnetic medium layer 310 are sequentially disposed on the substrate 100, a source opening and a drain opening are formed in the magnetic medium layer 310, then a source metal 610 and a drain metal 620 are formed by vapor deposition of metal in the source opening and the drain opening, and the source metal 610 and the drain metal 620 respectively form ohmic contact with the drift layer. Then, a gate metal 630 is formed on the magnetic medium layer 310 between the source metal 610 and the drain metal 620 by vapor deposition, so as to form an active device with a gate control function, and since the magnetic medium layer 310 is located below the gate metal 630, the magnetic medium layer 310 is controlled by the voltage of the gate metal 630, i.e. the magnetic medium layer 310 works under a variable electric field environment. When the radio frequency magnetic field is introduced, the magnetic medium layer 310 generates induced current under the magnetic field, so that a micro-conductive channel is formed, current collapse caused by the inherent trap state of the device is counteracted, current reduction phenomenon caused by the trap state is regulated and controlled, gate delay time is effectively shortened, power compression and high-frequency dispersion in radio frequency application are improved, and performance and stability of the HEMT device are improved.
The above description is only of the preferred embodiments of the present invention and is not intended to limit the present invention, but various modifications and variations can be made to the present invention by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (10)
1. A high electron mobility transistor, comprising:
a substrate;
a drift layer disposed on the substrate;
a magnetic medium layer disposed on the drift layer;
the source electrode metal and the drain electrode metal are respectively in ohmic contact with the drift layer, and the magnetic medium layer is respectively arranged at intervals with the source electrode metal and the drain electrode metal;
a gate metal disposed on a magnetic medium layer between the source metal and the drain metal, the magnetic medium layer being in contact with the drift layer and the gate metal, respectively, the magnetic medium layer being Cr 2 Ge 2 Te 6 、Fe 3 GeTe 2 、CrI 3 One of a Bi-based ceramic film and an Ir-based ceramic film.
2. The high electron mobility transistor of claim 1 wherein the magnetic medium layer has a thickness of 10nm to 100nm.
3. The high electron mobility transistor of claim 1 wherein the drift layer comprises a channel layer and a barrier layer.
4. The high electron mobility transistor of claim 1 wherein a passivation layer is disposed between the magnetic dielectric layer and the source metal and between the magnetic dielectric layer and the drain metal.
5. The high electron mobility transistor of claim 1, wherein an active region and a non-active region are defined on the drift layer, the non-active region being located at a periphery of the active region, the magnetic medium layer, the source metal, the drain metal, and the gate metal being located at the active region.
6. A method of manufacturing a high electron mobility transistor, the method comprising:
forming a drift layer and a magnetic medium layer on a substrate in sequence;
etching the magnetic medium layer to form a source electrode opening and a drain electrode opening respectively;
evaporating metal on the drift layer in the source electrode opening and the drain electrode opening to form source electrode metal and drain electrode metal respectively, wherein the source electrode metal and the drain electrode metal are in ohmic contact with the drift layer respectively, and the magnetic medium layer is arranged at intervals with the source electrode metal and the drain electrode metal respectively;
forming a gate metal on a magnetic medium layer between the source metal and the drain metal, wherein the magnetic medium layer is respectively contacted with the drift layer and the gate metal, and the magnetic medium layer is Cr 2 Ge 2 Te 6 、Fe 3 GeTe 2 、CrI 3 One of a Bi-based ceramic film and an Ir-based ceramic film.
7. The method of manufacturing a high electron mobility transistor of claim 6, wherein after said etching said magnetic dielectric layer to form a source opening and a drain opening, respectively, said method further comprises:
forming a passivation layer covering the magnetic medium layer, the source electrode opening and the drain electrode opening on the magnetic medium layer;
and etching the passivation layer to form a first opening positioned in the source electrode opening and a second opening positioned in the drain electrode opening respectively, wherein the orthographic projection area of the first opening on the substrate is smaller than that of the source electrode opening on the substrate, and the orthographic projection area of the second opening on the substrate is smaller than that of the drain electrode opening on the substrate.
8. The method of manufacturing a high electron mobility transistor of claim 7, wherein forming a gate metal on the magnetic medium layer between the source metal and the drain metal comprises:
etching the passivation layer and ending at the magnetic medium layer to form a gate groove on the passivation layer;
and evaporating metal on the magnetic medium layer in the grid electrode groove to form the grid electrode metal.
9. The method of manufacturing the high electron mobility transistor according to claim 6, wherein sequentially forming the drift layer and the magnetic medium layer on the substrate comprises:
depositing a drift layer on the substrate;
an active region and a passive region are defined on the drift layer through a mesa isolation process or an insulating ion implantation process;
and depositing the magnetic medium layer in the active region of the drift layer.
10. The method of claim 6, wherein the magnetic medium layer is formed by one of ALD, PECVD, LPCVD, CVD, MBE, pull-off transfer, electrochemical transfer, sol-gel process, or a combination of any two or three.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310530111.2A CN116504821A (en) | 2021-06-29 | 2021-06-29 | High electron mobility transistor and preparation method thereof |
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110729642.5A CN113451130B (en) | 2021-06-29 | 2021-06-29 | High electron mobility transistor and preparation method thereof |
| CN202310530111.2A CN116504821A (en) | 2021-06-29 | 2021-06-29 | High electron mobility transistor and preparation method thereof |
Related Parent Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202110729642.5A Division CN113451130B (en) | 2021-06-29 | 2021-06-29 | High electron mobility transistor and preparation method thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN116504821A true CN116504821A (en) | 2023-07-28 |
Family
ID=77814265
Family Applications (2)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202310530111.2A Pending CN116504821A (en) | 2021-06-29 | 2021-06-29 | High electron mobility transistor and preparation method thereof |
| CN202110729642.5A Active CN113451130B (en) | 2021-06-29 | 2021-06-29 | High electron mobility transistor and preparation method thereof |
Family Applications After (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202110729642.5A Active CN113451130B (en) | 2021-06-29 | 2021-06-29 | High electron mobility transistor and preparation method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (2) | CN116504821A (en) |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR101283934B1 (en) * | 2011-12-06 | 2013-07-16 | 한국과학기술연구원 | Complementary logic device using spin injection |
| CN104603951B (en) * | 2012-08-14 | 2017-05-24 | 国立研究开发法人科学技术振兴机构 | Spin polarization transistor element |
| CN111613535B (en) * | 2019-02-26 | 2023-10-13 | 苏州晶湛半导体有限公司 | Semiconductor structure and preparation method thereof |
| CN112071902B (en) * | 2020-08-14 | 2022-07-29 | 中国电子科技集团公司第五十五研究所 | Spin-polarized coupled GaN high-electron-mobility transistor |
-
2021
- 2021-06-29 CN CN202310530111.2A patent/CN116504821A/en active Pending
- 2021-06-29 CN CN202110729642.5A patent/CN113451130B/en active Active
Also Published As
| Publication number | Publication date |
|---|---|
| CN113451130A (en) | 2021-09-28 |
| CN113451130B (en) | 2023-07-21 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN108649071B (en) | Semiconductor devices and its manufacturing method | |
| CN108305834B (en) | Preparation method of enhanced gallium nitride field effect device | |
| CN104992974A (en) | Diamond-base double-layer insulated gate dielectric field effect transistor and a preparation method thereof | |
| CN104701359B (en) | Vertical stratification AlGaN/GaN HEMT devices and preparation method thereof | |
| CN109524460B (en) | High hole mobility transistor | |
| CN105304689A (en) | Fluorinated graphene passivated AlGaN/GaN HEMT (high electron mobility transistor) device and manufacturing method therefor | |
| CN110690284A (en) | Gallium nitride-based field effect transistor and preparation method thereof | |
| JP2019506740A (en) | Schottky barrier rectifier | |
| CN107154426A (en) | A kind of device architecture and implementation method for improving silicon substrate GaN HEMT breakdown voltages | |
| CN111384171B (en) | High-channel mobility vertical UMOSFET device and preparation method thereof | |
| CN104659082A (en) | AlGaN/GaN HEMT device with vertical structure and method for manufacturing device | |
| CN111739801B (en) | Preparation method of SOI (silicon on insulator) -based p-GaN enhanced GaN power switch device | |
| CN113451129B (en) | High electron mobility transistor and preparation method thereof | |
| CN110875372A (en) | Field effect transistor and manufacturing method | |
| CN113451130B (en) | High electron mobility transistor and preparation method thereof | |
| CN115692184A (en) | P-AlGaN gate enhancement transistor based on selective wet etching process and preparation method | |
| TW201250951A (en) | Vertical junction field effect transistors with improved thermal characteristics and methods of making | |
| CN113793806A (en) | Semiconductor device and preparation method | |
| CN108598154A (en) | A kind of enhancement type gallium nitride transistor and preparation method thereof | |
| CN111739800B (en) | Preparation method of SOI-based concave gate enhanced GaN power switch device | |
| CN115274825A (en) | Semiconductor device and preparation method thereof | |
| CN108878509A (en) | gallium nitride transistor and its manufacturing method | |
| CN113451128B (en) | High electron mobility transistor and preparation method thereof | |
| CN113659013A (en) | Schottky diode with p-type oxide dielectric composite mixed anode and manufacturing method thereof | |
| CN109860056A (en) | A kind of VDMOS device and preparation method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |