CN116504800A - Semiconductor structure preparation method and semiconductor structure - Google Patents
Semiconductor structure preparation method and semiconductor structure Download PDFInfo
- Publication number
- CN116504800A CN116504800A CN202310779496.6A CN202310779496A CN116504800A CN 116504800 A CN116504800 A CN 116504800A CN 202310779496 A CN202310779496 A CN 202310779496A CN 116504800 A CN116504800 A CN 116504800A
- Authority
- CN
- China
- Prior art keywords
- layer
- target
- semiconductor structure
- isolation
- epitaxial layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 64
- 238000002360 preparation method Methods 0.000 title abstract description 7
- 238000000034 method Methods 0.000 claims abstract description 74
- 238000002955 isolation Methods 0.000 claims abstract description 60
- 230000008569 process Effects 0.000 claims abstract description 53
- 239000000758 substrate Substances 0.000 claims abstract description 46
- 238000009792 diffusion process Methods 0.000 claims abstract description 29
- 239000007790 solid phase Substances 0.000 claims abstract description 29
- 229910052751 metal Inorganic materials 0.000 claims abstract description 28
- 239000002184 metal Substances 0.000 claims abstract description 28
- 238000000137 annealing Methods 0.000 claims abstract description 27
- 239000002131 composite material Substances 0.000 claims abstract description 22
- 239000010410 layer Substances 0.000 claims description 280
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 78
- 229910021332 silicide Inorganic materials 0.000 claims description 33
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 33
- 239000000377 silicon dioxide Substances 0.000 claims description 29
- 235000012239 silicon dioxide Nutrition 0.000 claims description 29
- 238000004519 manufacturing process Methods 0.000 claims description 24
- 239000000463 material Substances 0.000 claims description 20
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 17
- 239000002346 layers by function Substances 0.000 claims description 13
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 claims description 10
- 238000000151 deposition Methods 0.000 claims description 9
- IJGRMHOSHXDMSA-UHFFFAOYSA-N nitrogen Substances N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 8
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 7
- 229910052785 arsenic Inorganic materials 0.000 claims description 7
- 229910052757 nitrogen Inorganic materials 0.000 claims description 7
- 229910052698 phosphorus Inorganic materials 0.000 claims description 7
- 239000011574 phosphorus Substances 0.000 claims description 7
- 239000011241 protective layer Substances 0.000 claims description 7
- 229910052787 antimony Inorganic materials 0.000 claims description 6
- WATWJIUSRGPENY-UHFFFAOYSA-N antimony atom Chemical compound [Sb] WATWJIUSRGPENY-UHFFFAOYSA-N 0.000 claims description 6
- 229910052797 bismuth Inorganic materials 0.000 claims description 6
- JCXGWMGPZLAOME-UHFFFAOYSA-N bismuth atom Chemical compound [Bi] JCXGWMGPZLAOME-UHFFFAOYSA-N 0.000 claims description 6
- 238000005530 etching Methods 0.000 claims description 6
- QJGQUHMNIGDVPM-UHFFFAOYSA-N nitrogen group Chemical group [N] QJGQUHMNIGDVPM-UHFFFAOYSA-N 0.000 claims description 6
- 125000006850 spacer group Chemical group 0.000 claims description 5
- 238000011049 filling Methods 0.000 claims description 2
- 238000001914 filtration Methods 0.000 claims 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 17
- 229910052710 silicon Inorganic materials 0.000 description 14
- 239000010703 silicon Substances 0.000 description 14
- 238000002513 implantation Methods 0.000 description 8
- 229910052760 oxygen Inorganic materials 0.000 description 8
- 239000001301 oxygen Substances 0.000 description 8
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 7
- 239000013078 crystal Substances 0.000 description 6
- QVQLCTNNEUAWMS-UHFFFAOYSA-N barium oxide Chemical compound [Ba]=O QVQLCTNNEUAWMS-UHFFFAOYSA-N 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 4
- 238000001312 dry etching Methods 0.000 description 4
- 238000005468 ion implantation Methods 0.000 description 4
- MRELNEQAGSRDBK-UHFFFAOYSA-N lanthanum(3+);oxygen(2-) Chemical compound [O-2].[O-2].[O-2].[La+3].[La+3] MRELNEQAGSRDBK-UHFFFAOYSA-N 0.000 description 4
- 239000002245 particle Substances 0.000 description 4
- 238000000231 atomic layer deposition Methods 0.000 description 3
- 230000008021 deposition Effects 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 238000009616 inductively coupled plasma Methods 0.000 description 3
- 238000010884 ion-beam technique Methods 0.000 description 3
- 238000001020 plasma etching Methods 0.000 description 3
- 239000000126 substance Substances 0.000 description 3
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 230000000295 complement effect Effects 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 238000005137 deposition process Methods 0.000 description 2
- 229910000449 hafnium oxide Inorganic materials 0.000 description 2
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 description 2
- 230000031700 light absorption Effects 0.000 description 2
- CPLXHLVBOLITMK-UHFFFAOYSA-N magnesium oxide Inorganic materials [Mg]=O CPLXHLVBOLITMK-UHFFFAOYSA-N 0.000 description 2
- 239000000395 magnesium oxide Substances 0.000 description 2
- AXZKOIWUVFPNLO-UHFFFAOYSA-N magnesium;oxygen(2-) Chemical compound [O-2].[Mg+2] AXZKOIWUVFPNLO-UHFFFAOYSA-N 0.000 description 2
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 2
- SIWVEOZUMHYXCS-UHFFFAOYSA-N oxo(oxoyttriooxy)yttrium Chemical compound O=[Y]O[Y]=O SIWVEOZUMHYXCS-UHFFFAOYSA-N 0.000 description 2
- BPUBBGLMJRNUCC-UHFFFAOYSA-N oxygen(2-);tantalum(5+) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ta+5].[Ta+5] BPUBBGLMJRNUCC-UHFFFAOYSA-N 0.000 description 2
- RVTZCBVAJQQJTK-UHFFFAOYSA-N oxygen(2-);zirconium(4+) Chemical compound [O-2].[O-2].[Zr+4] RVTZCBVAJQQJTK-UHFFFAOYSA-N 0.000 description 2
- 125000004437 phosphorous atom Chemical group 0.000 description 2
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 238000000926 separation method Methods 0.000 description 2
- 239000002210 silicon-based material Substances 0.000 description 2
- 229910001936 tantalum oxide Inorganic materials 0.000 description 2
- OGIDPMRJRNCKJF-UHFFFAOYSA-N titanium oxide Inorganic materials [Ti]=O OGIDPMRJRNCKJF-UHFFFAOYSA-N 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- 229910001928 zirconium oxide Inorganic materials 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 238000007664 blowing Methods 0.000 description 1
- 238000001723 curing Methods 0.000 description 1
- 238000001035 drying Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000003628 erosive effect Effects 0.000 description 1
- 238000011010 flushing procedure Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- 238000013007 heat curing Methods 0.000 description 1
- 238000005286 illumination Methods 0.000 description 1
- 238000003384 imaging method Methods 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000001788 irregular Effects 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- -1 oxygen ion Chemical class 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
- 230000000750 progressive effect Effects 0.000 description 1
- 230000035945 sensitivity Effects 0.000 description 1
- 239000007921 spray Substances 0.000 description 1
- 238000005507 spraying Methods 0.000 description 1
- 238000003892 spreading Methods 0.000 description 1
- 230000007480 spreading Effects 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/1463—Pixel isolation structures
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
Abstract
The application relates to a semiconductor structure preparation method and a semiconductor structure, wherein the semiconductor structure preparation method comprises the following steps: providing a target substrate; forming first groove structures which are arranged at intervals along a first direction in the epitaxial layer, wherein part of isolation layers are exposed out of the first groove structures; performing at least one solid phase diffusion post-annealing push-well process in the epitaxial layer between the first trench structures adjacent along the first direction to form a target doped region in the epitaxial layer; forming a composite metal grid column positioned right above the first groove structure, wherein the composite metal grid column comprises a dielectric layer at least filled with the first groove structure; and forming a filter layer between the adjacent composite metal grid upright posts. The preparation method adopts at least one solid phase diffusion post-annealing push-well process to form the target doped region, reduces the damage to the target substrate, avoids the pixel crosstalk problem of the semiconductor device under the condition of not influencing the front-end process, and improves the product yield.
Description
Technical Field
The present disclosure relates to semiconductor manufacturing technology, and in particular, to a semiconductor structure and a method for manufacturing the same.
Background
Image sensors can be classified into charge coupled device (Charge Coupled Device, CCD) image sensors and complementary metal-oxide-semiconductor (Complementary Metal Oxide Semiconductor, CMOS) image sensors according to the difference between the photosensitive element and the photosensitive principle. Compared with a CCD image sensor, the CMOS image sensor has the advantages of low price, large bandwidth, blurring prevention, flexible access and large filling coefficient. The back-illuminated incidence (Back Side Illumination, BSI) CMOS image sensor can improve light utilization and dark-light imaging quality by changing the direction of light incidence.
The conventional technology causes damage to the sensor due to plasma implantation during the manufacturing process of the BSI CMOS image sensor, resulting in a pixel crosstalk problem.
Disclosure of Invention
In view of the foregoing, it is desirable to provide a semiconductor structure manufacturing method and a semiconductor structure capable of solving the pixel crosstalk problem.
To achieve the above and other objects, according to various embodiments of the present application, an aspect of the present application provides a semiconductor structure manufacturing method, including: providing a target substrate, wherein the target substrate is provided with a first surface and a second surface which are opposite in the thickness direction, the target substrate is provided with a base and an epitaxial layer which are laminated in the thickness direction, and first isolation structures which are arranged at intervals in the first direction are formed in the epitaxial layer; the first isolation structure extends towards the top surface of the epitaxial layer through the bottom surface of the epitaxial layer; the first direction is perpendicular to the thickness direction; forming an isolation layer extending along a first direction, wherein the isolation layer covers a first surface of the first isolation layer, and the first surface of the first isolation structure is close to a second surface of the target substrate; forming first groove structures which are arranged at intervals along a first direction in the epitaxial layer, wherein part of isolation layers are exposed out of the first groove structures; performing at least one solid phase diffusion post-annealing push-well process in the epitaxial layer between the first trench structures adjacent along the first direction to form a target doped region in the epitaxial layer; forming a composite metal grid column positioned right above the first groove structure, wherein the composite metal grid column comprises a dielectric layer at least filled with the first groove structure; and forming a filter layer between the adjacent composite metal grid upright posts.
In the method for manufacturing a semiconductor structure in the above embodiment, the target doped region is formed in the epitaxial layer by performing at least one post-solid-phase diffusion annealing push-well process on the epitaxial layer between the first trench structures adjacent along the first direction, so as to reduce damage to the target substrate in the process of forming the doped region, the doped region is formed by using a high-energy particle implantation method in the conventional method for manufacturing a semiconductor structure, the damage to the substrate is large, the problem of pixel crosstalk can be caused in the semiconductor device, the target doped region is formed by using the post-solid-phase diffusion annealing push-well process at least once, the damage to the target substrate is reduced, the problem of pixel crosstalk in the semiconductor device is avoided under the condition that the front-end process is not influenced, and the product yield is improved.
In some embodiments, performing at least one post-solid-phase diffusion anneal push-well process includes: depositing a first silicide layer by adopting a solid-phase diffusion process, wherein the first silicide layer covers the exposed top surface of the epitaxial layer, the bottom surface and the side wall of the first groove structure, and the first silicide layer contains a first target element; and annealing the first silicide layer to diffuse the first target element in the first silicide layer into the epitaxial layer and form a first silicon oxide layer, wherein the first silicon oxide layer covers the exposed top surface of the epitaxial layer, and the bottom surface and the side wall of the first groove structure.
In some embodiments, performing at least one post-solid-phase diffusion anneal push-well process includes: removing the first silicon oxide layer; depositing a second silicide layer by adopting a solid-phase diffusion process, wherein the second silicide layer covers the exposed top surface of the epitaxial layer, the bottom surface and the side wall of the first groove structure, and the second silicide layer contains a second target element; annealing the second silicide layer to diffuse the second target element into the epitaxial layer and form a second silicon dioxide layer, wherein the doped region in the epitaxial layer forms a target doped region; the second silicon dioxide layer covers the exposed top surface of the epitaxial layer, and the bottom surface and the side wall of the first trench structure.
In some embodiments, the target doped region includes a first target element doped pillar and a second target element doped layer, the first target element doped pillar being located between adjacent first trench structures for forming a Photodiode (PD); the second target element doped layer covers the outer surface of the first target element doped column, and the first target element column and the second target element doped layer formed by adopting a solid-phase diffusion post-annealing push-well process jointly form the photodiode, so that high-energy ion implantation is not needed, and the damage to a target substrate is reduced.
In some embodiments, the first target element is selected from nitrogen, phosphorus, arsenic, antimony, bismuth, or a combination thereof; the second target element is selected from nitrogen, phosphorus, arsenic, antimony, bismuth, or a combination thereof.
In some embodiments, forming the isolation layer extending along the first direction includes: forming an isolation material layer extending along a first direction, wherein the isolation material layer covers a first surface of the first isolation structure; and annealing the isolation material layer to form an isolation layer.
In some embodiments, after forming the target doped region and the second silicon dioxide layer, further comprising: forming an insulating layer on the first surface of the second silicon dioxide layer far away from the base, wherein the first surface of the base is far away from the first surface of the target substrate, the insulating layer and the second silicon dioxide layer are filled with the first groove structure together, and the top surface of the insulating layer is flush and higher than the top surface of the second silicon dioxide layer; forming a functional layer on the top surface of the insulating layer; and etching back the functional layer to obtain a composite metal grid (Composite Metal Grid, CMG) upright post, and forming a dielectric layer by the residual second silicon dioxide layer and the residual insulating layer.
In some embodiments, the functional layer includes a target dielectric constant layer, a metal layer, and a protective layer stacked in a thickness direction; the target dielectric constant layer is adjacent to the insulating layer, each composite metal grid stand column comprises the target dielectric constant layer and the protective layer, and the composite metal grid stand column with the multilayer structure can reduce the generation of dark current and improve the product yield.
In some embodiments, the filter layer includes a red filter layer, a green filter layer, and a blue filter layer, which can split red, green, and blue components of the reflected light and form a bayer array filter through the photosensitive element to convert a black and white sensor image into color.
In another aspect, the present application provides a semiconductor structure prepared by the above preparation method.
In the semiconductor structure in the above embodiment, the target doped region is formed in the epitaxial layer by performing at least one solid phase diffusion post-annealing push-well process on the epitaxial layer between the first trench structures adjacent along the first direction, so as to reduce the damage to the target substrate in the formation process of the doped region, the doped region is formed in a high-energy particle implantation mode in the conventional semiconductor structure, the damage to the substrate is large, the pixel crosstalk problem can be caused to the semiconductor device, the target doped region is formed in the semiconductor structure in the embodiment by using at least one solid phase diffusion post-annealing push-well process, the damage to the target substrate is reduced, the pixel crosstalk problem of the semiconductor device is avoided under the condition that the front-end process is not influenced, and the product yield is improved.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the description of the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic flow chart of a method for fabricating a semiconductor structure according to an embodiment of the present application;
fig. 2 is a schematic cross-sectional view of a method for fabricating a semiconductor structure according to a first embodiment of the present application;
FIG. 3 is a schematic cross-sectional view of a method for fabricating a semiconductor structure according to a second embodiment of the present application;
FIG. 4 is a schematic cross-sectional view of a method for fabricating a semiconductor structure according to a third embodiment of the present application;
fig. 5 is a schematic cross-sectional view of a method for fabricating a semiconductor structure according to a fourth embodiment of the present application;
fig. 6 is a schematic cross-sectional view of a method for fabricating a semiconductor structure according to a fifth embodiment of the present application;
fig. 7 is a schematic cross-sectional view of a method for fabricating a semiconductor structure according to a sixth embodiment of the present application;
fig. 8 is a schematic cross-sectional view of a method for fabricating a semiconductor structure according to a seventh embodiment of the present application;
fig. 9 is a schematic cross-sectional view of a semiconductor structure manufacturing method according to an eighth embodiment of the present application;
fig. 10 is a schematic cross-sectional view of a method for fabricating a semiconductor structure according to a ninth embodiment of the present application;
fig. 11 is a schematic cross-sectional view of a semiconductor structure manufacturing method according to a tenth embodiment of the present application;
fig. 12 is a schematic cross-sectional view of a semiconductor structure manufacturing method according to an eleventh embodiment of the present application;
fig. 13 is a schematic cross-sectional view of a method for fabricating a semiconductor structure according to a twelfth embodiment of the present application.
Reference numerals illustrate:
10. a target substrate; 11. a substrate; 12. an epitaxial layer; 13. a first isolation structure; 10a, a first surface of a target substrate; 10b, a second surface of the target substrate; 11a, a first surface of the substrate; 13a, a first surface of a first isolation structure; 21. a layer of isolation material; 20. an isolation layer; 30. a first trench structure; 40. a first silicide layer; 41. a first silicon oxide layer; 50. a second silicide layer; 51. a second silicon dioxide layer; 60. a target doped region; 61. doping the upright post with a first target element; 62. a second target element doped layer; 71. an insulating layer; 70. a dielectric layer; 80. a functional layer; 81. a target dielectric constant layer; 811. a first target dielectric constant layer; 812. a second target dielectric constant layer; 82. a metal layer; 83. a protective layer; 90. composite metal grid upright posts; 100. a filter layer; 101. a red filter layer; 102. a green filter layer; 103. a blue filter layer.
Detailed Description
In order to facilitate an understanding of the present application, a more complete description of the present application will now be provided with reference to the associated drawings. Preferred embodiments of the present application are shown in the drawings. This application may, however, be embodied in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the description of the application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.
It will be understood that when an element or layer is referred to as being "on," "adjacent," "connected to," or "coupled to" another element or layer, it can be directly on, adjacent, connected, or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types and/or sections, these elements, components, regions, layers, doping types and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type or section from another element, component, region, layer, doping type or section. Thus, a first element, component, region, layer, doping type or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present application; for example, the first doping type may be made the second doping type, and similarly, the second doping type may be made the first doping type; the first doping type and the second doping type are different doping types, for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.
Spatially relative terms, such as "under", "below", "beneath", "under", "above", "over" and the like, may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements or features described as "under" or "beneath" other elements would then be oriented "on" the other elements or features. Thus, the exemplary terms "below" and "under" may include both an upper and a lower orientation. Furthermore, the device may also include an additional orientation (e.g., rotated 90 degrees or other orientations) and the spatial descriptors used herein interpreted accordingly.
As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. Also, as used herein, the term "and/or" includes any and all combinations of the associated listed items.
It should be noted that, the illustrations provided in the present embodiment merely illustrate the basic concepts of the application by way of illustration, and only the components related to the application are shown in the illustration, rather than being drawn according to the number, shape and size of the components in actual implementation, and the form, number and proportion of each component in actual implementation may be arbitrarily changed, and the layout of the components may be more complex.
The BSI technology is to arrange lenses on a silicon substrate at the rear of the sensor instead of the front, so that the problem that the front wiring can limit light absorption is solved, compared with a front-illuminated CMOS image sensor, the sensitivity and light absorption capacity in the positioning mode are greatly improved, smaller-sized pixels and higher resolution can be formed, but in the process of the traditional BSI CMOS image sensor, the problems of damage to devices, pixel crosstalk and the like are caused because the photodiode needs high-energy ion implantation.
Based on this, please refer to fig. 1, the present application provides a semiconductor structure manufacturing method, which includes:
step S102: providing a target substrate, wherein the target substrate is provided with a first surface and a second surface which are opposite in the thickness direction, the target substrate is provided with a base and an epitaxial layer which are laminated in the thickness direction, and first isolation structures which are arranged at intervals in the first direction are formed in the epitaxial layer; the first isolation structure extends towards the top surface of the epitaxial layer through the bottom surface of the epitaxial layer; the first direction is perpendicular to the thickness direction;
step S104: forming an isolation layer extending along a first direction, wherein the isolation layer covers a first surface of a first isolation structure, and the first surface of the first isolation structure is close to a second surface of a target substrate;
step S106: forming first groove structures which are arranged at intervals along a first direction in the epitaxial layer, wherein part of isolation layers are exposed out of the first groove structures;
step S108: performing at least one solid phase diffusion post-annealing push-well process in the epitaxial layer between the first trench structures adjacent along the first direction to form a target doped region in the epitaxial layer;
step S110: forming a composite metal grid column positioned right above the first groove structure, wherein the composite metal grid column comprises a dielectric layer at least filled with the first groove structure;
step S112: and forming a filter layer between the adjacent composite metal grid upright posts.
As an example, please continue to refer to fig. 1, in the method for manufacturing a semiconductor structure of the present application, by performing at least one post-solid-phase diffusion annealing push-well process on the epitaxial layer between the first trench structures adjacent along the first direction, so as to form a target doped region in the epitaxial layer, reduce the damage to the target substrate in the process of forming the doped region, the conventional method for manufacturing a semiconductor structure may form the doped region by using a high-energy particle implantation method, have a large damage to the substrate and may cause the pixel crosstalk problem of the semiconductor device, and the method for manufacturing the semiconductor structure of the present application adopts at least one post-solid-phase diffusion annealing push-well process to form the target doped region, reduce the damage to the target substrate, avoid the pixel crosstalk problem of the semiconductor device and improve the product yield under the condition of not affecting the front-end process.
As an example, referring to fig. 2, the target substrate 10 in step S102 has a first surface 10a and a second surface 10b opposite to each other in the thickness direction thereof, and the target substrate 10 has a base 11 and an epitaxial layer 12 stacked in the thickness direction thereof, which may be the OY direction.
As an example, referring to fig. 2, first isolation structures 13 are formed in the epitaxial layer 12 in step S102, the first isolation structures 13 are arranged at intervals along a first direction, the first isolation structures 13 have a first surface 13a, the first surface 13a of the first isolation structures 13 is close to the second surface 10b of the target substrate 10, the first direction may be OX direction, the first isolation structures 13 may be shallow trench isolation structures (Shallow Trench Isolation, STI), the first isolation structures 13 may isolate two adjacent devices, failure caused by current flowing between the adjacent devices is prevented, and the shallow trench isolation structures may reduce the area occupied by the wafer surface, increase the integration level of the devices, maintain the flatness of the wafer surface, and reduce the risk of channel width erosion.
In some embodiments, referring to fig. 3-4, forming the isolation layer 20 extending along the first direction in step S104 includes:
step S1041: forming an isolation material layer 21 extending in the first direction, the isolation material layer 21 covering the first surface 13a of the first isolation structure 13;
step S1042: the spacer material layer 21 is annealed to form the spacer layer 20.
As an example, referring to fig. 3-4, in step S1041, the isolation material layer 21 extending along the first direction may be formed by an ion implantation process, for example, an oxygen ion beam may be selectively directed to the epitaxial layer 12, and a portion of silicon atoms in the epitaxial layer 12 may be ejected from the surface of the epitaxial layer 12 by the oxygen ion beam, and after the oxygen ion beam is directed to the interior of the epitaxial layer 12, the speed may be gradually reduced due to the resistance of the epitaxial layer 12, and finally stay in the epitaxial layer 12 to form the isolation material layer 21.
As an example, referring to fig. 3-4, step 1042 forms isolation layer 20 by an oxygen implanted isolation (separation by implantation of oxygen, separation with implanted oxygen, SIMOX) technique using an annealing process to isolate material layer 21. Under high temperature condition, step 1041 implants high dose oxygen ion into monocrystalline silicon to form isolation material layer 21, step 1042 forms isolation layer 20 of three layers of top silicon, silicon dioxide buried layer and bulk silicon under ultra-high temperature annealing condition. The use of the oxygen implantation isolation technique enables the formation of a uniform isolation layer 20 and the thickness of silicon on the isolation layer 20 can be controlled by controlling the implantation energy. As an example, referring to fig. 5, in step S106, first trench structures 30 arranged at intervals along the first direction may be formed in the epitaxial layer 12 by using an etching process, and the first trench structures 30 may be deep trench isolation structures (Deep Trench Isolation, DTI). The etching process may include, but is not limited to, a dry etching process and/or a wet etching process. The dry etching process may include, but is not limited to, one or more of Reactive Ion Etching (RIE), inductively coupled plasma etching (ICP), and the like.
In some embodiments, referring to fig. 6-7, at least one post-solid-phase diffusion annealing push-well process is performed in step S108, including:
step S1081: depositing a first silicide layer 40 by a solid phase diffusion process, wherein the first silicide layer 40 covers the exposed top surface of the epitaxial layer 12, the bottom surface and the side wall of the first trench structure 30, and the first silicide layer 40 contains a first target element;
step S1082: the first silicide layer 40 is annealed such that the first target element in the first silicide layer 40 diffuses into the epitaxial layer 12 and forms a first silicon oxide layer 41, the first silicon oxide layer 41 covering the exposed top surface of the epitaxial layer 12 and the bottom and sidewalls of the first trench structure 30.
As an example, referring to fig. 6-7, in step S1081, the first silicide layer 40 may be silicon phosphide, the solid-phase diffusion process is used to deposit the silicon phosphide, the size of the phosphorus atoms is not greatly different from that of the silicon atoms, the phosphorus atoms are diffused along the jump of crystal lattice vacancies in the silicon crystal and occupy the normal positions of the lattice sites when diffusing, the crystal structure of the original silicon material is not changed, and the silicon phosphide is annealed, so that the phosphorus element in the silicon phosphide diffuses into the epitaxial layer 12 and forms the first silicon oxide layer 41, the first silicon oxide layer 41 covers the exposed top surface of the epitaxial layer 12, and the bottom surface and the side wall of the first trench structure 30. The first silicon oxide layer 41 may be a silicon dioxide layer.
In some embodiments, referring to fig. 8-10, at least one post-solid-phase diffusion annealing push-well process is performed in step S108, including:
step S1083: removing the first silicon oxide layer 41;
step S1084: depositing a second silicide layer 50 by a solid phase diffusion process, wherein the second silicide layer 50 covers the exposed top surface of the epitaxial layer 12, the bottom surface and the side walls of the first trench structure 30, and the second silicide layer 50 contains a second target element;
step S1085: annealing the second silicide layer 50 such that a second target element in the second silicide layer 50 diffuses into the epitaxial layer 12 and forms a second silicon dioxide layer 51, the doped region in the epitaxial layer 12 constituting a target doped region 60; the second silicon dioxide layer 51 covers the exposed top surface of the epitaxial layer 12, as well as the bottom and sidewalls of the first trench structure 30.
As an example, referring to fig. 8-10, in step S1083, first silicon oxide layer 41 may be removed using an etching process, which may include, but is not limited to, a dry etching process and/or a wet etching process. The dry etching process may include, but is not limited to, one or more of RIE, ICP, and the like.
As an example, referring to fig. 8-10, in step S1084, the second silicide layer 50 may be silicon arsenide, the solid phase diffusion process is used to deposit silicon arsenide, the size of arsenic atoms is not greatly different from that of silicon atoms, the arsenic atoms jump and spread along the crystal lattice vacancies in the silicon crystal on the exposed top surface of the epitaxial layer 12 and the bottom surface and the side wall of the first trench structure 30, the arsenic atoms occupy the normal positions of the lattice sites when spreading, the crystal structure of the original silicon material is not changed, and the annealing treatment is performed on the silicon arsenide, so that the arsenic element in the silicon arsenide is diffused into the epitaxial layer 12 and forms the second silicon dioxide layer 51, and the doped region in the epitaxial layer 12 forms the target doped region 60; the second silicon dioxide layer 51 covers the exposed top surface of the epitaxial layer 12, as well as the bottom and sidewalls of the first trench structure 30. The second silicon dioxide layer 51 may be a silicon dioxide layer.
In some embodiments, referring to fig. 10, the target doped region 60 includes a first target element doped pillar 61 and a second target element doped layer 62, the first target element doped pillar 61 is located between adjacent first trench structures 30 for forming a photodiode; the second target element doped layer 62 covers the outer surface of the first target element doped stud 61.
As an example, please continue to refer to fig. 10, the first target element pillar and the second element doped layer formed by the post-solid-phase diffusion annealing and push-well process together form a photodiode, so that the formation of a doped region of the photodiode by high-energy ion implantation is avoided, and the damage to the target substrate 10 is reduced.
In some embodiments, with continued reference to fig. 10, the first target element is selected from nitrogen, phosphorus, arsenic, antimony, bismuth, or a combination thereof; the second target element is selected from nitrogen, phosphorus, arsenic, antimony, bismuth, or a combination thereof.
In some embodiments, referring to fig. 11-12, after forming the target doped region 60 and the second silicon dioxide layer 51 in step S1085, the method further includes:
step S1091: forming an insulating layer 71 on the first surface 11a of the second silicon oxide layer 51 far from the substrate 11, wherein the first surface 11a of the substrate 11 is far from the first surface 10a of the target substrate 10, the insulating layer 71 and the second silicon oxide layer 51 together fill the first trench structure 30, and the top surface of the insulating layer 71 is level and higher than the top surface of the second silicon oxide layer 51;
step S1092: forming a functional layer 80 on the top surface of the insulating layer 71;
step S1093: the functional layer 80 is etched back to obtain a composite metal grid stud 90, and the remaining second silicon dioxide layer 51 and the remaining insulating layer 71 form the dielectric layer 70.
As an example, referring to fig. 11-12, in step S1091, an insulating layer 71 may be formed on the first surface 11a of the second silicon dioxide layer 51 away from the substrate 11 by a deposition process, the insulating layer 71 and the second silicon dioxide layer 51 together fill the first trench structure 30, the top surface of the insulating layer 71 is level and higher than the top surface of the second silicon dioxide layer 51, so as to improve the isolation effect of the first trench structure 30, and the deposition process may include, but is not limited to, one or more of a chemical vapor deposition process (Chemical Vapor Deposition, CVD), an atomic layer deposition process (Atomic Layer Deposition, ALD), a high density plasma deposition (High Density Plasma, HDP) process, a plasma enhanced deposition (Plasma Enhanced Chemical Vapor Deposition, PECVD) process, and a Spin-on Dielectric (SOD) process.
In some embodiments, please continue with fig. 11-12, the functional layer 80 in step S1092 includes a target dielectric constant layer 81, a metal layer 82, and a protective layer 83 stacked in the thickness direction; the target dielectric constant layer 81 is adjacent to the insulating layer 71. The target dielectric constant layer 81 includes a first target dielectric constant layer 811 and a second target dielectric constant layer 812 stacked in a thickness direction, the target dielectric constant layer 81 may be a high-k dielectric constant layer, a material of the first target dielectric constant layer 811 is selected from hafnium oxide, aluminum oxide, zirconium oxide, magnesium oxide, yttrium oxide, tantalum oxide, titanium oxide, lanthanum oxide, and/or barium oxide, a material of the second target dielectric constant layer 812 is selected from hafnium oxide, aluminum oxide, zirconium oxide, magnesium oxide, yttrium oxide, tantalum oxide, titanium oxide, lanthanum oxide, and/or barium oxide, a material of the metal layer 82 is selected from aluminum, and a material of the protective layer 83 is selected from silicon dioxide. After each deposition of one of the functional layers 80, the layer may be planarized by a planarization process, so that the arrangement between the layers of the functional layer 80 is tighter, and the generation of dark current is reduced. The planarization process includes chemical mechanical planarization, which may grind or planarize a layer or surface of deposited or plated material; the surface of the semiconductor device can be polished or planarized by combining chemical and mechanical planarization; the polishing pad and the retaining ring are combined by using an abrasive and a corrosive chemical polishing liquid, so that materials can be removed, irregular surface morphology of the semiconductor device can be equalized, and the semiconductor device can be flattened or planarized.
As an example, please continue to refer to fig. 11-12, in step S1093, the functional layer 80 is etched back to obtain the composite metal grid columns 90 distributed at intervals along the first direction, each composite metal grid column 90 includes the target dielectric constant layer 81, the metal layer 82 and the protective layer 83, and the composite metal grid column 90 with the multilayer structure can reduce the generation of dark current and increase the product yield.
In some embodiments, referring to fig. 13, the filter layer 100 formed in step S112 includes a red filter layer 101, a green filter layer 102 and a blue filter layer 103. The red filter layer 101 corresponding to the pixels is formed by coating a layer of red photoresist, exposing, developing and baking, wherein the baking process comprises pre-baking after coating and post-baking after developing, and the baking process can enable the organic film on the substrate to be firmer and baking can be carried out by adopting an oven; the developing process can adopt a developing machine to spray and develop the substrate, and after developing, pure water is used for spraying and flushing, and nitrogen is used for blowing and drying; repeating the above process to manufacture the green and blue filter layers 103; and then, sticking the glass sheet with standard size on the prepared substrate by using glue, and performing ultraviolet curing or heat curing after sticking, so as to form the filter layer 100. The filter layer 100 may split red, green, and blue components of the reflected light and form a bayer array filter through the photosensitive element to convert a black and white sensor image into color.
It should be understood that, although the steps in the flowchart of fig. 1 are shown in sequence as indicated by the arrows, the steps are not necessarily performed in sequence as indicated by the arrows. The steps are not strictly limited to the order of execution unless explicitly recited herein, and the steps may be executed in other orders. Moreover, although at least a portion of the steps in FIG. 1 may include multiple steps or stages that are not necessarily performed at the same time, but may be performed at different times, the order in which the steps or stages are performed is not necessarily sequential, and may be performed in rotation or alternatively with at least a portion of the steps or stages in other steps or steps.
In some embodiments, another aspect of the present application provides a semiconductor structure prepared using the above-described preparation method.
By way of example, in the semiconductor structure of the present application, the target doped region is formed in the epitaxial layer by performing at least one solid phase diffusion post-annealing push-well process on the epitaxial layer between the first trench structures adjacent along the first direction, so as to reduce the damage to the target substrate in the formation process of the doped region, the doped region is formed in a high-energy particle implantation mode in the conventional semiconductor structure, the damage to the substrate is large, the pixel crosstalk problem can be caused to the semiconductor device, the target doped region is formed in the semiconductor structure of the present embodiment by using at least one solid phase diffusion post-annealing push-well process, the damage to the target substrate is reduced, the pixel crosstalk problem can be avoided to the semiconductor device under the condition that the front-end process is not affected, and the product yield is improved.
In some embodiments, a further aspect of the present application provides a backside illuminated image sensor comprising the above-described semiconductor structure.
In this specification, each embodiment is described in a progressive manner, and each embodiment is mainly described by differences from other embodiments, and identical and similar parts between the embodiments are all enough to be referred to each other.
The technical features of the above embodiments may be arbitrarily combined, and all possible combinations of the technical features in the above embodiments are not described for brevity of description, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.
The foregoing examples represent only a few embodiments of the present application, which are described in more detail and are not thereby to be construed as limiting the scope of the disclosure. It should be noted that it would be apparent to those skilled in the art that various modifications and improvements could be made without departing from the spirit of the present application, which would be within the scope of the present application.
Claims (10)
1. A method of fabricating a semiconductor structure, comprising:
providing a target substrate, wherein the target substrate is provided with a first surface and a second surface which are opposite in the thickness direction, the target substrate is provided with a base and an epitaxial layer which are laminated in the thickness direction, and first isolation structures which are arranged at intervals in the first direction are formed in the epitaxial layer; the first isolation structure extends towards the top surface of the epitaxial layer through the bottom surface of the epitaxial layer; the first direction is perpendicular to the thickness direction;
forming an isolation layer extending along the first direction, wherein the isolation layer covers a first surface of the first isolation structure, and the first surface of the first isolation structure is close to a second surface of the target substrate;
forming first groove structures which are arranged at intervals along the first direction in the epitaxial layer, wherein part of the isolation layer is exposed out of the first groove structures;
performing at least one solid-phase diffusion post-annealing push-well process in the epitaxial layer between the first trench structures adjacent along the first direction to form a target doped region in the epitaxial layer;
forming a composite metal grid column positioned right above the first groove structure, wherein the composite metal grid column comprises a dielectric layer at least filling the first groove structure;
and forming a light filtering layer between the adjacent composite metal grid upright posts.
2. The method of manufacturing a semiconductor structure according to claim 1, wherein performing at least one post-solid-phase diffusion anneal push-well process comprises:
depositing a first silicide layer by adopting a solid-phase diffusion process, wherein the first silicide layer covers the exposed top surface of the epitaxial layer, the bottom surface and the side wall of the first groove structure, and the first silicide layer contains a first target element;
and annealing the first silicide layer to enable a first target element in the first silicide layer to diffuse into the epitaxial layer and form a first silicon oxide layer, wherein the first silicon oxide layer covers the exposed top surface of the epitaxial layer, and the bottom surface and the side wall of the first groove structure.
3. The method of manufacturing a semiconductor structure according to claim 2, wherein performing at least one post-solid-phase diffusion anneal push-well process comprises:
removing the first silicon oxide layer;
depositing a second silicide layer by adopting a solid-phase diffusion process, wherein the second silicide layer covers the exposed top surface of the epitaxial layer, the bottom surface and the side wall of the first groove structure, and the second silicide layer contains a second target element;
annealing the second silicide layer to enable a second target element in the second silicide layer to diffuse into the epitaxial layer and form a second silicon dioxide layer, wherein a doped region in the epitaxial layer forms the target doped region; the second silicon dioxide layer covers the exposed top surface of the epitaxial layer, and the bottom surface and the side wall of the first groove structure.
4. The method of manufacturing a semiconductor structure of claim 3, wherein the target doped region comprises:
a first target element doped column positioned between adjacent first trench structures for forming a photodiode; and
and the second target element doped layer covers the outer surface of the first target element doped upright post.
5. The method of manufacturing a semiconductor structure of claim 4, wherein the first target element is selected from nitrogen, phosphorus, arsenic, antimony, bismuth, or a combination thereof;
the second target element is selected from nitrogen, phosphorus, arsenic, antimony, bismuth, or a combination thereof.
6. The method of fabricating a semiconductor structure of claim 5, wherein forming an isolation layer extending along the first direction comprises:
forming a spacer material layer extending along a first direction, the spacer material layer covering a first surface of the first spacer structure;
and annealing the isolation material layer to form an isolation layer.
7. The method of manufacturing a semiconductor structure according to any one of claims 3 to 5, further comprising, after forming the target doped region and the second silicon dioxide layer:
forming an insulating layer on a first surface of the second silicon dioxide layer, which is far away from the base, wherein the first surface of the base is far away from the first surface of the target substrate, the insulating layer and the second silicon dioxide layer together fill the first groove structure, and the top surface of the insulating layer is flush and higher than the top surface of the second silicon dioxide layer;
forming a functional layer on the top surface of the insulating layer;
and etching the functional layer back to obtain the composite metal grid stand column, wherein the rest second silicon dioxide layer and the rest insulating layer form the dielectric layer.
8. The method for manufacturing a semiconductor structure according to claim 7, wherein the functional layer includes a target dielectric constant layer, a metal layer, and a protective layer stacked in the thickness direction;
the target dielectric constant layer is adjacent to the insulating layer.
9. The method of manufacturing a semiconductor structure according to any one of claims 1 to 5, wherein the filter layer includes a red filter layer, a green filter layer, and a blue filter layer.
10. A semiconductor structure prepared by the method of any one of claims 1-9.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310779496.6A CN116504800B (en) | 2023-06-29 | 2023-06-29 | Semiconductor structure preparation method and semiconductor structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310779496.6A CN116504800B (en) | 2023-06-29 | 2023-06-29 | Semiconductor structure preparation method and semiconductor structure |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN116504800A true CN116504800A (en) | 2023-07-28 |
| CN116504800B CN116504800B (en) | 2023-09-12 |
Family
ID=87325356
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202310779496.6A Active CN116504800B (en) | 2023-06-29 | 2023-06-29 | Semiconductor structure preparation method and semiconductor structure |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN116504800B (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116884837A (en) * | 2023-09-06 | 2023-10-13 | 合肥晶合集成电路股份有限公司 | Semiconductor device and method for manufacturing the same |
| CN117219649A (en) * | 2023-11-09 | 2023-12-12 | 合肥晶合集成电路股份有限公司 | Semiconductor structure and preparation method thereof |
| CN117293155A (en) * | 2023-11-22 | 2023-12-26 | 合肥晶合集成电路股份有限公司 | Semiconductor structure, preparation method thereof and back-illuminated image sensor |
| CN117393574A (en) * | 2023-12-13 | 2024-01-12 | 合肥晶合集成电路股份有限公司 | Semiconductor structure and manufacturing method thereof |
Citations (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20120077301A1 (en) * | 2010-09-29 | 2012-03-29 | Samsung Electronics Co., Ltd. | Image sensor and method of fabricating the same |
| US20130149822A1 (en) * | 2011-12-08 | 2013-06-13 | Tsung-Hsiung LEE | Method for fabricating semiconductor device |
| CN106206629A (en) * | 2015-05-28 | 2016-12-07 | 台湾积体电路制造股份有限公司 | Imageing sensor and method thereof without implant damage |
| CN107799543A (en) * | 2017-11-03 | 2018-03-13 | 德淮半导体有限公司 | The manufacture method of contact-type image sensor |
| US20200066768A1 (en) * | 2018-08-27 | 2020-02-27 | Taiwan Semiconductor Manufacturing Co., Ltd. | Image sensor having improved full well capacity and related method of formation |
| CN113097238A (en) * | 2019-12-23 | 2021-07-09 | 豪威科技股份有限公司 | Method for passivating full-front-side deep trench isolation structures |
| US20220102397A1 (en) * | 2020-09-29 | 2022-03-31 | Taiwan Semiconductor Manufacturing Co., Ltd. | Back-side deep trench isolation structure for image sensor |
| CN114664870A (en) * | 2021-03-05 | 2022-06-24 | 台湾积体电路制造股份有限公司 | Image sensor and method of forming semiconductor device |
| CN115939159A (en) * | 2023-02-02 | 2023-04-07 | 合肥晶合集成电路股份有限公司 | Image sensor and manufacturing method thereof |
| CN116093144A (en) * | 2023-01-17 | 2023-05-09 | 飞锃半导体（上海）有限公司 | Semiconductor structure and forming method |
| CN116110923A (en) * | 2023-03-31 | 2023-05-12 | 合肥新晶集成电路有限公司 | Method for preparing semiconductor structure and semiconductor structure |
| CN116314229A (en) * | 2023-03-31 | 2023-06-23 | 合肥晶合集成电路股份有限公司 | Image sensor and manufacturing method thereof |
| CN116314018A (en) * | 2023-05-23 | 2023-06-23 | 合肥晶合集成电路股份有限公司 | Semiconductor integrated device and manufacturing method thereof |
-
2023
- 2023-06-29 CN CN202310779496.6A patent/CN116504800B/en active Active
Patent Citations (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20120077301A1 (en) * | 2010-09-29 | 2012-03-29 | Samsung Electronics Co., Ltd. | Image sensor and method of fabricating the same |
| US20130149822A1 (en) * | 2011-12-08 | 2013-06-13 | Tsung-Hsiung LEE | Method for fabricating semiconductor device |
| CN106206629A (en) * | 2015-05-28 | 2016-12-07 | 台湾积体电路制造股份有限公司 | Imageing sensor and method thereof without implant damage |
| CN107799543A (en) * | 2017-11-03 | 2018-03-13 | 德淮半导体有限公司 | The manufacture method of contact-type image sensor |
| US20200066768A1 (en) * | 2018-08-27 | 2020-02-27 | Taiwan Semiconductor Manufacturing Co., Ltd. | Image sensor having improved full well capacity and related method of formation |
| CN113097238A (en) * | 2019-12-23 | 2021-07-09 | 豪威科技股份有限公司 | Method for passivating full-front-side deep trench isolation structures |
| US20220102397A1 (en) * | 2020-09-29 | 2022-03-31 | Taiwan Semiconductor Manufacturing Co., Ltd. | Back-side deep trench isolation structure for image sensor |
| CN114664870A (en) * | 2021-03-05 | 2022-06-24 | 台湾积体电路制造股份有限公司 | Image sensor and method of forming semiconductor device |
| CN116093144A (en) * | 2023-01-17 | 2023-05-09 | 飞锃半导体（上海）有限公司 | Semiconductor structure and forming method |
| CN115939159A (en) * | 2023-02-02 | 2023-04-07 | 合肥晶合集成电路股份有限公司 | Image sensor and manufacturing method thereof |
| CN116110923A (en) * | 2023-03-31 | 2023-05-12 | 合肥新晶集成电路有限公司 | Method for preparing semiconductor structure and semiconductor structure |
| CN116314229A (en) * | 2023-03-31 | 2023-06-23 | 合肥晶合集成电路股份有限公司 | Image sensor and manufacturing method thereof |
| CN116314018A (en) * | 2023-05-23 | 2023-06-23 | 合肥晶合集成电路股份有限公司 | Semiconductor integrated device and manufacturing method thereof |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116884837A (en) * | 2023-09-06 | 2023-10-13 | 合肥晶合集成电路股份有限公司 | Semiconductor device and method for manufacturing the same |
| CN116884837B (en) * | 2023-09-06 | 2023-11-17 | 合肥晶合集成电路股份有限公司 | Semiconductor device and method for manufacturing the same |
| CN117219649A (en) * | 2023-11-09 | 2023-12-12 | 合肥晶合集成电路股份有限公司 | Semiconductor structure and preparation method thereof |
| CN117219649B (en) * | 2023-11-09 | 2024-02-20 | 合肥晶合集成电路股份有限公司 | Semiconductor structure and preparation method thereof |
| CN117293155A (en) * | 2023-11-22 | 2023-12-26 | 合肥晶合集成电路股份有限公司 | Semiconductor structure, preparation method thereof and back-illuminated image sensor |
| CN117293155B (en) * | 2023-11-22 | 2024-02-20 | 合肥晶合集成电路股份有限公司 | Semiconductor structure, preparation method thereof and back-illuminated image sensor |
| CN117393574A (en) * | 2023-12-13 | 2024-01-12 | 合肥晶合集成电路股份有限公司 | Semiconductor structure and manufacturing method thereof |
| CN117393574B (en) * | 2023-12-13 | 2024-03-01 | 合肥晶合集成电路股份有限公司 | Semiconductor structure and manufacturing method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| CN116504800B (en) | 2023-09-12 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN116504800B (en) | Semiconductor structure preparation method and semiconductor structure | |
| KR101650246B1 (en) | Image sensor comprising reflective guide layer and method of forming the same | |
| US20210375962A1 (en) | Image sensor device and method of fabricating the same | |
| US8378440B2 (en) | Back-lit image sensor and method of manufacture | |
| TWI407553B (en) | Backside illuminated image sensor having deep light reflective trenches | |
| KR101489038B1 (en) | Methods and apparatus for an improved reflectivity optical grid for image sensors | |
| CN106972036A (en) | Integrated circuit and forming method thereof | |
| JP6076299B2 (en) | Back injection sensor co-injection system | |
| TW201349468A (en) | Semiconductor device and method for manufacturing the same | |
| US20130234202A1 (en) | Image Sensor Isolation Region and Method of Forming the Same | |
| WO2009146253A1 (en) | Image sensor with focusing interconnections | |
| JP2008546176A (en) | Color pixel with anti-blooming isolation and formation method | |
| TWI541989B (en) | Image sensor and fabrications thereof | |
| US20110169991A1 (en) | Image sensor with epitaxially self-aligned photo sensors | |
| CN117219649B (en) | Semiconductor structure and preparation method thereof | |
| TWI540688B (en) | Semiconductor device, backside illuminated image sensor device and method for forming the same | |
| KR20220043809A (en) | Back-side deep trench isolation structure for image sensor | |
| KR20190006764A (en) | Backside illuminated image sensor and method of manufacturing the same | |
| CN109585481B (en) | Image sensor structure and preparation method thereof | |
| US11538839B2 (en) | Solid-state image sensor including patterned structure for decreasing petal flares | |
| KR102580342B1 (en) | Backside illuminated image sensor and the method of manufacturing the same | |
| CN112714953A (en) | Solid-state image pickup device and electronic apparatus | |
| CN117293155B (en) | Semiconductor structure, preparation method thereof and back-illuminated image sensor | |
| TWI815124B (en) | Image sensor and method of forming the same | |
| TW202306135A (en) | Solid-state image sensor |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |