CN116093144A - Semiconductor structure and forming method - Google Patents

Semiconductor structure and forming method Download PDF

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Publication number
CN116093144A
CN116093144A CN202310081862.0A CN202310081862A CN116093144A CN 116093144 A CN116093144 A CN 116093144A CN 202310081862 A CN202310081862 A CN 202310081862A CN 116093144 A CN116093144 A CN 116093144A
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gate
region
grid
dielectric layer
forming
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张永杰
李浩南
彭定康
周永昌
三重野文健
黄晓辉
董琪琪
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Feicheng Semiconductor Shanghai Co ltd
Alpha Power Solutions Ltd
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Feicheng Semiconductor Shanghai Co ltd
Alpha Power Solutions Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0638—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for preventing surface leakage due to surface inversion layer, e.g. with channel stopper
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/402—Field plates
    • H01L29/407—Recessed field plates, e.g. trench field plates, buried field plates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate

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Abstract

The technical scheme provides a semiconductor structure and a forming method thereof, wherein the semiconductor structure comprises: a substrate comprising an epitaxial layer thereon; the first doped region is positioned in the epitaxial layer and is distributed in a staggered manner; a well region extending from a surface of the epitaxial layer into the epitaxial layer; a source region discrete extending from a surface of the well region into the well region; the second doped region is positioned between adjacent source regions and extends from the surface of the well region into the well region or extends out of the well region; the first grid structure and the second grid structure are alternately distributed in the source electrode, the well region and the epitaxial layer, and both the first grid structure and the second grid structure comprise grids, wherein the first grid structure further comprises a pseudo grid positioned below the grids. The semiconductor structure and the forming method thereof can reduce the electric field at the bottom of the grid structure and reduce grid leakage charges.

Description

Semiconductor structure and forming method
Technical Field
The present disclosure relates to semiconductor manufacturing, and more particularly, to a semiconductor structure and a method of forming the same.
Background
With the continued development of power MOSFET technology, trench type MOSFET (Trench MOSFET) has emerged. The biggest advantage of trench MOSFETs is that they can increase the channel density of planar devices to increase the current handling capability of the devices. However, the bottom of the gate structure of the current trench MOSFET is subjected to a higher electric field, and the gate-drain charge (Qgd) is larger.
Disclosure of Invention
The technical problem to be solved by the application is how to reduce the electric field at the bottom of the gate structure and reduce the gate leakage charge.
To solve the above technical problem, the present application provides a semiconductor structure, including: a substrate comprising an epitaxial layer thereon; the first doped region is positioned in the epitaxial layer and is distributed in a staggered manner; a well region extending from a surface of the epitaxial layer into the epitaxial layer; a source region discrete extending from a surface of the well region into the well region; the second doped region is positioned between adjacent source regions and extends from the surface of the well region into the well region or extends out of the well region; the first grid structure and the second grid structure are alternately distributed in the source electrode, the well region and the epitaxial layer, wherein the first grid structure is positioned on the surface of the first doped region at a lower position, the second grid structure is positioned on the surface of the first doped region at a higher position, the first grid structure and the second grid structure both comprise grids, the first grid structure also comprises a dummy grid positioned below the grid, and the side walls and the bottoms of the grid and the dummy grid are covered with a grid dielectric layer.
In some embodiments of the present application, the first gate structure has a width of 0.6 μm to 3.0 μm and a depth of 1.5 μm to 3.0 μm, and in the first gate structure, the gate dielectric layer of the dummy gate sidewall has a thickness of 50nm to 300nm, the gate dielectric layer between the dummy gate and the gate has a thickness of 50nm to 300nm, the gate dielectric layer of the dummy gate bottom has a thickness of 100nm to 500nm, the gate dielectric layer of the gate sidewall has a thickness of 15nm to 150nm, the dummy gate has a height of 0.5 μm to 1.0 μm, and the gate has a height of 0.6 μm to 1.8 μm.
In some embodiments of the present application, the second gate structure has a width of 0.6 μm to 3.0 μm and a depth of 1.0 μm to 2.0 μm, and in the second gate structure, the gate has a height of 0.6 μm to 1.8 μm, the gate dielectric layer of the gate sidewall has a thickness of 15nm to 150nm, and the gate dielectric layer of the gate bottom has a thickness of 100nm to 500nm.
In some embodiments of the present application, a spacing between adjacent first gate structures and second gate structures is 0.6 μm to 3.0 μm.
In some embodiments of the present application, the gate and dummy gate materials include polysilicon, and the gate dielectric layer materials include high-K material and/or silicon dioxide.
In some embodiments of the present application, the first doped region has a height of 0.2 μm to 1.5 μm.
In some embodiments of the present application, the depth of the source region is 0.2 μm to 0.8 μm, the depth of the second doped region is 0.3 μm to 1.8 μm, the width of the second doped region is 0.2 μm to 1.5 μm, and the depth of the well region is 0.5 μm to 1.5 μm.
In some embodiments of the present application, the epitaxial layer and the source region have a first doping type, the first doping region, the well region, the second doping region have a second doping type, and the first doping type and the second doping type are opposite.
In some embodiments of the present application, the surfaces of the first gate structure and the second gate structure and a portion of the source region further include an insulating layer, and a thickness of the insulating layer is 100nm to 500nm.
In some embodiments of the present application, the semiconductor structure further includes a source metal, and the source metal is located on surfaces of the remaining source region, the second doped region, and the insulating layer.
The application also provides a method for forming the semiconductor structure, which comprises the following steps: providing a substrate, wherein the substrate comprises an epitaxial layer; forming a first doped region in the epitaxial layer, wherein the first doped region is distributed in a staggered manner; forming a well region extending from a surface of the epitaxial layer into the epitaxial layer; forming discrete source regions extending from a surface of the well region into the well region; forming a second doped region between adjacent source regions, wherein the second doped region extends from the surface of the well region into the well region or extends out of the well region; and forming first grid structures and second grid structures which are alternately distributed in the source electrode, the well region and the epitaxial layer, wherein the first grid structures are positioned on the surface of the first doped region at a lower position, the second grid structures are positioned on the surface of the first doped region at a higher position, the first grid structures and the second grid structures comprise grids, the first grid structures also comprise dummy grids positioned below the grids, and the side walls and the bottoms of the grids and the dummy grids are covered with grid dielectric layers.
In some embodiments of the present application, a method of forming the first gate structure includes: forming deep trenches in the source electrode, the well region and the epitaxial layer on the surface of the first doped region at the lower position; forming a first gate dielectric layer on the side wall and the bottom of the deep trench; forming a dummy gate in a part of the deep trench; forming a second gate dielectric layer on the surface of the dummy gate and the surface of the first gate dielectric layer higher than the dummy gate; and forming a grid electrode on the surface of the second grid dielectric layer, wherein the grid electrode fills the deep groove.
In some embodiments of the present application, the deep trench has a width of 0.6 μm to 3.0 μm and a depth of 1.5 μm to 3.0 μm, the dummy gate has a height of 0.5 μm to 1.0 μm, the first gate dielectric layer of the dummy gate sidewall has a thickness of 50nm to 300nm, the second gate dielectric layer between the dummy gate and the gate has a thickness of 50nm to 300nm, the first gate dielectric layer of the bottom of the dummy gate has a thickness of 100nm to 500nm, the total thickness of the first gate dielectric layer and the second gate dielectric layer of the gate sidewall has a thickness of 15nm to 150nm, and the gate has a height of 0.6 μm to 1.8 μm.
In some embodiments of the present application, a method of forming the second gate structure includes: forming grooves in the source electrode, the well region and the epitaxial layer on the surface of the first doped region at the higher position; forming a second gate dielectric layer on the side wall and the bottom of the groove; and forming the grid electrode which fills up the groove on the surface of the second grid dielectric layer.
In some embodiments of the present application, the width of the trench is 0.6 μm to 3.0 μm, the depth is 1.0 μm to 2.0 μm, the thickness of the second gate dielectric layer on the sidewall of the trench is 15nm to 150nm, the thickness of the second gate dielectric layer on the bottom of the trench is 100nm to 500nm, and the height of the gate is 0.6 μm to 1.8 μm.
In some embodiments of the present application, the doping concentration of the epitaxial layer is 1×10 14 /cm 3 ～1×10 16 /cm 3 The doping concentration of the well region is 5×10 16 /cm 3 ～5×10 20 /cm 3 The doping concentration of the first doped region is 5×10 16 /cm 3 ～1×10 21 /cm 3 The doping concentration of the second doped region is 3×10 17 /cm 3 ～1×10 21 /cm 3 The doping concentration of the source region is 1×10 18 /cm 3 ～1×10 21 /cm 3 。
In some embodiments of the present application, the method for forming a semiconductor structure further includes: forming an insulating layer on the surfaces of the first gate structure, the second gate structure and part of the source region; and forming source metal on the surfaces of the rest of the source region, the second doped region and the insulating layer.
Compared with the prior art, the semiconductor structure and the forming method of the technical scheme have the following beneficial effects:
the semiconductor structure and the forming method thereof are characterized in that a first grid structure and a second grid structure are arranged in a source electrode, a well region and an epitaxial layer, the first grid structure and the second grid structure comprise grids which are used as grid parts of MOS tubes, the first grid structure further comprises a dummy grid which is positioned below the grid of the first grid structure and can be used as a field plate to provide an electric field clamping effect. Meanwhile, the first grid structures and the second grid structures are alternately distributed, so that the density of the MOS tube can be relatively increased.
And a first doping region is arranged below the first grid electrode structure and the second grid electrode structure, and the first doping region can reduce the electric field of the grid dielectric layer, so that the reliability of the grid dielectric layer is improved, and the grid leakage charge is reduced. Meanwhile, the first doped region can also prevent the diffusion of the dislocation defects of the basal plane and improve the conductivity.
Drawings
The following figures describe in detail exemplary embodiments disclosed in the present application. Wherein like reference numerals refer to like structure throughout the several views of the drawings. Those of ordinary skill in the art will understand that these embodiments are non-limiting, exemplary embodiments, and that the drawings are for illustration and description purposes only and are not intended to limit the scope of the present application, other embodiments may equally well accomplish the intent of the invention in this application. It should be understood that the drawings are not to scale. Wherein:
fig. 1 is a schematic structure diagram of a trench MOSFET;
fig. 2 to 14 are schematic structural diagrams illustrating steps in a method for forming a semiconductor structure according to an embodiment of the present application.
Detailed Description
The following description provides specific applications and requirements to enable any person skilled in the art to make and use the teachings of the present application. Various modifications to the disclosed embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments and applications without departing from the spirit and scope of the application. Thus, the present application is not limited to the embodiments shown, but is to be accorded the widest scope consistent with the claims.
Referring to fig. 1, a trench MOSFET includes an epitaxial layer 10, a gate structure 20 is formed in the epitaxial layer 10, a well region 30 is formed between adjacent gate structures 20, an active region 40 is formed in the well region 30, the active region 40 abuts against a sidewall of the gate structure 20, a doped region 50 is also formed in the source region 40 and the well region 30, and the source region 40 and the doped region 50 extend from a surface of the well region 30 into the well region 30. Such trench MOSFETs, while capable of improving the current handling capability of the device, have a higher electric field at the bottom of the gate structure 20 and a larger gate drain charge Qgd.
Based on the above, the semiconductor structure and the forming method of the technical scheme of the application form the first grid structure and the second grid structure which are alternately distributed in the source region, the well region and the epitaxial layer, wherein the first grid structure and the second grid structure both comprise grids which can be used for MOS tubes, meanwhile, the first grid structure also comprises dummy grids, the dummy grids are positioned below the corresponding grids and can be used as field plates to provide an electric field clamping effect. In addition, a first doping region is formed below the first gate structure and the second gate structure, so that the electric field of the gate dielectric layer can be reduced, the reliability of the gate dielectric layer is improved, gate leakage charges are reduced, diffusion of defects of base surface dislocation (BPD, basal Plane Dislocation) can be prevented, and conductivity is improved.
The following describes the semiconductor structure of the technical scheme of the present application in detail with reference to the accompanying drawings and specific embodiments.
Referring to fig. 13, an embodiment of the present application provides a semiconductor structure, including: the substrate 100 may be, for example, a SiC substrate, the substrate 100 includes an epitaxial layer 110 thereon, and the material of the epitaxial layer 110 may be the same as that of the substrate 100. The epitaxial layer 110 may be doped with impurity ions of a first doping type, which may be, for example, nitrogen, arsenic, antimony, phosphorus, or the like. The doping concentration of the epitaxial layer 110 may be 10 14 /cm 3 ～10 16 /cm 3 。
The first doped regions 200 are located in the epitaxial layer 110, and the first doped regions 200 are distributed in a staggered manner, that is, a part of the first doped regions 200 are located at a lower position, a part of the first doped regions 200 are located at an upper position, and the first doped regions 200 at a lower position and the first doped regions 200 at an upper position are alternately distributed. The depth of the first doped region 200 is dependent on the depth of the corresponding gate structure above. The first doped region 200 has a height of 0.2 μm to 1.5 μm. The first doped region 200 has a second doping type that is opposite to the first doping type. In some embodiments, the epitaxial layer 110 is doped N-type and the first doped region 200 is doped P-type. The doping concentration of the first doped region 200 may be 5×10 16 /cm 3 ～1×10 21 /cm 3 . The first doped region 200 may prevent the expansion of BPD defects, thereby improving the conductivity of the device.
The well region 300 extends from the surface of the epitaxial layer 110 into the epitaxial layer 110, and the depth of the well region 300 may be 0.5 μm to 1.5 μm. The well region 300 has a second doping type, for example, the well region 300 is lightly doped P-type. For example, aluminum can be usedThe well region 300 is doped with ions so that the doping concentration of the well region 300 is 5×10 16 /cm 3 ～5×10 20 /cm 3 。
Source regions 400 are discrete extending from the surface of the well region 300 into the well region 300, and the source regions 400 have a first doping type. As an example, the source region 400 is doped N-type and has a doping concentration of 1×10 18 /cm 3 ～1×10 21 /cm 3 . In some embodiments, the source region 400 has a depth of 0.2 μm to 0.8 μm.
The second doped region 500 is located between adjacent source regions 400 and extends from the surface of the well region 300 into the well region 300. In some embodiments, the second doped region 500 may further extend out of the well region 300, thereby reducing the forward turn-on voltage of the PN junction. The second doped region 500 has a second doping type, such as P-type doping. In some embodiments, the second doped region 500 has a doping concentration of 3×10 17 /cm 3 ～1×10 21 /cm 3 . The depth of the second doped region 500 may be 0.3 μm to 1.8 μm, and the width of the second doped region 500 may be 0.2 μm to 1.5 μm.
The semiconductor structure further includes a first gate structure and a second gate structure alternately distributed in the source 400, the well 300, and the epitaxial layer 110. The spacing between adjacent first and second gate structures may be 0.6 μm to 3.0 μm. Wherein the first gate structure is located at a lower position on the surface of the first doped region 200, and the first gate structure has a width of 0.6 μm to 3.0 μm and a depth of 1.5 μm to 3.0 μm. The first gate structure comprises a gate 820 and a dummy gate 810 positioned below the gate 820, and the sidewalls and bottom of the gate 820 and the dummy gate 810 are covered with a gate dielectric layer. In the first gate structure, the thickness of the gate dielectric layer (i.e., the subsequent first gate dielectric layer 711) on the sidewall of the dummy gate 810 is 50nm to 300nm, the thickness of the gate dielectric layer (i.e., the subsequent first gate dielectric layer 711) on the bottom of the dummy gate 810 is 100nm to 500nm, and the height of the dummy gate 810 is 0.5 μm to 1.0 μm. The height of the gate electrode 820 above the dummy gate 810 is 0.6 μm to 1.8 μm, and the thickness of the gate dielectric layer (i.e., the subsequent second gate dielectric layer 712) between the dummy gate 810 and the gate electrode 820 is 50nm to 300nm. The thickness of the gate dielectric layer (i.e., the first gate dielectric layer 711 and the second gate dielectric layer 712) on the sidewall of the gate 820 is 15nm to 150nm. The gate 820 and dummy gate 810 may comprise polysilicon, and the gate dielectric layer may comprise a high-K material (i.e., a material having a dielectric constant greater than that of silicon dioxide) and/or silicon dioxide.
The gate 820 of the first gate structure is used as a gate of the MOS transistor, and the dummy gate 810 under the gate 820 may serve as a field plate to provide an electric field clamping effect. The first doped region 200 under the dummy gate 810 not only can reduce the electric field of the gate dielectric layer of the first gate structure, improve the reliability of the gate dielectric layer, reduce the gate leakage charge, but also can prevent the diffusion of BPD defects and improve the conductivity of the device.
The second gate structure is located on the surface of the first doped region 200 at a higher position, and has a width of 0.6 μm to 3.0 μm and a depth of 1.0 μm to 2.0 μm. The second gate structure includes a gate 820, and the sidewalls and bottom of the gate 820 are also covered with a gate dielectric layer. In the second gate structure, the height of the gate 820 is 0.6 μm to 1.8 μm, the thickness of the gate dielectric layer (i.e., the subsequent second gate dielectric layer 712) on the sidewall of the gate 820 is 15nm to 150nm, and the thickness of the gate dielectric layer (i.e., the subsequent second gate dielectric layer 712) on the bottom of the gate 820 is 100nm to 500nm. The gate 820 material may include polysilicon and the gate dielectric layer material may include high-K material and/or silicon dioxide. The widths of the first gate structure and the second gate structure may be the same or different.
The second gate structure may be used for a gate structure of a MOS transistor. The first doped region 200 below the second gate structure can reduce the electric field of the gate dielectric layer of the second gate structure, improve the reliability of the gate dielectric layer, reduce the gate leakage charge, prevent the diffusion of BPD defects, and improve the conductivity of the device.
If all the second gate structures are replaced by the first gate structures, that is, all the second gate structures are designed as the first gate structures, the density of the MOS transistor cannot be increased when the density of the MOS transistor is increased to a certain extent due to the limitation of the deep trench process. However, when the second gate structures are inserted between the first gate structures, that is, the first gate structures and the second gate structures are alternately distributed, the density of the MOS transistor can be further increased.
Referring to fig. 14, the semiconductor structure may further include an insulating layer 713, the insulating layer 713 may be located on the surfaces of the first and second gate structures and a portion of the source region 400, and the insulating layer 713 may have a thickness of 100nm to 500nm. The material of the insulating layer 713 may include a high-K material and/or silicon dioxide. The semiconductor structure may further include a source metal 900, and the source metal 900 is located on the surfaces of the remaining source region 400, the second doped region 500, and the insulating layer 713. The material of the source metal 900 may include aluminum.
The method for forming the semiconductor structure according to the embodiments of the present application will be described in detail below with reference to the accompanying drawings and specific embodiments.
The method for forming the semiconductor structure comprises the following steps:
s1: providing a substrate, wherein the substrate comprises an epitaxial layer;
s2: forming a first doped region in the epitaxial layer, wherein the first doped region is distributed in a staggered manner;
s3: forming a well region extending from a surface of the epitaxial layer into the epitaxial layer;
s4: forming discrete source regions extending from a surface of the well region into the well region;
s5: forming a second doped region between adjacent source regions, wherein the second doped region extends from the surface of the well region into the well region or extends out of the well region;
s6: and forming first grid structures and second grid structures which are alternately distributed in the source electrode, the well region and the epitaxial layer, wherein the first grid structures are positioned on the surface of the first doped region at a lower position, the second grid structures are positioned on the surface of the first doped region at a higher position, the first grid structures and the second grid structures comprise grids, the first grid structures also comprise dummy grids positioned below the grids, and the side walls and the bottoms of the grids and the dummy grids are covered with grid dielectric layers.
Referring to fig. 2, in step S1, an epitaxial layer 110 is formed on the substrate 100 provided. The material of the substrate 100 and the epitaxial layer 110 may include silicon carbide, and the epitaxial layer 110 may be formed by an epitaxial growth process. The epitaxial layer 110 may be doped with N-type impurity ions such as nitrogen, arsenic, antimony or phosphorus by ion implantation, and the doping concentration of the N-type impurity ions may be 10 14 /cm 3 ～10 16 /cm 3 。
Referring to fig. 3, a first doped region 200 is formed in the epitaxial layer 110, and the first doped region 200 is distributed in a staggered manner, wherein the first doped region 200 at a lower position is located under a subsequently formed first gate structure, and the first doped region 200 at a higher position is located under a subsequently formed second gate structure, so as to reduce an electric field of gate dielectric layers in the first gate structure and the second gate structure, improve reliability of the gate dielectric layer, and reduce gate leakage charges. Meanwhile, the first doped region 200 can prevent the diffusion of the dislocation defect of the basal plane and improve the conductivity. The first doped region 200 has a doping concentration of 5×10 16 /cm 3 ～1×10 21 /cm 3 . When forming the first doped region 200, the first doped region 200 at the lower position may be formed by an ion implantation process, and then the first doped region 200 at the upper position may be formed by an ion implantation process.
Referring to fig. 4, a well region 300 is formed in the epitaxial layer 110, and the well region 300 extends from the surface of the epitaxial layer 110 into the epitaxial layer 110. The well region 300 may be formed by an ion implantation process, and the implanted ions are of a type opposite to the doped ions of the epitaxial layer 110, e.gThe ion type of implantation is P type, the doping ion is aluminum ion, the doping concentration can be 5×10 16 /cm 3 ～5×10 20 /cm 3 。
Referring to fig. 5, a source region 400 extending from a surface of the well region 300 into the well region 300 is formed, and the source region 400 is separately located in the well region 300. The method of forming the source region 400 may include: forming a patterned oxide layer on the surface of the well region 300, exposing the ion-implanted region of the patterned oxide layer, forming the source region 400 by ion implantation process, wherein the implantation ion type is the same as the doping ion type of the epitaxial layer 110, and the ion implantation concentration is 1×10 18 /cm 3 ～1×10 21 /cm 3 And finally, removing the patterned oxide layer.
Referring to fig. 6, a second doped region 500 is formed between adjacent source regions 400, and the second doped region 500 extends from the surface of the well region 300 into the well region 300. The forming process of the second doped region 500 may include: forming an oxide layer on the surface of the source region 250, wherein the oxide layer covers the source region 400 and leaks out of the second doped region 500, and performing ion implantation with the oxide layer as a mask, wherein the type of ion implantation is the same as the doping type of the first doped region 200 and the well region 300, the doping ions may be, for example, aluminum ions, and the doping concentration may be 3×10 17 /cm 3 ～1×10 21 /cm 3 And finally removing the oxide layer. In an embodiment of the present application, the depth of the second doped region 500 may be less than or equal to the depth of the well region 300. In other embodiments, the second doped region 500 may also extend beyond the well region 300, as shown with reference to fig. 7.
Referring to fig. 8, a method of forming the first gate structure may include: deep trenches 610 in the source 400, the well 300 and the epitaxial layer 110 are formed on the surface of the first doped region 200 at a lower position, and the source 400, the well 300 and the epitaxial layer 110 above the first doped region 200 at a lower position may be sequentially etched by an etching process, and stopped on the surface of the first doped region 200, thereby forming the deep trenches 610. Then, a first gate dielectric layer 711 is formed on the sidewall and the bottom of the deep trench 610, and the forming process of the first gate dielectric layer 711 may be a deposition process such as chemical vapor deposition, physical vapor deposition, atomic layer deposition, etc. The deep trench 610 has a width of 0.6 μm to 3.O μm and a depth of 1.5 μm to 3.O μm. Because the depth of the deep trench 610 is greater, when the first gate dielectric layer 711 is formed by a deposition process, the thickness of the first gate dielectric layer 711 formed on the upper sidewall of the deep trench 610 is thinner, and the thickness of the first gate dielectric layer 711 formed on the lower sidewall and bottom of the deep trench 610 is relatively thicker. In some embodiments, the thickness of the first gate dielectric layer 711 located on the sidewall of the lower portion of the deep trench 610 is 50nm to 300nm, and the first gate dielectric layer 711 located on the portion of the first gate dielectric layer 711, that is, the first gate dielectric layer 711 located on the sidewall of the dummy gate. The thickness of the first gate dielectric layer 711 at the bottom of the deep trench 610, that is, the first gate dielectric layer 711 at the bottom of the dummy gate, is 100 nm-500 nm. The material of the first gate oxide layer 711 may include a high-K material and/or silicon dioxide.
Referring to fig. 9, dummy gates 810 are formed in portions of the deep trenches 610. The process of forming the dummy gate 810 may include: depositing a dummy gate material in the deep trench 610 and on the surfaces of the source region 400 and the second doped region 500 by a deposition process; an etching process is used to remove the dummy gate material on the surfaces of the source region 400 and the second doped region 500 and in part of the deep trench 610, thereby forming a dummy gate 810. The dummy gate 810 may have a height of 0.5 μm to 1.0 μm. The material of the dummy gate 810 may include polysilicon.
Referring to fig. 10, a second gate dielectric layer 712 is formed on the surface of the dummy gate 810 and the surface of the first gate dielectric layer 711 higher than the dummy gate 810. The second gate dielectric layer 712 may be formed by chemical vapor deposition, physical vapor deposition, atomic layer deposition, or the like. The thickness of the second gate dielectric layer 712 located on the surface of the dummy gate 810 is 50 nm-300 nm, which is the second gate dielectric layer 712 located between the dummy gate 810 and the gate formed subsequently. The total thickness of the first gate dielectric layer 711 and the second gate dielectric layer 712 located on the gate sidewall formed later is 15nm to 150nm. The material of the second gate dielectric layer 712 may include a high-K material (having a dielectric constant greater than that of silicon dioxide) and/or silicon dioxide.
Referring to fig. 11, a gate 820 is formed on the surface of the second gate dielectric layer 712, and the gate 820 fills the deep trench 610. The process of forming the gate 820 may include: depositing gate materials in the deep trench 610 and on the surfaces of the source region 400 and the second doped region 500 by a deposition process; and removing gate materials on the surfaces of the source region 400 and the second doped region 500 by adopting a grinding process, so that the surfaces of the gate materials are flush with the top surfaces of the source region 400 and the second doped region 500, and forming a gate 820. The height of the gate 820 may be 0.6 μm to 1.8 μm. The material of the gate 820 may include polysilicon.
Referring to fig. 12, the method of forming the second gate structure includes: a trench 620 is formed in the source 400, the well 300 and the epitaxial layer 110 at the surface of the first doped region 200 at the upper position. The trench 620 may be formed by etching the source region 400, the well region 300, and the epitaxial layer 110 over the first doped region 200 at the higher position. The width of the groove 620 is 0.6 μm to 3.0 μm and the depth is 1.0 μm to 2.0 μm. Then, a second gate dielectric layer 712 is formed on the sidewall and the bottom of the trench 620, where the forming process of the second gate dielectric layer 712 may be a deposition process such as chemical vapor deposition, physical vapor deposition, atomic layer deposition, etc. The thickness of the second gate dielectric layer 712 on the sidewall of the trench 620 is 15nm to 150nm, and the thickness of the second gate dielectric layer 712 on the bottom of the trench 620 is 100nm to 500nm. The material of the second gate dielectric layer 712 may include a high-K material (having a dielectric constant greater than that of silicon dioxide) and/or silicon dioxide.
Referring to fig. 13, a gate 820 is formed on the surface of the second gate dielectric layer 712 of the second gate structure, and the gate 820 fills the trench 620. The process of forming the gate 820 may include: depositing gate material in the trenches 620 and on the surfaces of the source region 400 and the second doped region 500 by a deposition process; and removing gate materials on the surfaces of the source region 400 and the second doped region 500 by adopting a grinding process, so that the surfaces of the gate materials are flush with the top surfaces of the source region 400 and the second doped region 500, and forming a gate 820. The height of the gate 820 may be 0.6 μm to 1.8 μm. The material of the gate 820 may include polysilicon.
Referring to fig. 14, the method for forming a semiconductor structure may further include: an insulating layer 713 is formed on the surfaces of the first and second gate structures and a portion of the source region 400. The forming method of the insulating layer 713 may include: depositing insulating materials on the surfaces of the first gate structure and the second gate structure, the source region 400 and the second doped region 500 by adopting deposition processes such as chemical vapor deposition, physical vapor deposition or atomic layer deposition; the insulating material is then etched to expose the second doped region 500 and portions of the surface of the source region 400 on both sides of the second doped region 500, forming the insulating layer 713. The material of the insulating layer 713 may include a high-K material and/or silicon dioxide.
The method for forming the semiconductor structure can further comprise the following steps: source metal 900 is formed on the surfaces of the remaining source region 400, the second doped region 500, and the insulating layer 713. The source metal 900 material includes, for example, aluminum.
In view of the foregoing, it will be evident to those skilled in the art after reading this application that the foregoing application may be presented by way of example only and may not be limiting. Although not explicitly described herein, those skilled in the art will appreciate that the present application is intended to embrace a variety of reasonable alterations, improvements and modifications to the embodiments. Such alterations, improvements, and modifications are intended to be within the spirit and scope of the exemplary embodiments of the present application.
It should be understood that the term "and/or" as used in this embodiment includes any or all combinations of one or more of the associated listed items. It will be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements may also be present.
Similarly, it will be understood that when an element such as a layer, region or substrate is referred to as being "on" another element, it can be directly on the other element or intervening elements may also be present. In contrast, the term "directly" means without intermediate elements. It will be further understood that the terms "comprises," "comprising," "includes" or "including," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
It will be further understood that, although the terms first, second, third, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. Thus, a first element in some embodiments could be termed a second element in other embodiments without departing from the teachings of the present application. Like reference numerals or like reference numerals designate like elements throughout the specification.
Furthermore, the present specification describes example embodiments by reference to idealized example cross-sectional and/or plan and/or perspective views. Thus, differences from the illustrated shapes, due to, for example, manufacturing techniques and/or tolerances, are to be expected. Thus, the exemplary embodiments should not be construed as limited to the shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an etched region shown as a rectangle will typically have rounded or curved features. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the exemplary embodiments.

Claims (17)

1. A semiconductor structure, comprising:
a substrate comprising an epitaxial layer thereon;
the first doped region is positioned in the epitaxial layer and is distributed in a staggered manner;
a well region extending from a surface of the epitaxial layer into the epitaxial layer;
a source region discrete extending from a surface of the well region into the well region;
the second doped region is positioned between adjacent source regions and extends from the surface of the well region into the well region or extends out of the well region;
the first grid structure and the second grid structure are alternately distributed in the source electrode, the well region and the epitaxial layer, wherein the first grid structure is positioned on the surface of the first doped region at a lower position, the second grid structure is positioned on the surface of the first doped region at a higher position, the first grid structure and the second grid structure both comprise grids, the first grid structure also comprises a dummy grid positioned below the grid, and the side walls and the bottoms of the grid and the dummy grid are covered with a grid dielectric layer.
2. The semiconductor structure of claim 1, wherein the first gate structure has a width of 0.6 μm to 3.0 μm and a depth of 1.5 μm to 3.0 μm, and wherein in the first gate structure, the gate dielectric layer of the dummy gate sidewall has a thickness of 50nm to 300nm, the gate dielectric layer between the dummy gate and the gate has a thickness of 50nm to 300nm, the gate dielectric layer of the dummy gate bottom has a thickness of 100nm to 500nm, the gate dielectric layer of the gate sidewall has a thickness of 15nm to 150nm, the dummy gate has a height of 0.5 μm to 1.0 μm, and the gate has a height of 0.6 μm to 1.8 μm.
3. The semiconductor structure of claim 1, wherein the second gate structure has a width of 0.6 μm to 3.0 μm and a depth of 1.0 μm to 2.0 μm, and wherein the second gate structure has a height of 0.6 μm to 1.8 μm, wherein the gate dielectric layer of the gate sidewall has a thickness of 15nm to 150nm, and wherein the gate dielectric layer of the gate bottom has a thickness of 100nm to 500nm.
4. The semiconductor structure of claim 1, wherein a spacing between adjacent first gate structures and second gate structures is 0.6 μιη to 3.0 μιη.
5. The semiconductor structure of claim 1, wherein the gate and dummy gate materials comprise polysilicon and the gate dielectric layer material comprises high-K material and/or silicon dioxide.
6. The semiconductor structure of claim 1, wherein a height of the first doped region is 0.2 μm to 1.5 μm.
7. The semiconductor structure of claim 1, wherein the source region has a depth of 0.2 μm to 0.8 μm, the second doped region has a depth of 0.3 μm to 1.8 μm, the second doped region has a width of 0.2 μm to 1.5 μm, and the well region has a depth of 0.5 μm to 1.5 μm.
8. The semiconductor structure of claim 1, wherein the epitaxial layer and the source region have a first doping type, the first doping region, the well region, the second doping region have a second doping type, and the first doping type and the second doping type are opposite.
9. The semiconductor structure of claim 1, wherein surfaces of the first and second gate structures and a portion of the source region further comprise an insulating layer, the insulating layer having a thickness of 100nm to 500nm.
10. The semiconductor structure of claim 9, further comprising a source metal, wherein the source metal is located on a surface of the remaining source region, the second doped region, and the insulating layer.
11. A method of forming a semiconductor structure, comprising:
providing a substrate, wherein the substrate comprises an epitaxial layer;
forming a first doped region in the epitaxial layer, wherein the first doped region is distributed in a staggered manner;
forming a well region extending from a surface of the epitaxial layer into the epitaxial layer;
forming discrete source regions extending from a surface of the well region into the well region;
forming a second doped region between adjacent source regions, wherein the second doped region extends from the surface of the well region into the well region or extends out of the well region;
and forming first grid structures and second grid structures which are alternately distributed in the source electrode, the well region and the epitaxial layer, wherein the first grid structures are positioned on the surface of the first doped region at a lower position, the second grid structures are positioned on the surface of the first doped region at a higher position, the first grid structures and the second grid structures comprise grids, the first grid structures also comprise dummy grids positioned below the grids, and the side walls and the bottoms of the grids and the dummy grids are covered with grid dielectric layers.
12. The method of forming a semiconductor structure of claim 11, wherein the method of forming the first gate structure comprises:
forming deep trenches in the source electrode, the well region and the epitaxial layer on the surface of the first doped region at the lower position;
forming a first gate dielectric layer on the side wall and the bottom of the deep trench;
forming a dummy gate in a part of the deep trench;
forming a second gate dielectric layer on the surface of the dummy gate and the surface of the first gate dielectric layer higher than the dummy gate;
and forming a grid electrode on the surface of the second grid dielectric layer, wherein the grid electrode fills the deep groove.
13. The method of claim 12, wherein the deep trench has a width of 0.6 μm to 3.0 μm and a depth of 1.5 μm to 3.0 μm, the dummy gate has a height of 0.5 μm to 1.0 μm, the first gate dielectric layer of the dummy gate sidewall has a thickness of 50nm to 300nm, the second gate dielectric layer between the dummy gate and the gate has a thickness of 50nm to 300nm, the first gate dielectric layer of the bottom of the dummy gate has a thickness of 100nm to 500nm, the first gate dielectric layer of the gate sidewall and the second gate dielectric layer have a total thickness of 15nm to 150nm, and the gate has a height of 0.6 μm to 1.8 μm.
14. The method of forming a semiconductor structure of claim 11, wherein the method of forming the second gate structure comprises:
forming grooves in the source electrode, the well region and the epitaxial layer on the surface of the first doped region at the higher position;
forming a second gate dielectric layer on the side wall and the bottom of the groove;
and forming the grid electrode which fills up the groove on the surface of the second grid dielectric layer.
15. The method of claim 14, wherein the trench has a width of 0.6 μm to 3.0 μm and a depth of 1.0 μm to 2.0 μm, the second gate dielectric layer on the sidewall of the trench has a thickness of 15nm to 150nm, the second gate dielectric layer on the bottom of the trench has a thickness of 100nm to 500nm, and the gate has a height of 0.6 μm to 1.8 μm.
16. The method of claim 11, wherein the epitaxial layer has a doping concentration of 1 x 10 14 /cm 3 ～1×10 16 /cm 3 Doping concentration of the well regionIs 5 multiplied by 10 16 /cm 3 ～5×10 20 /cm 3 The doping concentration of the first doped region is 5×10 16 /cm 3 ～1×10 21 /cm 3 The doping concentration of the second doped region is 3×10 17 /cm 3 ～1×10 21 /cm 3 The doping concentration of the source region is 1×10 18 /cm 3 ～1×10 21 /cm 3 。
17. The method of forming a semiconductor structure of claim 11, further comprising:
forming an insulating layer on the surfaces of the first gate structure, the second gate structure and part of the source region;
and forming source metal on the surfaces of the rest of the source region, the second doped region and the insulating layer.
CN202310081862.0A 2023-01-17 2023-01-17 Semiconductor structure and forming method Pending CN116093144A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116504800A (en) * 2023-06-29 2023-07-28 合肥晶合集成电路股份有限公司 Semiconductor structure preparation method and semiconductor structure

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116504800A (en) * 2023-06-29 2023-07-28 合肥晶合集成电路股份有限公司 Semiconductor structure preparation method and semiconductor structure
CN116504800B (en) * 2023-06-29 2023-09-12 合肥晶合集成电路股份有限公司 Semiconductor structure preparation method and semiconductor structure

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