CN116504759A

CN116504759A - Semiconductor device and preparation method thereof

Info

Publication number: CN116504759A
Application number: CN202310787400.0A
Authority: CN
Inventors: 刘杉; 韦玥; 刘庆波; 黎子兰
Original assignee: Xuzhou Zhineng Semiconductor Co ltd; Guangdong Zhineng Technology Co Ltd
Current assignee: Xuzhou Zhineng Semiconductor Co ltd; Guangdong Zhineng Technology Co Ltd
Priority date: 2023-06-30
Filing date: 2023-06-30
Publication date: 2023-07-28
Anticipated expiration: 2043-06-30
Also published as: CN116504759B

Abstract

The invention relates to a semiconductor device and a preparation method thereof, which belong to the technical field of semiconductors and are used for solving the problem of parasitic capacitance in the semiconductor device, wherein the semiconductor device comprises: the device comprises a device functional area, more than two electrode structures, more than two electrode pads and a shielding layer, wherein the more than two electrode structures are respectively formed inside the device functional area; the two or more electrode pads are respectively arranged on the surface of the device functional area, and each electrode structure is electrically connected with at least one electrode pad through an interconnection structure in the device functional area to form an electrode; the shielding layer includes one or more shielding sublayers formed between different electrodes. The semiconductor device provided by the invention can adjust the parasitic capacitance in the device, so as to achieve the purpose of matching with the parasitic capacitance of the matching circuit.

Description

Semiconductor device and preparation method thereof

Technical Field

The invention relates to the technical field of semiconductors, in particular to a semiconductor device and a preparation method thereof.

Background

Semiconductor gallium nitride (GaN) has the characteristics of large forbidden bandwidth, high critical breakdown electric field, high thermal conductivity, high electron saturation drift velocity, good chemical stability and the like, so that more and more GaN-based power devices for meeting various power requirements are generated. For example, gaN-based HEMTs (High Electron Mobility Transistors ) are becoming increasingly popular for microwave high power and high temperature applications with the advantages of faster switching speeds and lower on-resistance and switching losses. However, since GaN-based power devices are very sensitive to parasitic parameters during high-speed switching, high switching speeds are often accompanied by higher dv/di, di/dt, which can result in systems that are more susceptible to parasitic parameters, adding additional loss to the device and even damaging the device. One important class of parasitic parameters is parasitic capacitance, for example, there are three main parasitic capacitances inside GaN-based HEMTs: the gate-source capacitance Cgs, the gate-drain capacitance Cgd, and the drain-source capacitance Cds generate additional switching loss when these parasitic capacitances are not matched, so in order to solve this problem in the prior art, a method of adding a compensation capacitor is generally adopted to reduce the influence of the parasitic capacitance on the device or system performance. However, the use of additional compensation capacitance solutions increases the difficulty of the packaging process, the cost and the risk of device failure of the device.

Disclosure of Invention

Aiming at the technical problems in the prior art, the invention provides a semiconductor device and a preparation method thereof, which are used for adjusting parasitic capacitance in the device.

In order to solve the technical problem, according to one aspect of the present invention, a semiconductor device is provided, which includes a device functional region, two or more electrode structures, two or more electrode pads, and a shielding layer, wherein the one or more electrode structures are respectively formed inside the device functional region; the more than one electrode pad is respectively formed on the surface of the device functional area, and each electrode structure is electrically connected with at least one electrode pad through an interconnection structure in the device functional area to form an electrode; the shielding layer includes one or more shielding sublayers formed between different electrodes.

Optionally, the electrode pads of one electrode are located above the electrode structures of the other electrode, and at least one or more shielding sub-layers are located in the vertical overlap region between the electrode pads and the electrode structures.

Optionally, the plurality of shielding sublayers in the vertical overlapping region between the electrode pad and the electrode structure are located on the same plane or are located on different planes in an up-down staggered manner.

Optionally, the horizontal overlap region between the electrode structures of the different electrodes comprises one or more shielding sublayers; alternatively, the horizontal overlap region between the electrode pads of the different electrodes includes one or more shielding sublayers.

Optionally, the plurality of shielding sublayers in the horizontal overlapping region between different electrode structures are located on the same vertical plane or are located on different vertical planes in a left-right staggered manner.

Optionally, one or more of the plurality of shielding sublayers is electrically connected to an electrode structure and/or an electrode pad of one or more electrodes through the first interconnect metal for adjusting parasitic capacitance between different electrodes.

Optionally, the one or more shielding sublayers form one or more shielding bridges.

Optionally, the shielding bridge is in a convex shape structure or a concave shape structure.

Optionally, the shielding bridge of the convex structure comprises two first shielding sublayers horizontally spaced and a second shielding sublayer positioned above the two first shielding sublayers and covering the horizontally spaced area; or the shielding bridge with the convex-shaped structure is formed by a shielding sub-layer covered on the convex steps of the medium.

Optionally, the shielding bridge with the concave structure comprises a dielectric groove and a shielding sub-layer covering the dielectric groove; or the shielding bridge with the concave-shaped structure is a groove formed on the shielding sub-layer.

Optionally, the interconnection structure in the device functional region includes an interlayer via, wherein a dielectric region surrounding an inner surface of the interlayer via is wrapped with a shielding sub-layer.

Alternatively, the inter-layer vias of the electrode structures of the different electrodes are offset from each other.

Optionally, the interconnect structure in the device functional region includes a second interconnect metal, including one or more shielding sublayers between the second interconnect metal of one electrode and the electrode structure of the other electrode; and/or including one or more shielding sublayers between the second interconnect metal of one electrode and the electrode pad of the other electrode; and/or one or more shielding sublayers are included between the second interconnect metal of one electrode and the second interconnect metal of the other electrode.

Optionally, the device functional region is a GaN power device functional region, and the electrodes are a HEMT gate, a HEMT source and a HEMT drain.

Optionally, the device functional region is a MOS transistor functional region, and the electrode is a MOS gate, a MOS source, and a MOS drain.

Optionally, the device functional region is a diode functional region, and the electrodes are an anode and a cathode.

In order to solve the above technical problem, according to another aspect of the present invention, a method for manufacturing a semiconductor device is provided, which includes the steps of:

providing a device functional area;

providing more than two electrode structures in the device functional region;

providing more than two electrode pads on the surface of the device functional area, wherein each electrode structure is electrically connected with at least one electrode pad through an interconnection structure to form an electrode; and

one or more shielding sublayers are provided between the different electrodes.

According to the invention, the parasitic capacitance between different electrodes can be adjusted by adding the shielding layer between the different electrodes, so that the purpose of matching with the parasitic capacitance of the matched circuit is achieved, and the performance of the device or the circuit is improved.

Drawings

Preferred embodiments of the present invention will be described in further detail below with reference to the attached drawing figures, wherein:

fig. 1 is a flowchart of a method for manufacturing a semiconductor device according to a first embodiment of the present invention;

fig. 2 is a schematic longitudinal cross-sectional view of a semiconductor device structure according to a first embodiment of the present invention;

fig. 3 is a schematic diagram of parasitic capacitance between the first drain pad 131 and the first source structure 123 inside in the structure shown in fig. 2;

fig. 4 is a schematic longitudinal cross-sectional view of a semiconductor device structure according to a second embodiment of the present invention;

fig. 5 is a schematic longitudinal cross-sectional view of a semiconductor device structure according to a third embodiment of the present invention;

fig. 6 is a schematic longitudinal cross-sectional view of a semiconductor device structure according to a fourth embodiment of the present invention;

fig. 7 is a schematic longitudinal cross-sectional view of a semiconductor device structure according to a fifth embodiment of the present invention;

fig. 8 is a schematic longitudinal sectional view of a semiconductor device structure according to a sixth embodiment of the present invention;

fig. 9 is a schematic longitudinal cross-sectional view of a semiconductor device structure according to a seventh embodiment of the present invention;

fig. 10 is a schematic cross-sectional view of the first interlayer via 16 of fig. 9;

fig. 11 is a schematic longitudinal sectional view of a semiconductor device structure according to an eighth embodiment of the present invention;

fig. 12 is a schematic longitudinal sectional view of a semiconductor device structure according to a ninth embodiment of the present invention;

fig. 13 is a schematic cross-sectional view of a semiconductor device at a via between layers according to an embodiment ten of the invention;

fig. 14 is a schematic longitudinal sectional view of a semiconductor device according to an eleventh embodiment of the present invention; and

fig. 15 is a schematic longitudinal sectional view of a semiconductor device according to a twelfth embodiment of the present invention.

Detailed Description

For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are some embodiments of the present invention, but not all embodiments of the present invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.

In the following detailed description, reference is made to the accompanying drawings, which form a part hereof, and in which is shown by way of illustration specific embodiments in which the application may be practiced. In the drawings, like reference numerals describe substantially similar components throughout the different views. Various specific embodiments of the present application are described in sufficient detail below to enable those skilled in the art to practice the teachings of the present application. It is to be understood that other embodiments may be utilized or structural, logical, or electrical changes may be made to the embodiments of the present application.

The invention provides a semiconductor device which comprises a device functional region, more than one (i.e. two or more) electrode structures and shielding layers which are positioned in the device functional region, and electrode pads which are positioned on the surface of the device functional region. According to different device types, electrode structures for completing corresponding functions are formed inside the device functional area, the electrode pads are formed on the surface of the device functional area, and each electrode structure is electrically connected with one or more electrode pads through interconnection structures, such as interlayer vias and interconnection metals, so that one electrode is formed. The shielding layer includes one or more shielding sublayers formed between different electrodes.

The semiconductor device can be a heterojunction-based HEMT (high electron mobility transistor) or a GaN-based Schottky diode, or can be a PN junction-based silicon-based diode, a triode, a field effect transistor (such as MOSFET (metal oxide semiconductor field effect transistor) or CMOS (complementary metal oxide semiconductor) and the like. But also LCD, OLED, RF devices, memory, etc. The semiconductor device provided by the invention is described below by way of specific examples.

Embodiment one.

Fig. 1 is a flowchart of a method for manufacturing a semiconductor device according to a first embodiment of the present invention. Fig. 2 is a schematic longitudinal cross-sectional view of a semiconductor device structure according to a first embodiment of the present invention. In this embodiment, taking HEMT as an example, the structure of the semiconductor device is described with reference to fig. 1 and 2, and the method for manufacturing the semiconductor device in this embodiment includes the following steps:

in step S101, a first substrate 111 is provided. The material of the first substrate 111 is, for example, intrinsic GaN or a material such as silicon (Si), silicon carbide (SiC) or sapphire (the main component is Al ₂ O ₃ ) Etc. When the first substrate 111 is an extrinsic GaN substrate, a buffer layer may be further introduced to reduce the influence of lattice differences. The buffer layer may be one or more of aluminum nitride (AlN), gallium nitride (GaN), gallium aluminum nitride (AlGaN), gallium indium nitride (InGaN), indium aluminum nitride (AlInN) and indium gallium aluminum nitride (AlGaInN), so as to reduce the influence caused by the difference between the lattice constant and the thermal expansion coefficient between the first substrate 111 and the channel layer 112, and effectively avoid the situation of cracking and the like of the nitride epitaxial layer. The buffer layer is an optional structure.

In step S102, a channel layer 112, a barrier layer 113, and a gate dielectric layer 114 are epitaxially formed on a first substrate 111. The material of the channel layer 112 is GaN, the material of the barrier layer 113 is AlGaN, and the channel layer 112 and the barrier layer 113 form a heterojunction to generate a two-dimensional electron gas (2 DEG). The materials of the channel layer 112 and the barrier layer 113 constituting the heterojunction may also be other III-V semiconductor materials, such as AlN, gaN, indium nitride (InN), and compounds of these materials, such as AlGaN, inGaN, alInGaN, etc. In order to protect the barrier layer 113, a cap layer may be further added on the barrier layer 113. The material of the gate dielectric layer 114 is, for example, silicon nitride.

In step S103, the first drain structure 121, the first gate structure 122, and the first source structure 123 are sequentially provided. The first gate structure 122 forms a schottky contact, and the first drain structure 121 and the first source structure 123 are coupled to the heterojunction, respectively, to form an ohmic contact.

In step S104, a first passivation dielectric layer 115 is provided to cover and separate the three electrode structures. The first passivation dielectric layer 115 may also be CMP mechanically planarized after it is deposited.

In step S105, a first source-drain shield sub-layer 141 is provided over the first passivation dielectric layer 115. In the present embodiment, the first source pad 133 and the internal first drain structure 121 have a certain overlapping area in the vertical direction based on the structural layout, and thus parasitic capacitance may be generated therebetween, and the present embodiment provides the first source-drain shielding sub-layer 141 in the vertically overlapping area of the first source pad 133 and the internal first drain structure 121, which may have an area greater than or equal to the overlapping area. Similarly, another first source-drain shield sub-layer 141 is provided at a vertically overlapping region of the first drain pad 131 and the inner first source structure 123. Similarly, if the first gate pad (not shown in fig. 2) has an upper and lower vertical overlapping area with the internal first drain structure 121 or the first source structure 123, a gate-drain parasitic capacitance or a gate-source parasitic capacitance can be generated, and a shielding sub-layer, i.e., the first gate-drain shielding sub-layer 142 (see fig. 7), may be provided as well. The first source-drain shielding sub-layer 141 in fig. 2 is two separate shielding sub-layers for isolating the first drain pad 131 from the inner first source structure 123, the first source pad 133 and the inner first drain structure 121, respectively. Thereby providing a completed shielding layer between the individual electrodes. The shielding sub-layers may be made of conductive materials, such as various metals, such as titanium (Ti), aluminum (Al), copper (Cu), and the like, or composite metals, such as titanium nitride (TiN), titanium aluminide (TiAl), and the like. The shielding sub-layer may also be a semiconductor material such as aluminum nitride (AlN) or zinc oxide (ZnO), etc.

In step S106, a second passivation dielectric layer 116 is provided over the current structure to cover all of the shielding sub-layers. The second passivation dielectric layer 116 may also be CMP mechanically planarized.

In step S107, electrode pads (Bonding pads) are provided at predetermined positions on the second passivation dielectric layer 116 according to layout requirements. Such as a first drain pad 131, a first source pad 133, and a first gate pad not shown in the drawing.

Some conventional steps are omitted in the above-described flow. For example, the step of forming a hole in the dielectric layer and filling the hole with metal is performed, for example, before step S105, and when the first source-drain shielding sub-layer 141 is provided above the first passivation dielectric layer 115 in step S105, a layer of metal may be grown in the formed hole and on the surface of the first passivation dielectric layer 115 at the same time. For example, when the metal is grown on the surface of the first passivation dielectric layer 115, a step of growing the metal according to a preset pattern or a step of patterning the metal on which the entire layer is grown may be omitted, and thus a plurality of separate shielding sublayers may be obtained. In addition, the structure for electrically connecting the internal electrode structure and the external electrode pad may require interconnection metal in addition to interlayer vias according to layout requirements of the internal electrode structure and the external electrode pad of the functional region. In order to clearly show the relationship between the shield layer and the respective structures constituting the electrode, an interconnection structure such as an interlayer via and possibly an interconnection metal for electrically connecting the internal electrode structure and the external electrode pad is omitted in fig. 2.

Fig. 3 is a schematic diagram of parasitic capacitance between the first drain pad 131 and the first source structure 123 inside in the structure shown in fig. 2. When the first source-drain shielding sub-layer 141 is absent, a source-drain parasitic capacitance C between the first source structure 123 and the first drain pad 131 _SD Is the first capacitance C1 determined by the overlapping area and distance between the two. After the first source-drain shielding sub-layer 141 is added, a source-drain parasitic capacitance C between the first source structure 123 and the first drain pad 131 _SD And is instead constituted by a second capacitor C11 and a third capacitor C12. The overlapping area and distance between the first drain pad 131 and the first source drain shield sub-layer 141 determine the second capacitance C11, and the overlapping area and distance between the first source drain shield sub-layer 141 and the first source structure 123 determine the third capacitance C12. Thus, the source-drain parasitic capacitance C between the first source structure 123 and the first drain pad 131 can be changed by providing the overlapping area and distance of the shielding sub-layer and the electrode structure or the electrode pad _SD . Source-drain parasitic capacitance C between the first source structure 123 and the first drain pad 131 _SD I.e. parasitic capacitance or portion between source and drainParasitic capacitance is divided, and similarly, the parasitic capacitance C of the grid and the drain between the grid and the drain can be changed _GD Gate-source parasitic capacitance C between gate and source _GS 。

In this embodiment, since the electrode pad and the electrode structure below the electrode pad are components of different electrodes, a certain voltage difference may be generated between the electrode pad and the electrode structure, and for a HEMT device, the voltage difference may be up to several kv, so the first passivation dielectric layer 115 and the second passivation dielectric layer 116 need to be capable of withstanding a high voltage electric field. In one embodiment, the material of the first passivation dielectric layer 115 and the second passivation dielectric layer 116 is SiN, siO ₂ As can be seen from the foregoing steps, the structure shown in fig. 2, and the principle of adjusting parasitic capacitance shown in fig. 3, the parasitic capacitance between the electrodes can be adjusted by adding a shielding layer between the electrodes, so as to achieve the purpose of matching with the driving circuit.

When the HEMT device shown in this embodiment is a depletion GaN transistor, a Cascode device may be formed with a low-voltage enhancement MOS transistor. In order to match with the parasitic capacitance generated by the low-voltage enhancement MOS transistor, a shielding layer is added between the electrodes of the depletion type GaN transistor to adjust the parasitic capacitance of the depletion type GaN transistor, so that the parasitic capacitance value can be adjusted, the problem of matching of the parasitic capacitance in the Casode device is further solved, dependence on the compensating capacitance is reduced, and the performance of the Casode device is improved.

Embodiment two.

Fig. 4 is a schematic longitudinal cross-sectional view of a semiconductor device structure according to a second embodiment of the present invention. In this embodiment, other structures, such as the first gate pad, the interlayer via, and possibly the interconnection structure such as the interconnection metal for connecting the electrode structure and the electrode pad, are omitted for clarity of the structure to be expressed in this embodiment. Compared to the first embodiment, the semiconductor device in this embodiment further includes a first interconnection metal 15 on the basis of fig. 2, and the first source-drain shielding sub-layer 141 located between the first drain pad 131 and the first source structure 123 is electrically connected to the first gate structure 122 through the first interconnection metal 15, so that the source-drain parasitic capacitance is reduced. Similarly, the shielding sub-layer can be electrically connected to other electrode structures or electrode pads according to the matching requirement of the parasitic capacitance, so as to adjust the corresponding parasitic capacitance.

In this embodiment, the area of the shielding sub-layer and the distance between the shielding sub-layer and the electrode structure or the electrode pad are set to adjust the parasitic capacitance, and the shielding layer is communicated with the potential of a certain electrode to achieve the purpose of adjusting the parasitic capacitance. For example, in the present embodiment, when both the first source-drain shield sublayers 141 are electrically connected to the gate electrode (only one is shown in fig. 4), the gate-source parasitic capacitances C may be formed, respectively _GS And parasitic capacitance C of gate and drain _GD Thereby avoiding the formation of drain-source parasitic capacitance C _DS 。

When the shielding sub-layer is electrically connected with the electrode structure through interconnection metal, the shielding sub-layer can also play a role of a field plate, and the purpose of reducing or regulating an electric field is achieved.

The first interconnection metal 15 in this example is not limited in shape, position, and number, so as to realize the interconnection function of the two structures. Therefore, the first interconnection metal 15 may be a plate-like or strip-like structure extending horizontally in the same dielectric layer, or a columnar structure extending vertically and passing through different dielectric layers and having a circular, square, trapezoid, triangle or the like cross section, or the like, and may avoid the interconnection metal of other electrodes by combining the two shapes according to the positions of the shielding sub-layer and the electrode portion (such as the electrode structure or the electrode pad) to be interconnected and the positions of other electrode structures, the electrode pad, and the shielding sub-layer.

Embodiment three.

Fig. 5 is a schematic longitudinal cross-sectional view of a semiconductor device structure according to a third embodiment of the present invention. In this embodiment, other structures, such as the first gate pad, the interlayer via, and possibly the interconnection structure such as the interconnection metal for connecting the electrode structure and the electrode pad, are omitted for clarity of the structure to be expressed in this embodiment. Compared with the first embodiment, the present embodiment provides multiple regions where the first drain pad 131 vertically overlaps the inner first source structure 123The number of layers, width, spacing, number and shape of the first source-drain shielding sub-layers 141 may be determined according to actual needs. In contrast to the schematic diagram 3, the present embodiment uses the source parasitic capacitance C between the source and the drain _SD The second capacitor C11 and the third capacitor C12 in the first embodiment are respectively changed into a plurality of corresponding capacitors, and by setting the number of the first source-drain shielding sublayers 141 electrically connected with the gate structure, a plurality of matching parasitic capacitors can be obtained. Therefore, in the manufacturing process, in the step of electrically connecting the gate structure and the first source-drain shielding sub-layer 141 by the interconnection metal, the number of the connected first source-drain shielding sub-layers 141 can be determined, so that the HEMT device meeting different matching requirements can be obtained, and the manufacturing process of the device is simplified.

Example four.

Fig. 6 is a schematic longitudinal cross-sectional view of a semiconductor device structure according to a fourth embodiment of the present invention. In this embodiment, other structures, such as the first gate pad, the interlayer via, and possibly the interconnection structure such as the interconnection metal for connecting the electrode structure and the electrode pad, are omitted for clarity of the structure to be expressed in this embodiment. Compared with the embodiment, in the present embodiment, a plurality of first source-drain shielding sub-layers 141 are provided in the vertically overlapped region of the first drain pad 131 and the first source structure 123 inside, and are divided into two layers and staggered. The distance between the first source-drain shielding sub-layer 141 and the first drain pad 131 and the first source structure 123 is adjusted by setting different positions of the first source-drain shielding sub-layer 141, so as to achieve the purpose of adjusting the parasitic capacitance.

Example five.

Fig. 7 is a schematic longitudinal cross-sectional view of a semiconductor device structure according to a fifth embodiment of the present invention. In the present embodiment, other structures such as gate pads, interlayer vias, and possibly interconnect metals for connecting electrode structures to electrode pads are omitted in order to clearly express the structures to be expressed in the present embodiment. The fifth embodiment provides a first gate-drain shielding sub-layer 142 in a horizontally overlapped region between the first gate structure 122 and the first drain structure 121 on the basis of the structure of the fourth embodiment, one first gate-drain shielding sub-layer 142 in the region being shown in fig. 7. Since an extremely high electric field, i.e., an extremely high voltage spike, is generated instantaneously from the first drain structure 121 to the first gate structure 122 during operation, the extremely high voltage spike can be attenuated into two small voltage spikes after the first gate-drain shield sub-layer 142 is added between the first gate structure 122 and the first drain structure 121, thereby effectively reducing the risk of gate breakdown.

Example six.

Fig. 8 is a schematic longitudinal sectional view of a semiconductor device structure according to a sixth embodiment of the present invention. In this embodiment, other structures, such as a gate structure, a first gate pad, an interlayer via, and possibly an interconnection structure such as an interconnection metal for connecting an electrode structure and an electrode pad, are omitted in order to clearly express the structure to be expressed in this embodiment. In the present embodiment, the first source structure 123 and the first drain structure 121 have respective field plate structures, and thus, a corresponding plurality of first source-drain shield sublayers 141 are included on a vertical plane of a horizontal overlap region between the first source structure 123 and the first drain structure 121.

Example seven.

Fig. 9 is a schematic longitudinal cross-sectional view of a semiconductor device structure according to a seventh embodiment of the present invention. In the present embodiment, other structures such as a gate structure, a first gate pad, a first source-drain shield sub-layer 141 located in a region where the first drain pad 131 vertically overlaps with the first source structure 123 inside, a first source-drain shield sub-layer 141 located in a horizontally overlapping region between the first drain structure 121 and the first source structure 123, and the like are omitted in order to clearly express the structure to be expressed in the present embodiment. In this embodiment, the electrode structure is connected to the electrode pad through the interlayer via and the necessary interconnect metal. An interconnection structure between the first source structure 123 and the first source pad 133 is shown in fig. 9 of the present embodiment. Wherein the interconnect structure includes a first inter-layer via 16 having metal implanted therein. Since the first drain pad 131 is above the first source structure 123 in this embodiment, the electrode structure and the electrode pad cannot be directly connected through the first interlayer via 16, but the two first interlayer vias 16 are electrically connected through the second interconnection metal 17 to achieve the electrical connection between the first source structure 123 and the first source pad 133.

In this embodiment, a via shield sub-layer 143 is wrapped around the dielectric region around the inner surface of the first inter-level via 16. Referring to fig. 10, a schematic cross-sectional view of the first interlayer via 16 of fig. 9 is shown. In the hole opening step, after the first interlayer via hole 16 is obtained, a ring hole is continuously formed around the first interlayer via hole 16, and when metal is grown, the metal can be grown in the first interlayer via hole 16 and the ring hole together, so that the illustrated via hole shielding sub-layer 143 is obtained, and the effect of reducing parasitic capacitance generated by the interlayer via hole, other electrode interlayer via holes or electrode structures, interconnection metal and the like is achieved.

Alternatively, the via shielding sublayer 143 may be electrically connected to the potential points of other electrodes as needed, thereby achieving the purpose of adjusting parasitic capacitance.

The second interconnection metal 17 in this example is not limited in shape, position, and number, so as to realize the interconnection function of the two structures. Therefore, the second interconnection metal 17 may be a plate-like or strip-like structure extending horizontally in the same dielectric layer, or a columnar structure extending vertically and passing through different dielectric layers and having a circular, square, trapezoid, triangle or the like cross section, or the like, and may avoid other structures by combining the two shapes according to the positions of the electrode structure to be interconnected and the electrode pad and the positions of other electrode structures, the electrode pad, and the shielding sub-layer.

Optionally, when the second interconnect metal 17 overlaps with the structure of the other electrode, a shielding sub-layer may be added at the overlapping region. The principle and structure are the same as those of the foregoing embodiments, and will not be described in detail herein.

The shielding sub-layer in the foregoing embodiments has a flat layer structure, however, the shielding sub-layer may form a shielding bridge, and a low-dielectric-constant dielectric material is filled in the shielding bridge, so that parasitic capacitance generated can be effectively reduced.

Example eight.

Fig. 11 is a schematic longitudinal sectional view of a semiconductor device structure according to an eighth embodiment of the present invention. In the present embodiment, a shielding bridge (hereinafter referred to as a first shielding bridge 144) of a zigzag structure is included in the middle of two first source-drain shielding sublayers 141 shown in the drawing. The first shielding bridge 144 of the convex structure includes two first shielding sub-layers horizontally spaced apart and a second shielding sub-layer above the two first shielding sub-layers and covering the horizontally spaced apart region. The first shielding bridge 144 may be filled with air or a dielectric material with a low dielectric constant.

When air is in the first shielding bridge 144, the preparation process includes, for example: manufacturing composite glue of stripping glue and photoresist at the position of the first shielding bridge 144 above the first passivation dielectric layer 115 to obtain a composite glue bump above the first passivation dielectric layer 115, and shaping the composite glue bump after high-temperature baking; depositing a layer of metallic titanium film or aluminum film or any other alloy film which is easy to wet corrosion on the first passivation dielectric layer 115 comprising the composite glue convex block, thereby shaping the upper surface of the composite glue convex block by metal; exposing and developing the composite glue bump area based on a photoetching process; removing the photoresist of the undeveloped part and the metal of the peripheral area of the composite rubber bump; removing photoresist by adopting an acetone solution, retaining the shaping metal, and forming an air bridge structure; a shielding sub-layer metal is deposited on the first passivation dielectric layer 115 with the air bridge structure, and the metal layer is etched to form a patterned structural pattern, so as to obtain the first shielding bridge 144 and other first source-drain shielding sub-layers 141 shown in fig. 11.

Another manufacturing process when air is inside the first shielding bridge 144 includes, for example: growing polysilicon (poly Si) over the first passivation dielectric layer 115 to obtain a polysilicon layer; etching the polysilicon layer at the position of manufacturing the first shielding bridge 144 to obtain a trapezoid polysilicon structure for generating an air bridge; depositing shielding layer metal on the surface of the first passivation dielectric layer 115 comprising the trapezoid polysilicon structure; etching shielding layer metal according to the number and the positions of the shielding sublayers and reserving a plurality of separated partial areas as the shielding sublayers; the trapezoid polysilicon structure is etched with a desilication liquid to obtain a first shielding bridge 144 with air inside.

The shielding bridge of the convex-shaped structure can also be formed by a shielding sub-layer covered on the convex steps of the medium. The dielectric boss steps are dielectric materials with low dielectric constants.

Example nine.

Fig. 12 is a schematic longitudinal sectional view of a semiconductor device structure according to a ninth embodiment of the present invention. In the present embodiment, a shielding bridge (hereinafter referred to as a second shielding bridge 145) of a concave structure is included in the middle of the two first source-drain shielding sublayers 141 shown in the drawings. The second shielding bridge 145 of the concave-shaped structure includes a dielectric groove and a shielding sub-layer covering the dielectric groove.

One process for preparing the second shielding bridge 145 with a concave-shaped structure includes: etching the first passivation dielectric layer 115 to form a recess; poly Si with a certain height is grown on the surface of the first passivation dielectric layer 115 with the groove (the height is designed according to the actual process and the electric field modulation requirement); then carrying out CMP mechanical planarization, grinding the upper top surface of the groove, and removing poly Si at other positions; depositing a shielding layer metal on the current structure; etching metal according to the number and the positions of the shielding sublayers, and reserving a plurality of separated partial areas as the shielding sublayers, wherein the metal area of the top surface of the groove is larger than that of the groove; the polysilicon in the recess is etched with a desilication solution, resulting in the second shield bridge 145 having a concave-shaped structure.

In addition, the second shielding bridge 145 may be a groove formed on the shielding sub-layer.

Embodiment ten.

Fig. 13 is a schematic cross-sectional view of a semiconductor device at a via between layers according to an embodiment ten of the present invention. Electrode pads of the same electrode of a semiconductor device are generally prepared to have larger areas on the surface of the device so as to facilitate wire bonding and interconnection during packaging, and the shape, occupied area and position of each electrode can be different according to requirements, so that a plurality of interlayer through holes are generally required when an internal electrode structure is electrically connected to the electrode pads on the surface, and parasitic capacitance can be generated between the electrode pads due to the pressure difference during use if the interlayer through holes of different electrodes have parallel relation in position. In this embodiment, the inter-conductive vias of different electrodes are offset from each other in position, and as shown in fig. 13, a plurality of inter-source vias 161 are electrically connected to the first source structure 123, and a plurality of inter-drain vias 162 are electrically connected to the first drain structure 121. The source inter-layer via 161 and the drain inter-layer via 162 are staggered, so that parasitic capacitance generated when the source inter-layer via 161 and the drain inter-layer via 162 are opposite is avoided.

For clarity of illustration of the features of the present embodiment, fig. 13 only shows the electrode structures and the interlayer vias, but of course includes other structures of the semiconductor device, and the shapes of the electrode structures and the interlayer vias shown in fig. 13 are also merely examples, which may be in other various shapes, numbers and layouts. And may also include shielding sublayers added at various positions in the foregoing embodiments, where in implementation, a corresponding implementation may be selected according to actual needs.

Example eleven.

Fig. 14 is a schematic longitudinal sectional view of a semiconductor device according to an eleventh embodiment of the present invention. The present embodiment describes the structure of a semiconductor device using an enhancement MOSFET as an example. The MOSFET in this embodiment uses a P-type silicon wafer as the second substrate 211, two N-type regions with high doping concentration are diffused on the second substrate 211 by a diffusion process, a layer of silicon dioxide is covered on the upper surface of the second substrate 211 as the first dielectric layer 212, then two ohmic contact electrodes are led out from the two N-type regions with high doping concentration through the second interlayer via 26, a metal layer is grown on the silicon dioxide surface, and etching is performed to obtain three bonding pads respectively, wherein the second drain bonding pad 231 and the second source bonding pad 233 which are electrically connected with the two N-type regions with high doping concentration through the second interlayer via 26, and the other is the second gate bonding pad 232. In this embodiment, the two N-type structures with high doping concentrations are respectively used as the second drain structure 221 and the second source structure 223, and the surface electrode pads electrically connected to the two N-type structures are respectively the second drain pad 231 and the second source pad 233. A metal layer is grown on the substrate portion as a substrate electrode pad 234.

Parasitic capacitance in the MOS transistor is mainly generated between the grid electrode and the substrate, between the grid electrode and the source electrode and between the drain electrode. Specifically, silicon-based gate-source parasitic capacitance C _GS-Si Is the sum of the parasitic capacitance formed between the second gate pad 232 and the second source pad 233 and the parasitic capacitance formed between the second gate pad 232 and the second substrate 211 near the source region; silicon-based gate-drain parasitic capacitance C _GD-Si Is the sum of the parasitic capacitance formed between the second gate pad 232 and the second drain pad 231 and the parasitic capacitance formed between the second gate pad 232 and the second substrate 211 near the drain region; regarding silicon-based source drain parasitic capacitance C _DS-Si Since the second source pad 233 is connected to the substrate electrode pad 234, a silicon-based source drain parasitic capacitor C _DS-Si Is the PN junction capacitance between the drain region (second drain structure 221 in fig. 14) and the second substrate 211.

In order to reduce or adjust the parasitic capacitance, the semiconductor device structure in the present embodiment further includes a plurality of shielding sublayers, such as two second gate-source shielding sublayers 241 located between the second gate pad 232 and the second source pad 233 and between the second gate pad 232 and the second source structure 223, two 242 located between the second gate pad 232 and the second drain pad 231 and between the second gate pad 232 and the second drain structure 221, a second source-drain shielding sublayer 243 located under the second drain structure 221 in the second substrate 211, and the like. Of course, a shielding sub-layer may be disposed around the second interlayer via 26, and the plurality of interlayer vias may be offset from each other. The specific structure is referred to the foregoing embodiments one to ten, and will not be described herein.

The shielding sub-layers in the embodiment can be respectively and electrically connected with the electrode pads or the electrode structures according to the requirement, so that the related parasitic capacitance is increased or reduced, and the size of the increased or reduced parasitic capacitance can be adjusted according to the number of the electrically connected shielding sub-layers or the area and the distance of the shielding sub-layers.

When the MOSFET and the HEMT of the structure of the embodiment form a Cascode device, the purpose of matching parasitic capacitance of the MOSFET and the HEMT can be achieved by arranging respective shielding sublayers in the MOSFET and the HEMT respectively, so that an additional compensation capacitor can be omitted.

Example twelve.

Fig. 15 is a schematic longitudinal sectional view of a semiconductor device according to a twelfth embodiment of the present invention. The semiconductor device in this embodiment is a diode, and P-type impurities are diffused on an N-type silicon single crystal wafer 311 to obtain a P region 32, and a PN junction is formed between the P region 32 and the N region. A layer of silicon dioxide is covered over the P region 32 as a second dielectric layer 312, openings 36 are formed at positions corresponding to the P region 32, metal is grown inside and electrically connected to the anode pad 331 on the surface, and metal is grown at the bottom of the N-type silicon single crystal wafer 311 as a cathode pad 332. Since the PN junction is equivalent to a capacitor having P region 32 and N region as plates, it is called junction capacitance or parasitic capacitance. When PN junction is forward biased, junction capacitance mainly depends on diffusion capacitance, and capacitance value is large. When PN junction is reversely biased, junction capacitance depends on barrier capacitance and is small. When the diode is applied to a high-frequency communication circuit, the size of the junction capacitance influences the communication effect, and experiments prove that the smaller the junction capacitance of the diode is, the better the circuit performance is. In this embodiment, in order to be able to reduce the junction capacitance, the size of the junction capacitance may be adjusted by adding the shielding layer 34 in the N region as the junction capacitance plate, and by setting the area of the shielding layer and the distance from the P region 32.

In summary, the present invention provides a semiconductor device, in which the size of the parasitic capacitance is adjusted by adding the shielding layer, so that the requirement of matching the parasitic capacitance can be satisfied when the semiconductor device and other devices form a related circuit, thereby reducing the dependence on the external compensation capacitance, and avoiding the additional problems of the external device such as large packaging difficulty and increased failure risk.

The above embodiments are provided for illustrating the present invention and not for limiting the present invention, and various changes and modifications may be made by one skilled in the relevant art without departing from the scope of the present invention, therefore, all equivalent technical solutions shall fall within the scope of the present disclosure.

Claims

1. A semiconductor device, comprising:

a device functional region;

two or more electrode structures formed inside the device functional regions, respectively;

two or more electrode pads formed on the surface of the device functional region, respectively, each electrode structure being electrically connected to at least one electrode pad through an interconnection structure in the device functional region to form one electrode; and

a shielding layer comprising one or more shielding sublayers formed between different electrodes.

2. The semiconductor device of claim 1, wherein an electrode pad of one electrode is located over an electrode structure of the other electrode, and one or more shielding sublayers are located at vertically overlapping regions between the electrode pad and the electrode structure.

3. The semiconductor device of claim 2, wherein the plurality of shield layers in the vertical overlap region between the electrode pad and the electrode structure are located in the same plane or are located in different planes with an up-down offset.

4. A semiconductor device according to claim 1 or 2 or 3, characterized in that the horizontal overlap area between the electrode structures of the different electrodes comprises one or more shielding sublayers; alternatively, the horizontal overlap region between the electrode pads of the different electrodes includes one or more shielding sublayers.

5. The semiconductor device of claim 4, wherein the plurality of shield layers in the horizontal overlap region between electrode structures of different electrodes are located in the same vertical plane or are located in different vertical planes with a left-right offset.

6. The semiconductor device of claim 1, wherein one or more of the plurality of shield sublayers are electrically connected to electrode structures and/or electrode pads of one or more electrodes through a first interconnect metal for adjusting parasitic capacitance between different electrodes.

7. The semiconductor device of claim 1, wherein the one or more shield sublayers form one or more shield bridges.

8. The semiconductor device of claim 7, wherein the shielding bridge is in a convex or concave configuration.

9. The semiconductor device of claim 8, wherein the shielding bridge of the zig-zag structure comprises two first shielding sublayers spaced apart horizontally and a second shielding sublayer overlying the two first shielding sublayers covering the horizontally spaced apart regions; or the shielding bridge with the convex-shaped structure is formed by a shielding sub-layer covered on the convex steps of the medium.

10. The semiconductor device of claim 8, wherein the shielding bridge of the concave structure comprises a dielectric trench and a shielding sub-layer covering the dielectric trench; or, the shielding bridge with the concave-shaped structure is a groove formed on the shielding sub-layer.

11. The semiconductor device of claim 1, wherein the interconnect structure in the device functional region comprises an inter-level via, wherein a dielectric region surrounding an inner surface of the inter-level via is wrapped with a shielding sub-layer.

12. A semiconductor device according to claim 1 or 11, wherein the inter-layer vias of the electrode structures of the different electrodes are offset from each other.

13. The semiconductor device of claim 11, wherein the interconnect structure in the device functional region comprises a second interconnect metal, including one or more shield sublayers between the second interconnect metal of one electrode and the electrode structure of the other electrode; and/or including one or more shielding sublayers between the second interconnect metal of one electrode and the electrode pad of the other electrode; and/or one or more shielding sublayers are included between the second interconnect metal of one electrode and the second interconnect metal of the other electrode.

14. The semiconductor device of claim 1, wherein the device functional region is a GaN power device functional region and the electrodes are a HEMT gate, a HEMT source, and a HEMT drain.

15. The semiconductor device of claim 1, wherein the device functional region is a MOS transistor functional region and the electrodes are a MOS gate, a MOS source, and a MOS drain.

16. The semiconductor device of claim 1, wherein the device functional region is a diode functional region and the electrodes are an anode and a cathode.

17. A method of manufacturing a semiconductor device, comprising:

providing a device functional area;

providing more than two electrode structures in the device functional region;

one or more shielding sublayers are provided between the different electrodes.