CN116504742A - Frame for semiconductor package, method for manufacturing the same, and method for packaging the same - Google Patents
Frame for semiconductor package, method for manufacturing the same, and method for packaging the same Download PDFInfo
- Publication number
- CN116504742A CN116504742A CN202310737679.1A CN202310737679A CN116504742A CN 116504742 A CN116504742 A CN 116504742A CN 202310737679 A CN202310737679 A CN 202310737679A CN 116504742 A CN116504742 A CN 116504742A
- Authority
- CN
- China
- Prior art keywords
- frame
- layer
- gold
- powder
- pure
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 42
- 238000000034 method Methods 0.000 title claims abstract description 41
- 238000004806 packaging method and process Methods 0.000 title claims abstract description 40
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 38
- 239000000758 substrate Substances 0.000 claims abstract description 45
- 239000010935 stainless steel Substances 0.000 claims abstract description 38
- 229910001220 stainless steel Inorganic materials 0.000 claims abstract description 38
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 63
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 claims description 51
- 229910052737 gold Inorganic materials 0.000 claims description 48
- 239000010931 gold Substances 0.000 claims description 48
- 229910052709 silver Inorganic materials 0.000 claims description 40
- 239000004332 silver Substances 0.000 claims description 40
- 229910052751 metal Inorganic materials 0.000 claims description 39
- 239000002184 metal Substances 0.000 claims description 38
- 238000004512 die casting Methods 0.000 claims description 33
- 239000000843 powder Substances 0.000 claims description 21
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 19
- 238000005245 sintering Methods 0.000 claims description 14
- 238000010438 heat treatment Methods 0.000 claims description 12
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 11
- 238000001746 injection moulding Methods 0.000 claims description 9
- 238000003466 welding Methods 0.000 claims description 4
- 239000000853 adhesive Substances 0.000 claims description 3
- 230000001070 adhesive effect Effects 0.000 claims description 3
- 238000005520 cutting process Methods 0.000 claims description 3
- 230000003647 oxidation Effects 0.000 claims description 3
- 238000007254 oxidation reaction Methods 0.000 claims description 3
- 238000007788 roughening Methods 0.000 claims description 3
- 238000000227 grinding Methods 0.000 claims description 2
- 238000000465 moulding Methods 0.000 claims 1
- 230000008569 process Effects 0.000 abstract description 24
- 229910000881 Cu alloy Inorganic materials 0.000 abstract description 8
- 239000000463 material Substances 0.000 description 15
- 229910052802 copper Inorganic materials 0.000 description 14
- 239000010949 copper Substances 0.000 description 14
- 238000005516 engineering process Methods 0.000 description 6
- 235000012431 wafers Nutrition 0.000 description 5
- 238000011161 development Methods 0.000 description 4
- 238000002844 melting Methods 0.000 description 4
- 230000008018 melting Effects 0.000 description 4
- 229910052759 nickel Inorganic materials 0.000 description 4
- 238000013461 design Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000009713 electroplating Methods 0.000 description 3
- 230000007613 environmental effect Effects 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 150000002739 metals Chemical class 0.000 description 3
- 239000011148 porous material Substances 0.000 description 3
- 238000012545 processing Methods 0.000 description 3
- 238000012360 testing method Methods 0.000 description 3
- XEEYBQQBJWHFJM-UHFFFAOYSA-N Iron Chemical compound [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 description 2
- 230000005540 biological transmission Effects 0.000 description 2
- 238000009826 distribution Methods 0.000 description 2
- 229910052736 halogen Inorganic materials 0.000 description 2
- 150000002367 halogens Chemical class 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 238000013508 migration Methods 0.000 description 2
- 230000005012 migration Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000007747 plating Methods 0.000 description 2
- 239000011347 resin Substances 0.000 description 2
- 229920005989 resin Polymers 0.000 description 2
- 229910000679 solder Inorganic materials 0.000 description 2
- 239000007787 solid Substances 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- 241000416536 Euproctis pseudoconspersa Species 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 206010035148 Plague Diseases 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 241000607479 Yersinia pestis Species 0.000 description 1
- 230000002159 abnormal effect Effects 0.000 description 1
- 230000005856 abnormality Effects 0.000 description 1
- 230000004913 activation Effects 0.000 description 1
- 239000002390 adhesive tape Substances 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 239000013043 chemical agent Substances 0.000 description 1
- 230000008602 contraction Effects 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 230000032798 delamination Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 239000003814 drug Substances 0.000 description 1
- -1 firstly Substances 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- 239000000383 hazardous chemical Substances 0.000 description 1
- 238000007731 hot pressing Methods 0.000 description 1
- 230000008676 import Effects 0.000 description 1
- 230000006698 induction Effects 0.000 description 1
- 238000007689 inspection Methods 0.000 description 1
- 229910052742 iron Inorganic materials 0.000 description 1
- 230000009191 jumping Effects 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 230000005415 magnetization Effects 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 238000009768 microwave sintering Methods 0.000 description 1
- 238000013021 overheating Methods 0.000 description 1
- 238000012858 packaging process Methods 0.000 description 1
- 238000012536 packaging technology Methods 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 238000012827 research and development Methods 0.000 description 1
- 239000012266 salt solution Substances 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- 238000001179 sorption measurement Methods 0.000 description 1
- 238000004781 supercooling Methods 0.000 description 1
- 239000002699 waste material Substances 0.000 description 1
Abstract
The invention relates to a frame for semiconductor packaging, a manufacturing method thereof and a packaging method thereof, which relate to the field of semiconductor integrated circuit packaging. The invention solves the technical problems that the semiconductor lead frame in the prior art is easy to deform in the production and manufacture process, and the bottom of the frame is unsupported or has low supporting strength. The hardness and the supporting strength are both stronger than those of the punched and etched copper alloy frame, and the bottom of the stainless steel substrate is of a pure flat structure, so that the problem of deformation can be avoided in production and manufacture.
Description
Technical Field
The present invention relates to the field of semiconductor integrated circuit packaging, and more particularly, to a frame for semiconductor packaging, a method for manufacturing the same, and a packaging method.
Background
The current semiconductor lead frame for packaging is formed by processing a copper plate made of copper alloy through a stamping process (the copper plate is stamped once or a plurality of times by using a specific die by stamping equipment) or an etching process (the copper plate is processed by exposure, development, chemical liquid medicine etching and the like); the development cost of the die used in the stamping process is huge, the single development cost is high, and the loss is large once the research and development of the subsequent products are failed; the etching process has low initial development cost, but the subsequent unit price is high, and the mass production and use cost is high. Meanwhile, 80% of metal is consumed in the two processes, and the economic cost and the resource waste are high for nonferrous metals such as gold, copper and the like because of less resource reserves in the nonferrous metals and large dependence on import.
Meanwhile, the currently used copper alloy base material has low purity, other elements such as iron, nickel and the like are more or less arranged in the copper alloy base material, the risk of magnetization exists in the subsequent use process, and products with magnetic requirements (such as Hall sensors, which utilize the magnetic induction principle to measure the speed, the angle direction and the like) cannot be used. In the present stage, the environmental protection requirements of various countries are improved, ROHS (Restriction of Hazardous Substance, ROHS environmental protection certification), HF (Halogen Free or low Halogen certification) and the like have higher requirements on products, so that impurities in the used materials must be controlled.
Meanwhile, the frame process of small-size products is not easy to meet, especially QFN (Quad Flat No-leads Package) products with Package size smaller than 1mm in length and smaller than 1mm in width and smaller than 0.5mm in height, QFP (Quad Flat Package, square Flat packaging technology) products, the used copper alloy frame is very thin, the thickness is smaller than 0.152mm, the overall strength of frame strips is weaker, and the processes of production, transportation, inspection and the like are extremely easy to cause deformation and warpage, so that processing is difficult, plastic Package material overflow abnormality is easy to cause during injection molding, and appearance and weldability failure occur; if other anomalies such as jamming occur, the whole product is scrapped. The QFN half-etched frame bottom design is not a planar design, and a half of the frame bottom area is etched by chemical agents, which causes the problem of no support or low support strength at the frame bottom, and when DB (Die Bond, the process of separating a chip from a carrier, or the process of connecting a chip from a package substrate) and WB (Wire Bonding), the process of sequentially Bonding thin metal wires or metal strips on pads of a chip and a lead frame or a package substrate to form circuit interconnections, i.e., wire Bonding, the uncontrollable runout is caused, and abnormal conditions such as cold Bonding, ball drop or center shift of a top piece are caused, which greatly plagues the reliability of the product.
Disclosure of Invention
The invention provides a semiconductor packaging frame, a manufacturing method thereof and a packaging method thereof, which solve the technical problems that the semiconductor lead frame in the prior art is easy to deform in production and manufacture, and the bottom of the frame is unsupported or has low supporting strength.
In a first aspect, the invention discloses a frame for packaging a semiconductor, comprising a stainless steel substrate, at least one pin connected to the back surface of the stainless steel substrate, wherein the pin comprises a gold layer, an intermediate layer and a silver layer, wherein the gold layer is formed by die casting pure gold powder on the stainless steel substrate, the intermediate layer is formed by die casting single pure metal powder on the gold layer, and the silver layer is formed by die casting pure silver powder on the intermediate layer.
The frame for semiconductor packaging is further improved in that the single pure metal powder of the intermediate layer is pure copper powder.
The frame for packaging the semiconductor is further improved in that the single pure metal powder of the intermediate layer is pure nickel powder.
The frame for semiconductor packaging of the present invention is further improved in that the thickness of the intermediate layer is greater than the thickness of the gold layer and the thickness of the silver layer.
The frame for semiconductor packaging is further improved in that the stainless steel substrate is SUS430 type stainless steel with the thickness of 0.15-0.25 mm.
In a second aspect, the present invention also provides a method for manufacturing a frame for semiconductor package, including the steps of:
baking the pure gold powder, the single pure metal powder and the pure silver powder;
manufacturing a gold layer of a pin, connecting a lower cavity of one die casting die with the stainless steel substrate, adding pure gold powder into the corresponding upper cavity, closing the upper cavity added with the pure gold powder and the corresponding lower cavity, heating and pressurizing to form a rough blank, and then placing the rough blank into a vacuum furnace for vacuum sintering;
sequentially manufacturing an intermediate layer of single pure metal powder and a silver layer of pure silver powder by using two sets of die-casting molds in the same manufacturing mode as the gold layer, wherein the intermediate layer is formed on the gold layer, the silver layer is formed on the intermediate layer, and at least one pin is formed through the gold layer, the intermediate layer and the silver layer;
and carrying out heat treatment on the stainless steel substrate and the whole pin, so as to form a tightly combined frame.
The frame for semiconductor package of the present invention is further improved in that after the heat treatment, the frame surface is subjected to an oxidation-resistant and roughening treatment.
In a third aspect, the present invention also provides a packaging method of a frame for semiconductor packaging, including the steps of:
providing the frame for semiconductor packaging as described above;
bonding the chip on the silver layer of the pin by conducting resin;
bonding, namely electrically connecting the chip and the silver layer through pressure welding and wire bonding;
plastic packaging, namely carrying out injection molding treatment on the bonded product;
and (3) tearing and cutting the substrate, adhering a film to the plastic cover of the product after plastic packaging, and tearing the stainless steel substrate from the product after injection molding.
The frame for semiconductor packaging is further improved in that wafers of chips are ground and thinned before die bonding is performed, and the overall plastic packaging thickness is reduced.
Compared with the prior art, the invention has positive and obvious effects. The invention combines the stainless steel substrate and the pure metal powder to form the packaging frame, thereby solving the technical problems that the semiconductor lead frame in the prior art is easy to deform in the production and manufacture process, and the bottom of the frame has no support or low support strength. The hardness and the supporting strength are both stronger than those of the punched and etched copper alloy frame, and the bottom of the stainless steel substrate is of a pure flat structure, so that the problem of deformation can be avoided in production and manufacture.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for the description of the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a longitudinal sectional view of a semiconductor package frame according to the present invention.
Fig. 2 is a bottom view of the frame for semiconductor package of the present invention.
Fig. 3 is a longitudinal sectional view of the semiconductor package frame packaging method of the present invention after die bonding.
Fig. 4 is a longitudinal sectional view of the semiconductor package frame of the present invention after bonding wires of the chip.
Fig. 5 is a longitudinal sectional view of a semiconductor package frame according to the present invention after injection molding of a chip.
Fig. 6 is a longitudinal sectional view of a die stainless substrate of the frame packaging method for semiconductor package of the present invention after being peeled off.
Fig. 7 is a bottom view of the frame packaging method for semiconductor package of the present invention after bonding wires of the chip.
In the figure, 1, the back of a pin; 2. the front surface of the pin; 3. a stainless steel substrate; 4. a gold layer; 5. an intermediate layer; 6. a silver layer; 7. a chip; 8. welding wires; 9. conducting resin; 10. plastic package body
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
As shown in fig. 1 and 2, the present invention provides a frame for semiconductor package, comprising a stainless steel substrate 3, at least one lead connected to the back surface of the stainless steel substrate 3, the lead comprising a gold layer 4 provided from bottom to top, an intermediate layer 5 and a silver layer 6 for carrying a chip 7 or bonding wires 8, the gold layer 4 being formed by pure gold powder die-casting on the stainless steel substrate 3, the intermediate layer 5 being formed by single pure metal powder die-casting on the corresponding gold layer 4, the silver layer 6 being formed by pure silver powder die-casting on the corresponding intermediate layer 5. The small square frame is a part of the frame, which is exposed out of the back of the plastic package body 10, namely the back 1 of the pins (namely the bottom surface of the gold layer), the back of the single product is nine pins arranged in a matrix, and other areas are filled with the plastic package body 10, and as the exposed area is the gold layer 4, the SMT (Surface Mounted Technology, surface assembling technology or surface mounting technology) process can be carried out on a PCB (Printed Circuit Board ) without electroplating treatment, and the front carrying chip 7 and the routing position of the frame are silver layers 6, which have better combination and wettability with solder such as tin. Between the gold layer 4 and the silver layer 6 is a copper layer. In this embodiment, the size of the front surface 2 of the lead is 35-50 μm larger than that of the back surface 1 of the lead, which serves as a base island and carries the chip 7, and the front surface of the lead is a silver layer which can bond the bonding wires 8 (gold wires, copper wires, etc.), so that the cost of the silver layer is lower than that of other metals which can achieve the same effect.
Preferably, the single pure metal powder of the intermediate layer 5 is pure copper powder. Copper is selected when conductivity is high or when there is no magnetic product.
Preferably, the single pure metal powder of the intermediate layer 5 is pure nickel powder. When a frame having high corrosion resistance is required, a nickel material is required.
Preferably, the thickness of the intermediate layer 5 is greater than the thickness of the gold layer 4 and the thickness of the silver layer 6. Pins of the powder die-casting frame are formed on the stainless steel substrate 3 by using a die for hot pressing, and are generally formed by a first gold layer 4, a second nickel layer or copper layer; and the third layer of silver. The gold layer 4 is combined with solder during the product SMT process (Surface Mounted Technology, surface mount technology or surface mount technology) to improve solderability. The nickel layer or the copper layer is positioned between the gold layer 4 and the silver layer 6 and serves as a main material layer of the frame to perform heat conduction and electric conduction operations; and has a high hardness, acting as a "skeleton" for the entire plastic package 10. The silver layer 6 is positioned on the uppermost surface of the lead frame, and can be better combined with bonding wires 8 (copper wires, gold wires or alloy wires, etc.) during the bonding process. And if the magnetic requirement exists, the plating layers of gold, copper and silver are adopted, and no other materials which can be magnetized exist, so that the nonmagnetic product is truly realized.
Preferably, the stainless steel substrate 3 is SUS430 type stainless steel having a thickness of 0.15 to 0.25 mm. In this embodiment, a 0.15 to 0.25mm SUS430 (japanese SUS series stainless steel) stainless steel substrate 3 is used, which serves to receive a frame and optimize a packaging process, and the process of die casting, sintering, heat treatment, polishing, etc. of a desired metal powder is performed on this substrate a plurality of times to make a desired frame shape. Since the SUS430 stainless steel substrate 3 is used, the hardness and the supporting strength are both stronger than those of the punched and etched copper alloy frame, and the bottom of SUS430 is of a flat structure, so that the problems of deformation and the like can be well avoided in the production and manufacture, and the problem of jumping of the frame in the DB (Die Bond), the process of separating the chip from the carrier, and the process of connecting the chip to the package substrate, and the WB (Wire Bonding), in which thin metal wires or metal strips are sequentially punched on the pads of the chip and the lead frame or the package substrate to form circuit interconnections, i.e., wire Bonding) is solved, and the soldering strength is ensured. Meanwhile, the loss of the design metal is only 1-5%, and the loss of the metal is 50% in general processing, so that the resource utilization rate is effectively improved.
On the other hand, the invention also provides a manufacturing method of the frame for semiconductor packaging, which comprises the following steps:
baking the pure gold powder, the single pure metal powder and the pure silver powder;
providing three sets of die casting molds, wherein each set of die casting mold comprises at least one pair of lower die cavities and upper die cavities which are matched with each other;
manufacturing a gold layer 4 of a pin, connecting a lower cavity of one set of die casting die with the stainless steel substrate 3, adding pure gold powder into the corresponding upper cavity, closing the upper cavity added with the pure gold powder and the corresponding lower cavity, heating and pressurizing to form a rough blank, and then placing the rough blank into a vacuum furnace for vacuum sintering;
sequentially manufacturing an intermediate layer 5 of single pure metal powder and a silver layer 6 of pure silver powder by using two sets of die-casting molds in the same manufacturing mode as the gold layer 4, wherein the intermediate layer 5 is formed on the gold layer 4, the silver layer 6 is formed on the intermediate layer 5, and at least one pin is formed through the gold layer 4, the intermediate layer 5 and the silver layer 6;
the stainless steel substrate 3 and the whole pins are heat treated to form a tightly bonded frame. The heat treatment can further reduce voids, increase density, and reduce the risk of delamination between the different metal layers.
Preferably, after the heat treatment, the frame surface is subjected to an oxidation-resistant and roughening treatment. The operation can be selected to be carried out according to actual needs.
When selecting materials, firstly, stainless steel SUS430 with the thickness of 0.15mm is selected as a carrier, and the base material is not easy to deform and warp under external force, but attention should be paid to thermal expansion and cold contraction caused by overheating or supercooling. The gold layer 4, the copper layer and the silver layer 6 are die-cast by pure gold powder, pure copper powder and pure silver powder. Material acquisition: the purchased pure solid metal is crushed mechanically or the pure metal is reduced from the metal salt solution by replacement, and then the crushing is carried out, so that the high-purity gold powder, silver powder and copper powder are obtained. The obtained material needs to be baked for one time before use, moisture is removed, and the baking temperature is lower than the melting point of each metal powder, so that the metal layers are prevented from being combined and not being combined in the die casting and sintering processes, and larger pores are caused. And (3) manufacturing a die casting die, calculating the thickness of each metal layer according to the designed frame shape, materials and the performances required to be achieved by the materials, and determining the shape and depth of a die cavity. The frame uses three metal elements, namely gold, copper and silver, and the first die-casting die is respectively designed according to the shape and thickness of three metal layers: gold layer 4 cavity mould, second die casting mould: copper layer cavity mould, third die casting die: and (3) a silver layer 6 cavity die, and performing three times of die casting and three times of vacuum sintering. The metal powder is used for hot die casting, vacuum sintering or microwave sintering is used for manufacturing the lead frame with high purity, no impurity and good compactness.
When the gold layer 4 is die-cast, the SUS430 substrate is connected with the lower cavity, and the corresponding gold powder dosage is added into the upper cavity according to the designed shape area of the gold layer 4 and the thickness of the gold layer 4. After the upper and lower cavities are clamped, the heating temperature is under the melting point of gold after heating and pressurizing for a certain time, and a first gold layer 4 of a frame is formed on SUS430, wherein the metal in the rough blank has uneven distribution or pores. And placing the material into a vacuum furnace, and performing vacuum sintering for more than 60 minutes, wherein the sintering is performed at the temperature of 500-800 ℃ and the melting temperature of the body is lower than the melting temperature of the body. Sintering belongs to a solid diffusion process, and because the concentration gradient, the temperature gradient and the pressure gradient can lead to mass transmission, the temperature is high enough, the more intense the atomic thermal vibration is, the larger the atomic activation migration probability is, the longer the migration distance is, the particles are combined together through mass transmission in the sintering process, the pores are reduced, and the atomic distribution of the gold layer 4 is more uniform and compact.
When the die casting of the middle layer 5 is performed, the die casting and sintering are performed on the finished gold layer 4 by adopting the same die casting and sintering principle as that of the gold layer 4, so as to form the middle layer 5 corresponding to the frame; in the die casting of the silver layer 6, the same die casting and sintering principle as the gold layer 4 is used to die cast and sinter the completed intermediate layer 5 to form the silver layer 6 of the frame.
On the other hand, the invention also provides a packaging method of the frame for packaging the semiconductor, which comprises the following steps:
providing the frame for semiconductor packaging as described above;
die bonding, as shown in fig. 3, the chip 7 is transversely adhered to the silver layer 6 of the pin through the conductive adhesive 9; the chip 7 is adhered to the silver layer through the conductive adhesive 9, and at the moment, the stainless steel substrate 3 is used, so that the bottom flatness is high, the back surface is of a planar structure, and uncontrollable runout does not exist;
bonding, as shown in fig. 4 and 5, the chip 7 and the silver layer are electrically connected by pressure welding and wire bonding; at the moment, the stainless steel substrate 3 is used, so that the bottom flatness is high, the back surface is of a planar structure, uncontrollable runout does not exist, the vacuum adsorption back surface effect is optimal, and the bonding quality and reliability of the product are greatly superior to those of the original process method;
plastic packaging, as shown in fig. 6, the bonded product is subjected to injection molding treatment; the bottom of the stainless steel substrate 3 is of a pure flat structure, the flatness of the plane is high, and the plastic overflow during the injection molding stage can be avoided (due to the gold plating layer 4 on the back surface, the electroplating process is avoided, the subsequent cutting test is directly performed, the sealing and testing delivery period is shortened, the electroplating labor, the electric power, the environmental protection and the material cost are avoided);
the substrate is torn and cut, as shown in fig. 7, a film is stuck on a plastic cover of the product after plastic packaging, and the stainless steel substrate 3 is torn off from the product after injection molding; thereafter, PKG SAW (Package Saw, cut substrate) dicing separation was performed to obtain the desired finished product. The torn SUS430 substrate can be recycled. The separated product is cut and enters the testing stage.
Preferably, before die bonding, the wafer of the chip 7 is ground and thinned, so that the overall plastic package thickness is reduced, and the risk that the bonding wires 8 are exposed out of the plastic package body 10 is reduced. Thickness of wafer grinding and thinning of chip 7: the silicon single-substance wafer is 200-250 um, and the thickness of the gallium arsenide and silicon carbide wafer is 100 um.
In order to prevent flash, the conventional QFN (Quad Flat No-leads Package) uses a thermal plastic type high temperature adhesive tape attached to the back surface, which is expensive, and there is No similar substitute product in China, and it needs to be purchased from foreign manufacturers. The bottom of SUS430 is of a pure flat structure, the flatness of the plane is high, the hardness is high, the mechanical strength is strong, the deformation is not easy to occur, and the glue overflow during injection molding can be avoided; before the product is cut and separated, the product can be recovered and reused after being stripped from the product.
The invention combines the stainless steel substrate and the pure metal powder to form the packaging frame, thereby solving the technical problems that the semiconductor lead frame in the prior art is easy to deform in the production and manufacture process, and the bottom of the frame has no support or low support strength. The hardness and the supporting strength are both stronger than those of the punched and etched copper alloy frame, and the bottom of the stainless steel substrate is of a pure flat structure, so that the problem of deformation can be avoided in production and manufacture.
None of the inventions are related to the same or are capable of being practiced in the prior art. The present invention is not limited to the above-mentioned embodiments, but is not limited to the above-mentioned embodiments, and any simple modification, equivalent changes and modification made to the above-mentioned embodiments according to the technical matters of the present invention can be made by those skilled in the art without departing from the scope of the present invention.
Claims (9)
1. The frame for semiconductor packaging is characterized by comprising a stainless steel substrate and at least one pin connected to the surface of the stainless steel substrate, wherein the pin comprises a gold layer, an intermediate layer and a silver layer, wherein the gold layer is arranged from bottom to top, the silver layer is used for bearing a chip or bonding wires, the gold layer is formed by die casting pure gold powder on the stainless steel substrate, the intermediate layer is formed by die casting single pure metal powder on the gold layer, and the silver layer is formed by die casting pure silver powder on the intermediate layer.
2. The frame for semiconductor packages according to claim 1, wherein the single pure metal powder of the intermediate layer is pure copper powder.
3. The frame for semiconductor package according to claim 1, wherein the single pure metal powder of the intermediate layer is pure nickel powder.
4. The frame for semiconductor package according to claim 1, wherein the thickness of the intermediate layer is greater than the thickness of the gold layer and the thickness of the silver layer.
5. The frame for semiconductor package according to claim 1, wherein the stainless steel substrate is SUS430 type stainless steel having a thickness of 0.15 to 0.25 mm.
6. A method of manufacturing a frame for semiconductor packaging, comprising the steps of:
baking the pure gold powder, the single pure metal powder and the pure silver powder;
providing three sets of die casting molds, wherein each set of die casting mold comprises at least one pair of lower die cavities and upper die cavities which are matched with each other;
manufacturing a gold layer of a pin, connecting a lower cavity of one die casting die with a stainless steel substrate, adding pure gold powder into the corresponding upper cavity, closing the upper cavity added with the pure gold powder and the corresponding lower cavity, heating and pressurizing to form a rough blank, and then placing the rough blank into a vacuum furnace for vacuum sintering;
sequentially manufacturing an intermediate layer of single pure metal powder and a silver layer of pure silver powder by using two sets of die-casting molds in the same manufacturing mode as the gold layer, wherein the intermediate layer is formed on the gold layer, the silver layer is formed on the intermediate layer, and at least one pin is formed through the gold layer, the intermediate layer and the silver layer;
and carrying out heat treatment on the stainless steel substrate and the whole pin, so as to form a tightly combined frame.
7. The method of manufacturing a frame for semiconductor package according to claim 6, wherein after the heat treatment, the frame surface is subjected to an oxidation-resistant and roughening treatment.
8. A packaging method of a frame for semiconductor packaging, comprising the steps of:
providing the frame for semiconductor packaging according to claim 1;
fixing the chip, namely covering the chip on the corresponding pin, and adhering the chip on the silver layer of the pin by using conductive adhesive;
bonding, namely electrically connecting the chip and the silver layer through pressure welding and wire bonding;
plastic packaging, namely carrying out injection molding treatment on the bonded product;
and (3) tearing and cutting the substrate, adhering a film to the plastic-sealed product on the plastic cover, and tearing the stainless steel substrate from the plastic-sealed product.
9. The method of claim 8, wherein the wafer of the die is thinned by grinding to reduce the overall molding thickness before die bonding.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310737679.1A CN116504742B (en) | 2023-06-21 | 2023-06-21 | Frame for semiconductor package, method for manufacturing the same, and method for packaging the same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310737679.1A CN116504742B (en) | 2023-06-21 | 2023-06-21 | Frame for semiconductor package, method for manufacturing the same, and method for packaging the same |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN116504742A true CN116504742A (en) | 2023-07-28 |
| CN116504742B CN116504742B (en) | 2023-12-08 |
Family
ID=87328688
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202310737679.1A Active CN116504742B (en) | 2023-06-21 | 2023-06-21 | Frame for semiconductor package, method for manufacturing the same, and method for packaging the same |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN116504742B (en) |
Citations (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0590444A (en) * | 1991-09-26 | 1993-04-09 | Toshiba Corp | Ceramic circuit board |
| US6046496A (en) * | 1997-11-04 | 2000-04-04 | Micron Technology Inc | Chip package |
| US20010047880A1 (en) * | 1999-03-01 | 2001-12-06 | Abbott Donald C. | Double sided flexible circuit for integrated circuit packages and method of manufacture |
| KR20130079131A (en) * | 2011-12-30 | 2013-07-10 | 조인셋 주식회사 | Smt compatible elastomer contact terminal and method for making the same |
| JP2017019111A (en) * | 2015-07-07 | 2017-01-26 | 日本電気株式会社 | Laminate molding device and laminate molding method |
| WO2017203717A1 (en) * | 2016-05-27 | 2017-11-30 | 地方独立行政法人大阪府立産業技術総合研究所 | Laminate-molding metal powder, laminate-molded article manufacturing method, and laminate-molded article |
| CN108022899A (en) * | 2016-10-28 | 2018-05-11 | 台达电子工业股份有限公司 | Power module and its manufacture method with lead member |
| JP6635227B1 (en) * | 2018-03-05 | 2020-01-22 | 三菱電機株式会社 | Manufacturing method of three-dimensional shaped object |
| CN111996405A (en) * | 2020-08-22 | 2020-11-27 | 江苏精研科技股份有限公司 | Method for preparing high-strength and high-conductivity copper alloy through metal injection molding |
| CN112349673A (en) * | 2020-11-10 | 2021-02-09 | 江西芯世达微电子有限公司 | Ultrathin packaging part based on bonding wire connection and manufacturing process thereof |
| CN114300437A (en) * | 2022-01-27 | 2022-04-08 | 佛山市蓝箭电子股份有限公司 | Frameless semiconductor packaging structure and preparation process thereof |
-
2023
- 2023-06-21 CN CN202310737679.1A patent/CN116504742B/en active Active
Patent Citations (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0590444A (en) * | 1991-09-26 | 1993-04-09 | Toshiba Corp | Ceramic circuit board |
| US6046496A (en) * | 1997-11-04 | 2000-04-04 | Micron Technology Inc | Chip package |
| US20010047880A1 (en) * | 1999-03-01 | 2001-12-06 | Abbott Donald C. | Double sided flexible circuit for integrated circuit packages and method of manufacture |
| KR20130079131A (en) * | 2011-12-30 | 2013-07-10 | 조인셋 주식회사 | Smt compatible elastomer contact terminal and method for making the same |
| JP2017019111A (en) * | 2015-07-07 | 2017-01-26 | 日本電気株式会社 | Laminate molding device and laminate molding method |
| WO2017203717A1 (en) * | 2016-05-27 | 2017-11-30 | 地方独立行政法人大阪府立産業技術総合研究所 | Laminate-molding metal powder, laminate-molded article manufacturing method, and laminate-molded article |
| CN108022899A (en) * | 2016-10-28 | 2018-05-11 | 台达电子工业股份有限公司 | Power module and its manufacture method with lead member |
| JP6635227B1 (en) * | 2018-03-05 | 2020-01-22 | 三菱電機株式会社 | Manufacturing method of three-dimensional shaped object |
| CN111996405A (en) * | 2020-08-22 | 2020-11-27 | 江苏精研科技股份有限公司 | Method for preparing high-strength and high-conductivity copper alloy through metal injection molding |
| CN112349673A (en) * | 2020-11-10 | 2021-02-09 | 江西芯世达微电子有限公司 | Ultrathin packaging part based on bonding wire connection and manufacturing process thereof |
| CN114300437A (en) * | 2022-01-27 | 2022-04-08 | 佛山市蓝箭电子股份有限公司 | Frameless semiconductor packaging structure and preparation process thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| CN116504742B (en) | 2023-12-08 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US9293396B2 (en) | Method for manufacturing semiconductor device, and semiconductor device | |
| US6812552B2 (en) | Partially patterned lead frames and methods of making and using the same in semiconductor packaging | |
| CN100385641C (en) | Semiconductor packaging with partially patterned lead frames and its making methods | |
| JP3619773B2 (en) | Manufacturing method of semiconductor device | |
| US8749035B2 (en) | Lead carrier with multi-material print formed package components | |
| WO2003103038A1 (en) | Partially patterned lead frames and methods of making and using the same in semiconductor packaging | |
| JP7089388B2 (en) | Semiconductor devices and methods for manufacturing semiconductor devices | |
| US8865524B2 (en) | Lead carrier with print-formed package components | |
| JP2015527753A (en) | Lead carrier with terminal pads by printing formation | |
| US20180047588A1 (en) | Lead carrier structure and packages formed therefrom without die attach pads | |
| CN116504742B (en) | Frame for semiconductor package, method for manufacturing the same, and method for packaging the same | |
| CN105225972A (en) | A kind of manufacture method of semiconductor package | |
| JP4901776B2 (en) | Lead frame, semiconductor device using the same, and production method thereof | |
| JP2011040640A (en) | Method for manufacturing semiconductor device | |
| CN111799243A (en) | Chip packaging substrate and manufacturing method thereof, chip packaging structure and packaging method | |
| US6940183B1 (en) | Compound filled in lead IC packaging product | |
| CN100456442C (en) | Semiconductor encapsulation structure possessing support part, and preparation method | |
| JP2017108191A (en) | Semiconductor device | |
| CN114883201A (en) | AQFN production method | |
| KR101384343B1 (en) | Method of manufacturing a semiconductor package having no chip mounting area | |
| JP2004172647A (en) | Semiconductor device | |
| CN111653542A (en) | Semiconductor package lead frame | |
| KR100187718B1 (en) | Method of manufacturing semiconductor package lead frame to prevent back flash | |
| JP2013165304A (en) | Manufacturing method of semiconductor device | |
| JP3705571B2 (en) | Manufacturing method of semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |