CN116502576A - Instruction stream tracking verification method and debugging system - Google Patents
Instruction stream tracking verification method and debugging system Download PDFInfo
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Abstract
The invention provides an instruction stream tracking verification method and a debugging system, wherein the system comprises an arbitration module, a verification module and an embedded tracking macro unit (ETM) which is used for being connected with each single core in a chip to be debugged in a one-to-one correspondence manner; the ETM is configured to: capturing recorded data generated after the single core connected with the single core actually runs preset excitation, encoding the recorded data into an actual data packet and sending the actual data packet to the arbitration module; the arbitration module is configured to: integrating and outputting the actual data packets of each single core into a path of debugging data packet according to the working frequency of each single core; the verification module is configured to: simulating a simulation data packet generated by each single core after the preset excitation is operated; and comparing the simulation data packet with the debugging data packet, and outputting a tracking verification result according to the comparison result. The debugging system can be suitable for heterogeneous multi-core chips with different types of single cores, and the application range of the debugging system is increased.
Description
Technical Field
The disclosure relates to the field of chip debugging, in particular to an instruction stream tracking verification method and a debugging system.
Background
The debugging system of the chip plays an important role in the debugging stage of the chip after the chip is manufactured and the problem positioning in the use process of the chip. In the prior art, a debug system CoreSight is provided, which can realize the purpose of exporting the running instruction stream (data stream) inside a chip and trace.
However, the existing debug system CoreSight cannot meet the debug requirements of heterogeneous multi-core chips.
Disclosure of Invention
The purpose of the present disclosure is to provide an instruction stream tracking verification method and a debug system, which can improve the use range and the use flexibility of the debug system.
According to one aspect of the present disclosure, there is provided a debugging method applied to a debugging system, the method comprising: the system comprises an arbitration module, a verification module and a plurality of embedded tracking macro units ETM, wherein the embedded tracking macro units ETM are used for being connected with each single core in a chip to be debugged in a one-to-one correspondence manner; the ETM is configured to: capturing recorded data generated after the single core connected with the single core actually runs preset excitation, encoding the recorded data into an actual data packet and sending the actual data packet to the arbitration module; the arbitration module is configured to: integrating and outputting the actual data packets of each single core into a path of debugging data packet according to the working frequency of each single core; the verification module is configured to: simulating a simulation data packet generated by each single core after the preset excitation is operated; and comparing the simulation data packet with the debugging data packet, and outputting a tracking verification result according to the comparison result.
In a possible implementation manner of the present disclosure, when the arbitration module integrates and outputs the actual data packet of each single core into one path of debug data packet according to the working frequency of each single core, the arbitration module is specifically configured to: combining the actual data packets sent by the ETM by adopting a weighted polling mode according to the weight ratio of each preset single-core weighted polling to obtain the debugging data packet; the weighted polling weight ratio of each single core is the ratio of the working frequencies of each single core.
In a possible implementation manner of the present disclosure, each ETM includes a comparison register, configured to set a start address of an instruction stream to be tracked in the preset stimulus, where the ETM captures recorded data generated after actually running the preset stimulus by a single core connected to the ETM, where the ETM is specifically configured to: and under the condition that the running pointer of the single core connected with the self is determined to point to the starting address of the instruction stream to be tracked, starting to grab the recorded data generated by the single core connected with the self.
In one possible implementation of the present disclosure, the start addresses configured in the compare registers corresponding to different single cores are the same or partially the same or completely different.
In a possible implementation manner of the present disclosure, the actual data includes a header information header and a payload information payload, where the header information indicates an identifier of a corresponding single core, and the payload information indicates a single instruction stream in the preset excitation; the data structure of the actual data packet comprises an identification field and a payload field;
the ETM encodes the recorded data into actual data packets, specifically configured to: and filling the record data representing the header information into the identification field, and filling the record data representing the payload information into the payload field according to the generation sequence of the record data representing the payload information, so as to obtain the actual data packet.
In a possible implementation manner of the disclosure, the debugging system further includes a distribution module and a storage module, where the distribution module is configured to: receiving the debugging data packet output by the arbitration module and distributing the debugging data packet to the storage module; the storage module is configured to: and sending the debugging data packet to the verification module.
In one possible implementation manner of the present disclosure, when the first number of debug data packets included in a piece of data sent by the distribution module is different from the second number of debug data packets included in a piece of data received by the storage module, the distribution module distributes the debug data packets to the storage module, and is specifically configured to: and the distribution module is used for distributing the adjusted data to the storage module after the number of the debugging data packets included in the data to be sent is adjusted from the first number to the second number.
In a possible implementation manner of the present disclosure, in a case that the number of debug data packets included in a piece of data to be sent by the distribution module is adjusted from the first number to the second number, the distribution module is specifically configured to:
under the condition that the first number X is smaller than the second number Y, combining N data received continuously into one data, wherein the product of N and X is equal to Y, and X, N, Y is a positive integer;
the distribution module adjusts the number of the debug data packets included in the data to be sent from the first number to the second number.
In one possible implementation of the present disclosure, the verification module includes an excitation module and an analog module;
the excitation module is configured to: loading the preset excitation to the operation memory of the single core, writing the starting address of the instruction stream of the single core to be tracked and the identification of the single core into the ETM after the single core is reset, and sending the preset excitation and the starting address of the instruction stream of the single core to be tracked to the simulation module after the single core is reset;
the verification module is configured to, in a case of simulating a simulation data packet generated by each single core after the preset stimulus is executed,: a register pointer is activated and, if the register pointer points to a start address of the instruction stream to be traced, the instruction stream of the corresponding address is converted into an analog data packet.
In one possible implementation of the disclosure, the verification module further includes a comparison module, and the data structures of the analog data packet and the debug data packet each include an identification field and a payload field; the verification module is configured to, in a case where the analog data packet is compared with the debug data packet,: judging whether a corresponding target simulation data packet exists in the simulation data packet or not according to each debugging data packet sent upstream, wherein the identification information in the identification domain of the target simulation data packet is the same as that in the identification domain of the debugging data packet, and the payload information in the payload domains of the target simulation data packet and the debugging data packet is the same;
and under the condition that all the debugging data packets have corresponding target simulation data packets, the tracking verification result is pass, otherwise, the tracking verification result is fail.
In a possible implementation of the present disclosure, the comparing module is further configured to: storing the analog data packets with the same identification information into the same queue corresponding to the same identification information; correspondingly, the comparison module is specifically configured to, in the case of judging whether a corresponding target analog data packet exists in the analog data packets: for each debug data packet sent upstream, firstly judging whether the analog data packet exists in a target queue corresponding to the identification information of the debug data packet, if so, taking out a first analog data packet in the target queue, judging whether the first analog data packet is the target analog data packet, and if the target queue is empty or the first analog data packet is not the target analog data packet, outputting the first analog data packet as fail.
In one possible implementation of the present disclosure, the operating frequencies of the individual single cores are the same or partially the same or completely different.
According to another aspect of the disclosure, there is further provided an instruction stream trace verification method applied to a debug system, where the debug system includes an arbitration module, a verification module, and a plurality of embedded trace macro units ETM for one-to-one connection with each single core in a chip to be debugged; the method comprises the following steps: the ETM captures recorded data generated by a single core connected with the ETM after the single core is actually operated to preset excitation, codes the recorded data into an actual data packet and sends the actual data packet to the arbitration module; the arbitration module integrates and outputs the actual data packets of each single core into one path of debugging data packet according to the working frequency of each single core; the verification module simulates a simulation data packet generated after each single core runs the preset excitation; and comparing the simulation data packet with the debugging data packet, and outputting a tracking verification result according to the comparison result.
In a possible implementation manner of the present disclosure, according to the working frequency of each single core, the arbitration module integrates and outputs the actual data packet of each single core into a debug data packet, including: combining the actual data packets sent by the ETM by adopting a weighted polling mode according to the weight ratio of each preset single-core weighted polling to obtain the debugging data packet; the weighted polling weight ratio of each single core is the ratio of the working frequencies of each single core.
In one possible implementation of the present disclosure, each ETM includes a comparison register, configured to set a start address of an instruction stream to be tracked in the preset stimulus, where the ETM captures record data generated after actually running the preset stimulus by a single core connected to the ETM, and includes: and under the condition that the running pointer of the single core connected with the self is determined to point to the starting address of the instruction stream to be tracked, starting to grab the recorded data generated by the single core connected with the self.
In one possible implementation of the present disclosure, the start addresses configured in the compare registers corresponding to different single cores are the same or partially the same or completely different.
In a possible implementation manner of the present disclosure, the actual data includes a header information header and a payload information payload, where the header information indicates an identifier of a corresponding single core, and the payload information indicates a single instruction stream in the preset excitation; the data structure of the actual data packet comprises an identification field and a payload field; the encoding the recorded data into an actual data packet includes: and filling the record data representing the header information into the identification field, and filling the record data representing the payload information into the payload field according to the generation sequence of the record data representing the payload information, so as to obtain the actual data packet.
In a possible implementation manner of the disclosure, the debug system further includes a distribution module and a storage module, and the method further includes: the distribution module receives the debugging data packet output by the arbitration module and distributes the debugging data packet to the storage module; and the storage module sends the debugging data packet to the verification module.
In a possible implementation manner of the present disclosure, when a first number of debug data packets included in a piece of data sent by the distribution module is different from a second number of debug data packets included in a piece of data received by the storage module, the distributing the debug data packets to the storage module includes: and after the number of the debugging data packets included in the data to be sent is adjusted from the first number to the second number, distributing the adjusted data to the storage module.
In a possible implementation manner of the present disclosure, the adjusting the number of the debug data packets included in the piece of data to be sent from the first number to the second number includes:
under the condition that the first number X is smaller than the second number Y, combining N data received continuously into one data, wherein the product of N and X is equal to Y, and X, N, Y is a positive integer;
And under the condition that the first number X is larger than the second number Y, discarding Q invalid debugging data packets in each received data, wherein the difference between X and Q is equal to Y, and X, Q, Y is a positive integer.
In one possible implementation of the present disclosure, the verification module includes an excitation module and an analog module; the method further comprises the steps of: the excitation module loads the preset excitation to the operation memory of the single core, writes the starting address of the instruction stream of the single core, which needs to be tracked, and the identification of the single core into the ETM after the single core is reset, and sends the preset excitation and the starting address of the instruction stream of the single core, which needs to be tracked, to the simulation module after the single core is reset;
correspondingly, the verification module simulates a simulation data packet generated by each single core after the preset excitation is operated, and the simulation data packet comprises the following components: the emulation module initiates a register pointer and converts an instruction stream of a corresponding address into an emulation packet if the register pointer points to a start address of the instruction stream to be traced.
In one possible implementation of the disclosure, the verification module further includes a comparison module, and the data structures of the analog data packet and the debug data packet each include an identification field and a payload field; the comparing the analog data packet with the debug data packet includes: for each debug data packet sent upstream, the comparison module judges whether a corresponding target simulation data packet exists in the simulation data packet, wherein the identification information in the identification domain of the target simulation data packet is the same as that in the payload domain of the debug data packet, and the payload information in the payload domain of the target simulation data packet is the same as that in the payload domain of the debug data packet;
And under the condition that all the debugging data packets have corresponding target simulation data packets, the tracking verification result is pass, otherwise, the tracking verification result is fail.
In a possible implementation manner of the present disclosure, the method further includes: the comparison module stores the analog data packets with the same identification information into the same queue corresponding to the same identification information; correspondingly, the judging whether the corresponding target analog data packet exists in the analog data packet includes: for each debug data packet sent upstream, the comparison module firstly judges whether the analog data packet exists in a target queue corresponding to the identification information of the debug data packet, if so, takes out a first analog data packet in the target queue, judges whether the first analog data packet is the target analog data packet, and if the target queue is empty or the first analog data packet is not the target analog data packet, outputs as fail.
In one possible implementation of the present disclosure, the operating frequencies of the individual single cores are the same or partially the same or completely different.
Drawings
FIG. 1 is a schematic diagram of a debug system according to an embodiment of the present disclosure;
fig. 2 is a flow chart of an instruction stream trace verification method of an embodiment of the present disclosure.
Detailed Description
Before describing embodiments of the present disclosure, it should be noted that:
some embodiments of the disclosure are described as process flows, in which the various operational steps of the flows may be numbered sequentially, but may be performed in parallel, concurrently, or simultaneously.
The terms "first," "second," and the like may be used in embodiments of the present disclosure to describe various features, but these features should not be limited by these terms. These terms are only used to distinguish one feature from another.
The term "and/or," "and/or" may be used in embodiments of the present disclosure to include any and all combinations of one or more of the associated features listed.
It will be understood that when two elements are described in a connected or communicating relationship, unless a direct connection or direct communication between the two elements is explicitly stated, connection or communication between the two elements may be understood as direct connection or communication, as well as indirect connection or communication via intermediate elements.
In order to make the technical solutions and advantages of the embodiments of the present disclosure more apparent, the following detailed description of exemplary embodiments of the present disclosure is provided in conjunction with the accompanying drawings, and it is apparent that the described embodiments are only some embodiments of the present disclosure, not all embodiments of which are exhaustive. It should be noted that, without conflict, the embodiments of the present disclosure and features of the embodiments may be combined with each other.
While supporting debugging of the multi-core chip, the existing debugging system CoreSight considers the problem of debugging time sequence, and the premise of implementing debugging is that the model specifications of each single core in the multi-core chip are required to be the same so as to ensure that the output frequencies of instruction streams of the single cores are consistent, and then the instruction streams output by the single cores are integrated into one path of debugging data packet for subsequent debugging. For example, for a multi-core CPU chip system, trace debugging can be performed on the running instruction streams of each CPU in the multi-core CPU chip system at one time by using CoreSight on the premise that the model specifications of each CPU are consistent, and if the model specifications of each CPU are inconsistent, the packet loss of the instruction streams of part of the CPUs is easily caused by the difference of the output frequencies of the CPU instruction streams of different models.
In practice, however, the model number from core to core is not necessarily exactly the same for a multi-core chip. Then for heterogeneous multi-core chips, the existing debug system CoreSight cannot meet the debug requirement, i.e. CoreSight cannot play a debug role, so that the use range of the debug system is limited.
To extend the scope of use of CoreSight, as shown in fig. 1, one embodiment of the present disclosure provides a debug system that includes an arbitration module atb_arbiter, a validation module, an embedded trace macro ETM (Eembeded Trace Macrocell), and other modules that may be present, such as a distribution module (replier) and a storage module (ETB and/or TPIU), i.e., the debug system provided by the present disclosure, on existing CoreSight systems, an arbitration module and a validation module are mainly added.
The ETM is used for being connected with each single core in the chip to be debugged in a one-to-one correspondence mode. The chip to be debugged can be a single-core chip or a multi-core chip. The operating frequencies of the single cores in the multi-core chip may be the same, may be partially the same, or may be completely different.
Of course, the multi-core chip mentioned in the present disclosure may be a multi-core CPU (Central Processing Unit ) chip, or may be a multi-core GPU (Graphic Processing Unit, graphics processor) chip. Embodiments of the present disclosure will be described below taking a multi-core chip as an example of a multi-core CPU chip, and it will be understood that the implementation process may refer to a multi-core CPU chip when the multi-core chip is another type of chip.
It is now assumed that the multi-core CPU chip comprises CPU 0-CPU 3, each CPU may be of a different ARM type, for example, may be an ARM a series, an M system and an R series, and each CPU may be of a different combination, for example, CPU0 and CPU1 are of an ARM a series, CPU2 is of an M series, and CPU3 is of an R series. The operating frequencies of the CPUs belonging to different series are different.
Before the instruction stream tracking verification is required to be performed on the multi-core CPU chip, each single core in the multi-core CPU chip is required to be connected with the corresponding ETM one by one, or the corresponding ETM is directly built in the CPU.
After the above setting is completed, each ETM in the debug system is configured to: and capturing recorded data generated by a single core connected with the single core after the preset excitation is actually operated, encoding the recorded data into an actual data packet, and sending the actual data packet to the arbitration module.
The arbitration module is configured to: and integrating and outputting the actual data packets of each single core into one path of debugging data packet according to the working frequency of each single core.
The distribution module is configured to: receiving the debugging data packet output by the arbitration module and distributing the debugging data packet to the storage module; the storage module is configured to: and sending the debugging data packet to the verification module.
The verification module is configured to: simulating a simulation data packet generated by each single core after the preset excitation is operated; and comparing the simulation data packet with the debugging data packet, and outputting a tracking verification result according to the comparison result.
Therefore, when the debug system provided by the embodiment of the disclosure performs instruction stream trace verification on the multi-core chip, the actual data packets output by each single core can be integrated into one path of debug data packet based on the working frequency of each single core, and then the debug data packet and the analog data packet are compared, so that the trace verification result is output according to the comparison result. Because the actual data packets output by the single cores are integrated into one path of debugging data packet according to the working frequency of each single core, even if the working frequencies of the single cores are different, the situation that the data packet is lost due to the partial record of the high-frequency single core can be avoided, so that the accuracy of a debugging result is ensured, correspondingly, the debugging system can be suitable for heterogeneous multi-core chips with different types of the single cores, and the application range of the debugging system is increased.
The process of performing instruction stream trace verification on the multi-core chip with respect to the debug system will be described in detail.
Optionally, the verification modules mentioned in the embodiments of the present disclosure may include a stimulus module Testcase, an analog module ref-mode, and a comparison module scoreboard.
The excitation module Testcase can generate preset excitation according to configuration of debugging personnel, and the preset excitation is loaded into the fortune memory bootram of each single-core CPU.
Specifically, after receiving a C-language code (C-code) written by a debugger and operated by a CPU, the excitation module compiles the C-code into a boot code in a hex format by using a gcc compiler or an armcc compiler, namely, preset excitation, and then loads a hex file into a bootram of the CPU in a back door mode. The method comprises the steps that a preset excitation can be ensured to be copied into a memory of a CPU in a zero delay zero time sequence mode through a back gate, and then the CPU can acquire effective excitation data when being started.
In general, each single core shares the same preset stimulus, and different single cores can operate instructions corresponding to different address fields in the same preset stimulus according to preset configuration.
Furthermore, it is worth noting that in the embodiment of the present disclosure, a compare register (compare register) is included in each ETM, and the compare register is used to receive the software configuration of the debugger before the start of the debug, and further set the start address of the instruction stream to be traced in the preset stimulus. Of course, the debugger will also write a unique identification, such as an ATID, pre-configured for each single Core (CPU) to the ETM, typically before debugging begins.
The compare registers in ETMs corresponding to different single Cores (CPUs) within which the start addresses of the configured instruction streams that need to be traced may be the same; or the starting addresses of the instruction streams which need to be tracked of the individual CPUs are the same; or may be completely different, i.e., the starting addresses of the instruction streams that need to be traced are different for each CPU.
For each ETM, after setting the start address of the instruction stream to be traced, when determining that the CPU pointer connected with the ETM runs to the start address of the instruction stream to be traced in the preset stimulus set by the compare register, the ETM starts working, specifically starts capturing record data generated by the CPU connected with the ETM after the CPU runs the instruction stream to be traced.
After the ETM grabs the recorded data, it starts to encode the grabbed recorded data into an actual data packet.
Optionally, each piece of record data captured by the CPU may be header information header or payload information payload, that is, the actual data includes the header information header and the payload information payload. Wherein the header part is used for indicating the identification of a single Core (CPU) generating the record data, and the payload part is used for indicating the instruction stream operated by the single Core (CPU) and the corresponding timestamp, corresponding to the ATID and the previous, wherein the instruction stream is a single instruction stream in preset excitation.
The data structure of the actual data packet includes an identification field (ATID field) and a payload field (payload field). Based on this, the ETM encodes the recording data into actual data packets, specifically configured to: and filling record data representing header information into an ATID field, and filling M record data representing payload information into the payload field according to the generation sequence (which can be determined by a time stamp) of the record data representing payload information, so as to obtain the actual data packet. Wherein, the occupied bit width of the record data used for representing the header information header is less than the first preset bit width of the ATID domain in the data structure of the actual data packet, and the sum of the occupied bit widths of the record data used for representing the payload information is less than the second preset bit width of the payload domain in the data structure of the actual data packet.
The bit width of the data structure of the actual data packet corresponding to the different ETMs needs to be determined in advance according to the bit width of the recorded data that can be captured by the corresponding ETMs.
It is assumed that the recording data each representing payload information has a space occupation of 8 bits, and the recording data each representing header information has a space occupation of 8 bits, and based on this, one actual data is configured as 40 bits, 8 bits for the atid field, and 32 bits for the payload field, as shown in the following table.
Then 4 record data representing the payload information need to be padded to the payload field at a time for the above example.
Let it be assumed that the recording data captured by the ETM are in turn: 7D, E, 03, 1F, AA, 91, 00, 21, F7 … …, wherein the first record data generally represents header information, and is filled in the ATID field of the actual data packet; and for the subsequently generated record data representing the payload information, according to the sequence of the generation, the first 4 record data representing the payload information are sequentially filled into 0-7 bit, 8-15 bit, 16-23 bit and 24-31 bit of the payload domain according to the principle of filling the lower bit of the payload domain and then filling the upper bit of the payload domain. The first actual data packet after encoding is: the second actual packet is 40' h7daa1f03e 0: 40' H7DE7210091. Where "40'" indicates that a packet format of an actual data packet is 40 bits, 7d indicates the identity of the CPU generating the data, and the rest is the payload information.
After encoding the actual data packet, the ETM sends the actual data packet to the arbitration module.
In the embodiment of the disclosure, the arbitration module integrates and outputs the actual data packets of each single core into one path of debug data packet according to the working frequency of each single core, and is specifically configured to: according to the weight ratio of each preset single-core weighted poll, combining the actual data packets sent by different ETMs in a weighted poll mode to further obtain a path of debugging data packet stream, wherein the debugging data packet stream comprises the actual data packets sent by each ETM. Wherein the weight ratio of the weighted polling of each single core is the ratio of the working frequencies of each single core.
Alternatively, it is now assumed that there are CPU1 and CPU2, the CPU1 operating frequency is 600Hz, and connected thereto is ETM1; the CPU2 has an operating frequency of 300Hz, to which is connected ETM2. Because the working frequency ratio of the CPU1 to the CPU2 is 2:1, under the same clock period, the ETM1 can grasp and output the 2-beat real data packet corresponding to the CPU1, and the ETM2 can grasp and output the 1-beat real data packet corresponding to the CPU 2.
According to the debug system in the prior art, the weights used for receiving the actual data packets sent by the respective ETMs are consistent and can be considered as 1:1. thus, in the case shown by the above example, the debug system in the prior art immediately transfers the weight to the ETM2 to start receiving the 1-beat real data packet sent by the ETM2 (which would result in the 1-beat real data packet corresponding to the ETM1 being lost) after receiving the 1-beat real data packet sent by the ETM1, and then transfers the weight to the 1-beat real data packet … … in the next clock cycle to start receiving the 1-beat real data packet sent by the ETM1 so reciprocally, which would result in a large amount of lost packets, so that the debug system in the prior art can only debug the multicore chips with the same model.
In the embodiment of the present disclosure, since the operating frequency ratio of CPU1 to CPU2 is 2:1, the weighted polling weight ratio of CPU1 to CPU2 is configured to be 2:1. Under the same clock period, when the arbitration module combines the actual data packets sent by the ETM1 and the ETM2 according to the weight ratio 2:1 of the weighted polling of the CPU1 and the CPU2, the actual data packets sent by the ETM1 are acquired twice in a time division multiplexing mode in the time period, then the acquisition weight is handed over to the ETM2, and the actual data packets sent by the ETM2 are acquired once. And subsequently entering the next clock period, handing over the acquisition weight to the ETM1 again, and after the arbitration module acquires the actual data packet sent by the ETM1 twice, handing over the acquisition weight to the ETM2 … …, thereby orderly comprising: since the actual data packet transmitted by the ETM1 is taken by 2, the actual data packet transmitted by the ETM2 is taken by 1, the actual data packet transmitted by the ETM1 is taken by 2, and the actual data packet … … transmitted by the ETM2 is taken by 1, the problem of packet loss can be avoided by configuring the weighting ratio of weighted polling of each single core to the ratio of the working frequencies of each single core, and further, the heterogeneous multi-core chip comprising a plurality of single cores with different models can be debugged by the same debugging system.
The aforementioned debug system may further comprise a distribution module and a storage module, the distribution module configured to: receiving the debugging data packet output by the arbitration module and distributing the debugging data packet to the storage module; the storage module is configured to: and sending the debugging data packet to the verification module.
In practical situations, when the distribution module distributes data to the storage module, the number of debug data packets (hereinafter, simply referred to as the first number) included in a piece of data sent out is not necessarily the same as the number of debug data packets (hereinafter, simply referred to as the second number) included in a piece of data received by the storage module.
The distribution module can directly distribute the debug data packet included in one data to the storage module for storage under the condition that the first number is the same as the second number.
For the case that the first number X is different from the second number Y, the distribution module may further adjust the number of debug data packets included in the data to be sent, specifically: the distribution module adjusts the number of the debug data packets included in the data to be sent from the first number X to the second number Y.
After finishing the bit width adjustment, the distribution module distributes the adjusted data to the storage module.
Optionally, when the distribution module adjusts the number of debug data packets included in one piece of data, the distribution module is mainly divided into two cases of number expansion and number compression.
The number expansion mainly realizes the function of expanding the data bit width, for example, the data bit width is expanded from 32bit width to 64bit width, and the transmission frequency is reduced to 1/2 of the original transmission frequency; the data compression mainly realizes the function of reducing the data bit width, for example, the data bit width is reduced from 64bit width to 32bit width, and the transmission frequency is increased by 2 times.
Specifically, when the number of debug data packets included in a piece of data to be sent is adjusted from the first number X to the second number Y, the distribution module is specifically configured to: under the condition that the first number X is smaller than the second number Y, the distribution module combines N data received continuously into one data, the product of N and X is equal to Y, and X, N, Y is a positive integer.
In order to achieve the above effect, a buffer is built in the distribution module. Now, assuming that the occupied space of one debug data packet is 32 bits, one data sent by the distribution module comprises 1 debug data packet, and one data received by the storage module comprises 2 debug data packets, so that the distribution module is currently required to combine the continuously received 2 beats of data, then combine and output the continuously received 2 beats of data to the storage module in one clock period, and finally the occupied space of one data output by the distribution module is 64 bits, and the data comprises 2 debug data packets.
The distribution module is specifically further configured to, in a case where the number of debug data packets included in the piece of data to be sent is adjusted from the first number X to the second number Y: and under the condition that the first number X is larger than the second number Y, discarding Q invalid debugging data packets in each received data, wherein the difference between X and Q is equal to Y, and X, Q, Y is a positive integer.
The number compression generally corresponds to a case where a single core that does not need to be debugged exists in a multi-core chip, and thus, a debug packet corresponding to the single core that does not need to be debugged is an invalid debug packet. In order to achieve the above effect, it is assumed that the multi-core chip includes 2 single cores, respectively CPU0 and CPU1, and each debug packet corresponding to each single core occupies 32 bits. The data output by the distribution module comprises 2 debugging data packets, namely a debugging data packet 0 corresponding to the CPU0 and a debugging data packet 1 corresponding to the CPU 1. Now, assuming that the CPU1 does not need to participate in the debugging, in the debugging process, the second number Y of debug data packets included in the data received by the storage module may be set to 1, so that after each data received by the distribution module, the invalid debug data packet corresponding to the CPU1 (i.e. debug data packet 1) is discarded, and further, the occupation width of one data finally output by the distribution module is 32 bits, including 1 debug data packet. The identification of invalid debug packets may be determined by the ATID field in the debug packet.
The above-mentioned can play the effect of saving the bandwidth in the data transmission process by discarding the invalid debug data packet corresponding to the main core which does not need to participate in the debugging.
In addition, it is worth pointing out that under the condition that invalid debugging data packets are discarded, when the verification module simulates the behavior of the main core to generate simulation data, the simulation data packets corresponding to single cores which do not need to participate in debugging are correspondingly discarded, so that the number of the debugging data packets and the simulation data packets which need to be compared later is reduced, and the effects of saving verification time and improving verification efficiency can be achieved. After the single core which does not need to participate in debugging is determined, the analog data packet corresponding to the single core which does not need to participate in debugging can be determined through the ATID field in the analog data packet.
Optionally, the storage module may include ETB (Eembeded Trace Buffer) and/or TPIU (Trace Port Interface Unit).
ETB is a block of sram memory, and the default size is 32KB, and can be adjusted according to the requirement. The ETB has two interfaces, one is an ATB interface and is used for writing data; one is an APB interface for debug bus access to memory contents. When the received data is greater than the storage capacity, the previously written data is overwritten.
The TPIU is a component connected to the outside and is responsible for converting data of the ATB to GPIO. The data from the ATB is 32bit or 64bit wide, and becomes 16bit wide data after being converted to GPIO, so the TPIU is also responsible for rate conversion and data rearrangement.
Under the condition that the storage module simultaneously comprises the ETB and the TPIU, the distribution module can distribute the debugging data packet to buffers in the ETB for temporary storage, and can also distribute the debugging data packet to the TPIU for real-time observation. Alternatively, one-way gating of ETB and TPIU may be implemented through configuration registers.
The verification module includes the stimulus module Testcase, the simulation module ref-mode, and the comparison module scoreboard.
An excitation module configured to: the preset stimulus is loaded to the operation memory of the single core, and the starting address of the instruction stream of the single core, which needs to be tracked, and the identification of the single core, such as ATID, are written into the ETM after the single core is reset. In addition, after the single core is reset, the excitation module sends the preset excitation, the identification of the single core and the starting address of the instruction stream of the single core to be tracked to the simulation module through the analysis port.
The verification module is configured to, in a case of simulating a simulation data packet generated after each single core runs a preset stimulus, simulate ref-mode by the verification module: and receiving preset excitation sent by an excitation module Testcase, identification of a single core and a start address of an instruction stream to be tracked, and simulating the behavior of the single core to generate corresponding data. The process specifically can be as follows: and starting the register pointer, and converting the instruction stream corresponding to the starting address in the preset excitation into an analog data packet under the condition that the register pointer points to the starting address of the instruction stream to be tracked. The analog data packet may be considered herein as the full actual data packet that a single core can produce after running the corresponding instruction stream.
The process of the simulation module simulating the single-core operation instruction stream to convert the instruction stream of the corresponding address into the simulated data packet is similar to the process of capturing the recorded data and encoding the recorded data into the actual data packet by the ETM, and will not be described herein.
Of course, the analog data packet also includes an identification field and a payload field in its data structure.
For the comparison module scoreboard, data in two directions are received, which are respectively: the analog module ref-mode generates analog packets that are sent through an analysis port, and debug packets that are read from the memory module (e.g., read from the APB interface of the ETB by way of a front gate) or sent by the memory module (e.g., sent by the TPIU).
The verification module, in the case of comparing the analog data packet with the debug data packet, is configured to: for each debug data packet sent upstream or obtained from upstream, judging whether corresponding target analog data packets exist in the full amount of analog data packets, and if all the debug data packets exist corresponding target analog data packets, tracking and verifying the result as pass, otherwise, as fail.
The target analog data packet refers to an analog data packet which has the same identification information in the identification domain of the corresponding debug data packet and has the same payload information in the payload domain of the corresponding debug data packet. Upstream of this may be the ETB and/or TPIU in the storage module described above.
Of course, in some embodiments, the comparison module may also create a plurality of queues in advance, and establish a correspondence between the queues and the identification information. Based on this, the comparison module may be further configured to: and storing the analog data packets with the same identification information into the same queue corresponding to the same identification information.
Correspondingly, the comparison module is specifically configured to, in the case of judging whether the corresponding target analog data packet exists in the analog data packets: for each debug data packet sent upstream or obtained from upstream, it is first determined whether there is an analog data packet in the target queue corresponding to the identification information of the debug data packet, that is, whether there is no null.
And under the condition that the comparison module takes out the first simulation data packet in the target queue, judges whether the first simulation data packet is the target simulation data packet corresponding to the current debugging data packet to be compared, and judges the pass after all the debugging data packets are compared and the queue is empty. If the target queue is empty or the first analog packet is not the target analog packet, the output is fail.
That is, in the present disclosure, for the case where the trace verification result is fail, the output efficiency of the trace verification result may be improved by introducing a queue.
In addition, another embodiment of the disclosure further provides an instruction stream tracking verification method implemented based on a debug system, wherein the debug system comprises an arbitration module, a verification module and a plurality of embedded tracking macro units ETM which are used for being connected with each single core in a chip to be debugged in a one-to-one correspondence manner.
As shown in fig. 2, the method may include:
s110: the ETM captures recorded data generated by a single core connected with the ETM after the single core is actually operated to preset excitation, codes the recorded data into an actual data packet and sends the actual data packet to the arbitration module;
s120: the arbitration module integrates and outputs the actual data packets of each single core into one path of debugging data packet according to the working frequency of each single core;
s130: the verification module simulates a simulation data packet generated after each single core runs the preset excitation; and comparing the simulation data packet with the debugging data packet, and outputting a tracking verification result according to the comparison result.
In a possible implementation manner of the present disclosure, according to the working frequency of each single core, the arbitration module integrates and outputs the actual data packet of each single core into a debug data packet, including: combining the actual data packets sent by the ETM by adopting a weighted polling mode according to the weight ratio of each preset single-core weighted polling to obtain the debugging data packet; the weighted polling weight ratio of each single core is the ratio of the working frequencies of each single core.
In one possible implementation of the present disclosure, each ETM includes a comparison register, configured to set a start address of an instruction stream to be tracked in the preset stimulus, where the ETM captures record data generated after actually running the preset stimulus by a single core connected to the ETM, and includes: and under the condition that the running pointer of the single core connected with the self is determined to point to the starting address of the instruction stream to be tracked, starting to grab the recorded data generated by the single core connected with the self.
In one possible implementation of the present disclosure, the start addresses configured in the compare registers corresponding to different single cores are the same or partially the same or completely different.
In a possible implementation manner of the present disclosure, the actual data includes a header information header and a payload information payload, where the header information indicates an identifier of a corresponding single core, and the payload information indicates a single instruction stream in the preset excitation; the data structure of the actual data packet comprises an identification field and a payload field; the encoding the recorded data into an actual data packet includes: and filling the record data representing the header information into the identification field, and filling the record data representing the payload information into the payload field according to the generation sequence of the record data representing the payload information, so as to obtain the actual data packet.
In a possible implementation manner of the disclosure, the debug system further includes a distribution module and a storage module, and the method further includes: the distribution module receives the debugging data packet output by the arbitration module and distributes the debugging data packet to the storage module; and the storage module sends the debugging data packet to the verification module.
In a possible implementation manner of the present disclosure, when a first number of debug data packets included in a piece of data sent by the distribution module is different from a second number of debug data packets included in a piece of data received by the storage module, the distributing the debug data packets to the storage module includes: and after the number of the debugging data packets included in the data to be sent is adjusted from the first number to the second number, distributing the adjusted data to the storage module.
In a possible implementation manner of the present disclosure, the adjusting the number of the debug data packets included in the piece of data to be sent from the first number to the second number includes:
under the condition that the first number X is smaller than the second number Y, combining N data received continuously into one data, wherein the product of N and X is equal to Y, and X, N, Y is a positive integer;
And under the condition that the first number X is larger than the second number Y, discarding Q invalid debugging data packets in each received data, wherein the difference between X and Q is equal to Y, and X, Q, Y is a positive integer.
In one possible implementation of the present disclosure, the verification module includes an excitation module and an analog module; the method further comprises the steps of: the excitation module loads the preset excitation to the operation memory of the single core, writes the starting address of the instruction stream of the single core, which needs to be tracked, and the identification of the single core into the ETM after the single core is reset, and sends the preset excitation and the starting address of the instruction stream of the single core, which needs to be tracked, to the simulation module after the single core is reset;
correspondingly, the verification module simulates a simulation data packet generated by each single core after the preset excitation is operated, and the simulation data packet comprises the following components: the emulation module initiates a register pointer and converts an instruction stream of a corresponding address into an emulation packet if the register pointer points to a start address of the instruction stream to be traced.
In one possible implementation of the disclosure, the verification module further includes a comparison module, and the data structures of the analog data packet and the debug data packet each include an identification field and a payload field; the comparing the analog data packet with the debug data packet includes: for each debug data packet sent upstream, the comparison module judges whether a corresponding target simulation data packet exists in the simulation data packet, wherein the identification information in the identification domain of the target simulation data packet is the same as that in the payload domain of the debug data packet, and the payload information in the payload domain of the target simulation data packet is the same as that in the payload domain of the debug data packet;
And under the condition that all the debugging data packets have corresponding target simulation data packets, the tracking verification result is pass, otherwise, the tracking verification result is fail.
In a possible implementation manner of the present disclosure, the method further includes: the comparison module stores the analog data packets with the same identification information into the same queue corresponding to the same identification information; correspondingly, the judging whether the corresponding target analog data packet exists in the analog data packet includes: for each debug data packet sent upstream, the comparison module firstly judges whether the analog data packet exists in a target queue corresponding to the identification information of the debug data packet, if so, takes out a first analog data packet in the target queue, judges whether the first analog data packet is the target analog data packet, and if the target queue is empty or the first analog data packet is not the target analog data packet, outputs as fail.
In one possible implementation of the present disclosure, the operating frequencies of the individual single cores are the same or partially the same or completely different.
For a specific implementation process of the instruction stream tracking verification method provided in the present disclosure, please refer to the corresponding portion of the foregoing system embodiment, and details are not repeated herein.
In summary, the embodiments of the present disclosure provide an instruction stream trace verification method and a debug system, where when the debug system performs instruction stream trace verification on a multi-core chip, an actual data packet output by each single core may be integrated into a path of debug data packet based on a working frequency of each single core, and then the debug data packet and an analog data packet are compared, and further a trace verification result is output according to a comparison result. Because the actual data packets output by the single cores are integrated into one path of debugging data packet according to the working frequency of each single core, even if the working frequencies of the single cores are different, the situation that the data packets are lost due to the partial record of the high-frequency single core can be avoided, so that the accuracy of the debugging result is ensured, the debugging system can be suitable for heterogeneous multi-core chips with different types of the single cores, and the application range of the debugging system is increased.
While the preferred embodiments of the present disclosure have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. It is therefore intended that the following claims be interpreted as including the preferred embodiments and all such alterations and modifications as fall within the scope of the disclosure.
It will be apparent to those skilled in the art that various modifications and variations can be made to the present disclosure without departing from the spirit or scope of the disclosure. Thus, the present disclosure is intended to include such modifications and alterations insofar as they come within the scope of the appended claims or the equivalents thereof.
Finally, it should be noted that: the foregoing embodiments are merely for illustrating the technical solution of the present disclosure and not for limiting the scope thereof, and although the present disclosure has been described in detail with reference to the foregoing embodiments, it will be understood by those skilled in the art that various changes, modifications or equivalents may be made to the specific embodiments of the invention after reading the present disclosure, and these changes, modifications or equivalents are within the scope of the claims appended hereto.
Claims (15)
1. The debugging system is characterized by comprising an arbitration module, a verification module and a plurality of embedded tracking macro units (ETM) which are used for being connected with each single core in a chip to be debugged in a one-to-one correspondence manner;
the ETM is configured to: capturing recorded data generated after the single core connected with the single core actually runs preset excitation, encoding the recorded data into an actual data packet and sending the actual data packet to the arbitration module;
The arbitration module is configured to: integrating and outputting the actual data packets of each single core into a path of debugging data packet according to the working frequency of each single core;
the verification module is configured to: simulating a simulation data packet generated by each single core after the preset excitation is operated; and comparing the simulation data packet with the debugging data packet, and outputting a tracking verification result according to the comparison result.
2. The debug system according to claim 1, wherein the arbitration module is specifically configured to, in a case where the actual data packets of each single core are integrated and output into one debug data packet according to the working frequency of each single core: combining the actual data packets sent by the embedded tracking macro units in a weighted polling mode according to the weight ratio of each preset single core to obtain the debugging data packet; the weighted polling weight ratio of each single core is the ratio of the working frequencies of each single core.
3. The debugging system according to claim 1, wherein each ETM comprises a comparison register for setting a start address of an instruction stream to be traced in the preset stimulus, and the ETM, in case of grabbing recorded data generated by a single core connected to itself after actually running the preset stimulus, is specifically configured to: and under the condition that the running pointer of the single core connected with the self is determined to point to the starting address of the instruction stream to be tracked, starting to grab the recorded data generated by the single core connected with the self.
4. A debug system as claimed in claim 3, wherein the start addresses configured in the compare registers corresponding to different single cores are the same or partially the same or completely different.
5. The debugging system of claim 1, wherein the actual data comprises a header information header and a payload information payload, the header information representing an identification of a corresponding single core, the payload information representing a single instruction stream in the preset stimulus; the data structure of the actual data packet comprises an identification field and a payload field;
the ETM encodes the recorded data into actual data packets, specifically configured to: and filling the record data representing the header information into the identification field, and filling the record data representing the payload information into the payload field according to the generation sequence of the record data representing the payload information, so as to obtain the actual data packet.
6. The debug system of claim 1, further comprising a distribution module and a storage module, the distribution module configured to: receiving the debugging data packet output by the arbitration module and distributing the debugging data packet to the storage module; the storage module is configured to: and sending the debugging data packet to the verification module.
7. The debugging system of claim 6, wherein the distribution module distributes the debug data packet to the storage module if a first number of the debug data packets included in the distribution module sending one piece of data is different from a second number of the debug data packets included in the storage module receiving one piece of data, specifically configured to: and the distribution module is used for distributing the adjusted data to the storage module after the number of the debugging data packets included in the data to be sent is adjusted from the first number to the second number.
8. The debug system of claim 7, wherein, in the case where the number of debug packets included in a piece of data to be sent by the distribution module is adjusted from the first number to the second number, the distribution module is specifically configured to:
under the condition that the first number X is smaller than the second number Y, combining N data received continuously into one data, wherein the product of N and X is equal to Y, and X, N, Y is a positive integer;
and under the condition that the first number X is larger than the second number Y, discarding Q invalid debugging data packets in each received data, wherein the difference between X and Q is equal to Y, and X, Q, Y is a positive integer.
9. The debugging system of claim 1, wherein the verification module comprises an incentive module and a simulation module;
the excitation module is configured to: loading the preset excitation to the operation memory of the single core, writing the starting address of the instruction stream of the single core to be tracked and the identification of the single core into the ETM after the single core is reset, and sending the preset excitation and the starting address of the instruction stream of the single core to be tracked to the simulation module after the single core is reset;
the verification module is configured to, in a case of simulating a simulation data packet generated by each single core after the preset stimulus is executed,: a register pointer is activated and, if the register pointer points to a start address of the instruction stream to be traced, the instruction stream of the corresponding address is converted into an analog data packet.
10. The debug system of claim 9, wherein the validation module further comprises a comparison module, the data structures of the analog data packet and the debug data packet each comprising an identification field and a payload field; the verification module is configured to, in a case where the analog data packet is compared with the debug data packet,: judging whether a corresponding target simulation data packet exists in the simulation data packet or not according to each debugging data packet sent upstream, wherein the identification information in the identification domain of the target simulation data packet is the same as that in the identification domain of the debugging data packet, and the payload information in the payload domains of the target simulation data packet and the debugging data packet is the same;
And under the condition that all the debugging data packets have corresponding target simulation data packets, the tracking verification result is pass, otherwise, the tracking verification result is fail.
11. The debugging system of claim 10, wherein the comparison module is further configured to: storing the analog data packets with the same identification information into the same queue corresponding to the same identification information; correspondingly, the comparison module is specifically configured to, in the case of judging whether a corresponding target analog data packet exists in the analog data packets: for each debug data packet sent upstream, firstly judging whether the analog data packet exists in a target queue corresponding to the identification information of the debug data packet, if so, taking out a first analog data packet in the target queue, judging whether the first analog data packet is the target analog data packet, and if the target queue is empty or the first analog data packet is not the target analog data packet, outputting the first analog data packet as fail.
12. The debug system of any of claims 1-11, wherein the operating frequencies of the individual single cores are the same or partially the same or completely different.
13. The instruction stream tracking and verifying method is characterized by being applied to a debugging system, wherein the debugging system comprises an arbitration module, a verifying module and a plurality of embedded tracking macro units (ETM) which are used for being connected with each single core in a chip to be debugged in a one-to-one correspondence manner; the method comprises the following steps:
the ETM captures recorded data generated by a single core connected with the ETM after the single core is actually operated to preset excitation, codes the recorded data into an actual data packet and sends the actual data packet to the arbitration module;
the arbitration module integrates and outputs the actual data packets of each single core into one path of debugging data packet according to the working frequency of each single core;
the verification module simulates a simulation data packet generated after each single core runs the preset excitation; and comparing the simulation data packet with the debugging data packet, and outputting a tracking verification result according to the comparison result.
14. The method of claim 13, wherein the arbitration module integrates and outputs the actual data packets of each single core into a debug data packet according to the working frequency of each single core, and the method comprises:
combining the actual data packets sent by the embedded tracking macro units in a weighted polling mode according to the weight ratio of each preset single core to obtain the debugging data packet; the weighted polling weight ratio of each single core is the ratio of the working frequencies of each single core.
15. The method according to claim 13, wherein each of said ETMs comprises a comparison register for setting a start address of an instruction stream to be traced in said preset stimulus, said ETM grabbing recorded data generated after actually running the preset stimulus by a single core connected to itself, comprising:
and under the condition that the running pointer of the single core connected with the self is determined to point to the starting address of the instruction stream to be tracked, starting to grab the recorded data generated by the single core connected with the self.
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