CN116501287A - First-in first-out buffer device, control method, chip and electronic equipment - Google Patents

Abstract

The embodiment of the application provides a first-in first-out buffer device, a control method, a chip and electronic equipment, wherein the first-in first-out buffer device comprises: a storage module for storing data in the FIFO memory based on a write operation, and reading the data stored in the FIFO memory based on a read operation; the control module is used for generating an interrupt event based on the data quantity of the data stored in the FIFO memory and the interrupt condition; after the interrupt event is generated, a first operation triggered by the interrupt event is detected, and the interrupt event is generated again based on whether the first operation is detected. With the embodiment, the interrupt event can be generated again based on whether the operation triggered by the interrupt event is detected, so that the problem of data reading and writing caused by the fact that the interrupt event is ignored is reduced.

Description

First-in first-out buffer device, control method, chip and electronic equipment

Technical Field

The present disclosure relates to the field of electronic circuits, and in particular, to a first-in first-out buffer device, a control method, a chip, and an electronic device.

Background

A first-in first-out (First Input First Output, abbreviated FIFO) buffer for data stream buffering between the read device and the write device. The inventors have found that the FIFO buffer in the related art has a data read/write problem, for example, failure to read data in time causes overflow of the FIFO memory.

Disclosure of Invention

In view of the above, embodiments of the present application provide a first-in first-out buffer device, a control method, a chip, and an electronic device, so as to solve the above technical problems.

In a first aspect, an embodiment of the present application provides a first-in first-out buffer device, including: a storage module for storing data in the FIFO memory based on a write operation, and reading the data stored in the FIFO memory based on a read operation; the control module is used for generating an interrupt event based on the data quantity of the data stored in the FIFO memory and the interrupt condition, wherein the interrupt event is used for triggering the operation of the FIFO memory; after an interrupt event is generated, a first operation triggered by the interrupt event is detected, and the interrupt event is generated again based on whether the first operation is detected. By adopting the embodiment, the interrupt event can be generated again based on whether the operation triggered by the interrupt event is detected or not, and further the problem of data reading and writing caused by the fact that the interrupt event is ignored can be reduced.

Optionally, the control module includes: a first timer; the first timer is used for starting a first timing after the interrupt event is generated, wherein the duration of the first timing is a first preset duration; the control module is used for generating the interrupt event again under the condition that the first timing reaches a first preset duration and the first operation is not detected. By adopting the embodiment, when the operation triggered by the interrupt event (namely, the first operation) is not performed within the first preset time period after the interrupt event is generated, the interrupt event is generated again, and the operation triggered by the interrupt event can be triggered again.

Optionally, the control module is further configured to: if a first operation is detected in the first timing process, judging whether the data quantity of the data stored in the FIFO memory after the first operation meets the interrupt condition; when the interrupt condition is met, the first timer is cleared and the first timing is restarted.

Optionally, the control module includes a counter; a counter for starting to count a second operation triggering the interrupt event after the interrupt event is generated, wherein the number of the counts is a preset number; the control module is configured to, when the count reaches the preset number and the first operation is not detected, generate the interrupt event again. By adopting the embodiment, the operations triggering the interrupt event are counted after the interrupt event is generated, and the operations triggering the interrupt event can be triggered again under the condition that the operations triggering the interrupt event are not performed yet after the operations triggering the interrupt event are performed for a preset number.

Optionally, the control module is further configured to determine whether the data amount of the data stored in the FIFO memory after the first operation is performed meets the interrupt condition if the first operation is detected during the counting process; when the interrupt condition is satisfied, the counter is cleared and the count is restarted.

Optionally, the control module includes a second timer; the second timer is used for starting second timing when the first operation is detected, and the duration of the second timing is a second preset duration; the control module is used for suspending the generation of the interrupt event based on the data quantity stored in the FIFO memory and the interrupt condition under the condition that the second timing does not reach the second preset duration; continuously generating an interrupt event based on the data amount stored in the FIFO memory and the interrupt condition under the condition that the second timing reaches a second preset duration; when a new first operation is detected during the second timing, the second timer is cleared and the second timing is restarted. By adopting the embodiment, the first operation triggered by the interrupt event can be reduced, and the interrupt event can be triggered again when the first operation triggered by the interrupt event is performed.

Optionally, the first operation is a read operation. With this embodiment, the problem of triggering a read operation by an interrupt event to be ignored by the read device can be reduced to some extent.

Optionally, the first operation is a read operation and the second operation is a write operation. With this embodiment, the problem of triggering a read operation by an interrupt event to be ignored by the read device can be reduced to some extent.

Optionally, the above interrupt condition indicates: the interrupt event is generated when the data amount of the FIFO memory storage data is not less than the data amount threshold.

Optionally, the rate of the write operation is less than the rate of the read operation, and the first operation triggered by the interrupt event is the read operation.

In a second aspect, an embodiment of the present application further provides a method for controlling a fifo buffer device, including: storing data in the FIFO memory based on the write operation, and reading the data stored in the FIFO memory based on the read operation; generating an interrupt event based on the amount of data stored in the FIFO memory and the interrupt condition, wherein the interrupt event is used to trigger an operation on the FIFO memory; after the interrupt event is generated, a first operation triggered by the interrupt event is detected, and the interrupt event is generated again based on whether the first operation is detected. By adopting the embodiment, the interrupt event can be generated again based on whether the operation triggered by the interrupt event is detected or not, and further the problem of data reading and writing caused by the fact that the interrupt event is ignored can be reduced.

In a third aspect, an embodiment of the present application further provides a chip, including the fifo buffer device described above.

In a fourth aspect, an embodiment of the present application further provides an electronic device, including a device main body and a chip as described above disposed on the device main body.

According to the embodiment of the application, the interrupt event is generated based on the data quantity of the data stored in the FIFO memory and the interrupt condition, after the interrupt event is generated, the operation triggered by the interrupt event is detected, the interrupt event can be generated again based on whether the operation triggered by the interrupt event is detected, and further the problem that the interrupt event is ignored and data is read and written is solved.

These and other aspects of the present application will be more readily apparent from the following description of the embodiments.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the description of the embodiments will be briefly introduced below, it being obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

FIG. 1 is a schematic diagram of a system to which a FIFO buffer device according to an embodiment of the present application can be applied.

FIG. 2 shows a block diagram of a FIFO buffer device 100 according to an embodiment of the present application.

Fig. 3 shows a block diagram of a fifo buffer device 100 according to an embodiment of the application.

FIG. 4 is a block diagram showing another embodiment of the FIFO buffer device 100.

FIG. 5 is a block diagram showing another embodiment of the FIFO buffer device 100.

Fig. 6 shows a block diagram of a fifo buffer device 600 according to an embodiment of the application.

Fig. 7 shows a block diagram of a fifo buffer device 700 according to an embodiment of the application.

Fig. 8 is a flowchart illustrating a control method of the fifo buffer device according to an embodiment of the application.

FIG. 9 is a flow chart illustrating a method for controlling the FIFO buffer device shown in FIG. 3 according to an embodiment of the present application.

FIG. 10 is a flow chart illustrating a method for controlling the FIFO buffer device shown in FIG. 4 according to an embodiment of the present application.

FIG. 11 is a flowchart illustrating a method for controlling the FIFO buffer device shown in FIG. 5 according to an embodiment of the present application.

Detailed Description

Embodiments of the present application are described in detail below, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to like or similar elements or elements having like or similar functions throughout. The embodiments described below by referring to the drawings are exemplary only for the purpose of explaining the present application and are not to be construed as limiting the present application.

In order to better understand the solution of the present application, the following description will make clear and complete descriptions of the technical solution of the embodiment of the present application with reference to the accompanying drawings in the embodiment of the present application. It will be apparent that the described embodiments are only some, but not all, of the embodiments of the present application. All other embodiments, which can be made by those skilled in the art based on the embodiments herein without making any inventive effort, are intended to be within the scope of the present application.

In the embodiment of the application, at least one refers to one or more; plural means two or more. In the description of the present application, the words "first," "second," "third," and the like are used solely for the purpose of distinguishing between descriptions and not necessarily for the purpose of indicating or implying a relative importance or order.

Reference in the specification to "one embodiment" or "some embodiments" or the like means that a particular feature, structure, or characteristic described in connection with the embodiment is included in one or more embodiments of the application. Thus, the terms "comprising," "including," "having," and variations thereof herein mean "including but not limited to," unless expressly specified otherwise.

It should be noted that, in the embodiment of the present application, "and/or" describe the association relationship of the association object, which means that three relationships may exist, for example, a and/or B may be represented: a exists alone, A and B exist together, and B exists alone.

It should be noted that in the embodiments of the present application, "connected" is understood to mean electrically connected, and two electrical components may be connected directly or indirectly between two electrical components. For example, a may be directly connected to B, or indirectly connected to B via one or more other electrical components.

The fifo buffer device 100 provided in the present application may be applied to a system 200 as shown in fig. 1, where the system 200 includes a first device 21 and a second device 22. First-in first-out buffer device 100 may be used for buffering data streams between first device 21 and second device 22.

In some possible embodiments, at least part of the first device 21, the second device 22, and the first-in-first-out buffer device 100 may be components of the same apparatus. Illustratively, first-in first-out buffer device 100 is included in a data processing apparatus, and first and second devices 21, 22 may be circuit modules (e.g., integrated circuits) in the data processing apparatus, and first-in first-out buffer device 100 may be used for data transfer between the circuit modules in the data processing apparatus.

In some possible embodiments, the first device 21, the second device 22 and the fifo buffer device 100 may be integrated into an integrated circuit (also referred to as a chip).

In some possible embodiments, one of the first device 21 and the second device 22 may act as a read device and the other of the first device 21 and the second device 22 may act as a write device. The writing means writes data into the FIFO memory of the FIFO buffer 100 and the reading means reads data stored in the FIFO memory of the FIFO buffer 100. In some possible embodiments, the first device 21 may act as both a read device and a write device. The second device 22 may function as both a writing device and a reading device.

In some possible implementations, the write device is allowed to write data to the FIFO memory of the FIFO buffer device 100 at a first rate, and the read device is allowed to read data stored in the FIFO memory of the FIFO buffer device 100 at a second rate. The first rate may be based on a first clock frequency associated with the write device and the second rate may be based on a second clock frequency associated with the read device. The first rate and the second rate may be the same or different, and embodiments of the present application are not limited in this regard. For example, in some examples, the first rate is greater than the second rate, in other examples, the first rate is less than the second rate, and in still other examples, the first rate is equal to the second rate. When the first rate is different from the second rate, the fifo 100 can implement the clock domain crossing process, that is, the data of the writing device is written into the fifo 100 according to the first rate corresponding to the first clock frequency, and then the reading device reads the data in the fifo 100 according to the second rate corresponding to the second clock frequency.

In some possible embodiments, the write device is allowed to write data to the FIFO memory of the FIFO buffer device 100 at a first data bit width, and the read device is allowed to read data stored in the FIFO memory of the FIFO buffer device 100 at a second data bit width. When the first data bit width is different from the second data bit width, bandwidth synchronization can be achieved by the fifo buffer device 100. The data bit width outputted by the writing device is 4, the data writing port bit width of the fifo 100 is also set to 4, the data bit width inputted by the reading device is 8, and the data reading port bit width of the fifo 100 is also set to 8, i.e. the two data bit widths are spliced into one data bit width of 8, thereby realizing bandwidth synchronization.

In some possible embodiments, the fifo 100 triggers the read device and/or the write device to operate through an interrupt event, however, there is a case where the interrupt event is ignored by the target device, which results in a problem of data reading and writing.

To solve the above technical problem, the embodiment of the present application provides a first-in first-out buffer device 100 with an interrupt event retransmission mechanism.

Fig. 2 shows a block diagram of a fifo buffer device 100 according to an embodiment of the application, and as shown in fig. 2, the fifo buffer device 100 includes a storage module 11 and a control module 12.

The memory module 11 includes a FIFO memory 111. The storage module 11 is configured to store data in the FIFO memory 111 based on a write operation, and read data stored in the FIFO memory 111 based on a read operation.

The control module 12 is connected to the storage module 11, and the control module 12 is configured to generate an interrupt event based on the data amount of the data stored in the FIFO memory 111 and the interrupt condition. Wherein the interrupt event may be used to trigger an operation on FIFO memory 111.

In some possible implementations, one or more interrupt events may be set, any of which may trigger an associated operation. In some examples, each interrupt event is associated with a different operation. For example, interrupt event a is associated with operation a, i.e., interrupt event a is generated to trigger operation a; the interrupt event B is associated with operation B, i.e. the interrupt event B is generated to trigger operation B. In some examples, multiple interrupt events may be associated with the same operation. For example, interrupt event C is associated with operation F, i.e., interrupt event C is generated to trigger operation F; the interrupt event D is associated with operation F, i.e. the interrupt event D is generated to trigger operation F. That is, interrupt event C and interrupt event D may both be associated with operation F, i.e., both interrupt event C and interrupt event D are generated to trigger operation F.

In some possible embodiments, each interrupt event is associated with an interrupt condition, e.g., interrupt condition a is associated with interrupt event a, i.e., the premise of generating interrupt event a is that interrupt condition a is satisfied; the interrupt condition B is associated with the interrupt event B, i.e. the premise of generating the interrupt event B is that the interrupt condition B is satisfied.

In some possible implementations, each interrupt event is associated with a plurality of interrupt conditions. In some examples, an interrupt event is generated when any interrupt condition associated with the interrupt event is satisfied, that is, the relationship that the interrupt conditions are or. In other examples, an interrupt event is generated when all interrupt conditions associated with the interrupt event are satisfied, that is, the interrupt conditions are in a relationship with each other. Of course, the embodiment of the present application does not limit the logical relationship between the interrupt conditions.

Illustratively, interrupt event A is associated with interrupt condition A1, interrupt condition A2, and interrupt condition A3. The premise of generating the interrupt event a is that the interrupt condition A1, the interrupt condition A2, and the interrupt condition A3 are satisfied.

Illustratively, interrupt condition B is associated with interrupt event B1 and interrupt event B2. The premise of generating the interrupt event B is that the interrupt condition B1 or the interrupt event B2 is satisfied.

For example, an interrupt event a is generated when the interrupt condition a is satisfied to trigger the operation a; an interrupt event B is generated to trigger operation B when the interrupt condition B is satisfied.

For example, the interrupt event C is generated when the interrupt condition C is satisfied to trigger the operation F, and the interrupt event D is generated when the interrupt condition D is satisfied to trigger the operation F, i.e., the interrupt event generated by the interrupt condition C and the interrupt condition D trigger the operation F.

In this embodiment, the control module 12 is further configured to detect a first operation triggered by the interrupt event after the interrupt event is generated, and to generate the interrupt event again based on whether the first operation is detected. The interrupt condition is a condition concerning the data amount of the data stored in the FIFO memory 111. In this specification, "re-generating" is also referred to as "re-transmitting", i.e. re-generating the interrupt event, may be described as re-transmitting the interrupt event, and the re-generated interrupt event is also referred to as re-transmitting event.

In this embodiment, after the interrupt event is generated, when the first operation triggered by the interrupt event is detected, it indicates that the interrupt event is responded, and when the first operation is not detected, it indicates that the interrupt event is not responded. By adopting the embodiment, the interrupt event can be generated again based on whether the operation triggered by the interrupt event is detected or not, so that the problem of data reading and writing caused by the fact that the interrupt event is ignored is reduced.

An exemplary embodiment of the interrupt condition is described below.

As one embodiment, the interrupt condition may indicate: an interrupt event is generated when the amount of data stored in the FIFO memory 111 is not less than the data amount threshold.

For example, the first operation triggered by the interrupt event may be a read operation to cause the read device to read data from the FIFO memory 111 by the interrupt event. The reading device may perform one or more read operations in response to the interrupt event. Thereby enabling writing a plurality of times until the amount of data stored in the FIFO memory 111 is not less than the data amount threshold, triggering the reading means to read data from the FIFO memory 111, and when the amount of data stored in the FIFO memory 111 is less than the data amount threshold, the reading means may not perform a reading operation, thereby reducing the system power consumption. In particular, in the case where the rate of write operation is smaller than the rate of read operation, the system power consumption can be reduced.

The data amount of the data stored in the FIFO memory 111 is exemplarily described below.

Parameters of FIFO memory 111 may include the width and depth of the FIFO. The width of a FIFO refers to the data bits of a read operation or a write operation. The depth of the FIFO refers to how many N bits (N is the width of the FIFO) of data the FIFO memory 111 can store. An N-bit data may be referred to as a FIFO data.

The maximum number of N bits of data stored by the FIFO (i.e., the maximum number of FIFO data) is referred to as the maximum depth. When the depth of the stored data in the FIFO memory 111 reaches its maximum depth, the rewritten data may overflow (overflow). For example, the maximum depth of the FIFO memory 111 is 512, and when the FIFO memory 111 has stored data to a depth of 512, the re-written data will overflow. Furthermore, when the FIFO memory 111 is empty (i.e., data is not stored), continuing to read data from the FIFO memory 111 may cause underflow (underslow).

As an example, the data amount of the FIFO memory 111 storing data may be the stored data depth of the FIFO memory 111. Illustratively, the maximum depth of the FIFO memory 111 is 512, and when 100N bits (N is the width of the FIFO memory 111) of data are stored, that is, 100 FIFO data are stored, the stored data depth of the FIFO memory 111 is 100.

As an embodiment, the data amount threshold in the above interrupt condition may be a preset depth. Illustratively, the maximum depth of FIFO memory 111 is 512, and the data amount threshold may be 256. The interrupt condition may indicate: the above interrupt event is generated when the FIFO memory 111 has stored a data depth of not less than 256.

The embodiments of the present application are not limited in the manner in which interrupt events are generated and interrupt events are generated again.

In one aspect, embodiments of the present application are not limited to signals indicating the above-described interrupt event. As an embodiment, the same signal may be used for generating the interrupt event and for generating the interrupt event again. For example, the first signal may be used for both generating an interrupt event and generating an interrupt event again. As another embodiment, different signals may be used for generating the interrupt event and for generating the interrupt event again. Illustratively, generating an interrupt event uses a first signal and generating an interrupt event again uses a second signal that is different from the first signal.

On the other hand, the embodiment of the present application does not limit the interface generating the above signals. As an embodiment, the same interface may be used for generating the interrupt event and for generating the interrupt event again. For example, both generating an interrupt event and re-generating an interrupt event may use the first interface. As another implementation, different interfaces may be employed for generating the interrupt event and for generating the interrupt event again. For example, generating an interrupt event may use a first interface, and generating an interrupt event again may use a second interface different from the first interface.

As an example, an interrupt event is generated and an interrupt event is generated again, using the same interface and the same signal. As another example, an interrupt event is generated and an interrupt event is generated again using the same interface, and the interrupt event is generated using a first signal and the interrupt event is generated again using a second signal different from the first signal. As yet another example, generating an interrupt event employs a first interface, generating an interrupt event again uses a second interface different from the first interface, and generating an interrupt event again uses the same signal.

Embodiments are described below for generating an interrupt event again based on whether an interrupt event triggered operation is detected.

Embodiment one

As shown in fig. 3, the control module 12 includes a first timer 121, where the first timer 121 may start a first timing after generating the interrupt event, and a duration of the first timing is a first preset duration; the control module 12 is configured to re-generate the interrupt event if the first timer reaches a first preset duration and the first operation is not detected. By adopting the embodiment, when the interrupt event triggering operation is not performed within the first preset time period after the interrupt event is generated, the interrupt event is generated again, and the target device can be triggered again to perform the interrupt event triggering operation.

In some examples, the control module 12 is further configured to clear the first timer 121 and restart the first timing if the first timing reaches the first preset duration and the first operation is not detected. After restarting the first timing, the interrupt event may be generated again in case the first timing reaches a first preset duration and the first operation is not detected.

In some examples, the control module 12 is further configured to determine, when the first operation is detected during the first timing, whether the data amount of the data stored in the FIFO memory 111 after the first operation is performed meets the interrupt condition; when the data amount of the data stored in the FIFO memory 111 after the first operation is performed also meets the above-described interrupt condition, the first timer 121 is cleared and the above-described first timing is restarted; in the case where the data amount of the data stored in the FIFO memory 111 after the first operation is performed does not meet the above-described interrupt condition, the first timing is not performed. That is, in the case where the data amount of the data stored in the FIFO memory 111 after the first operation is performed does not meet the above-described interrupt condition, a determination is not made whether or not the interrupt event is generated again.

As an example, the first operation may be a read operation of the read device, detecting a read operation of the read device indicating that the read device has responded to the interrupt event, and not detecting a read operation of the read device indicating that the interrupt event was ignored by the read device.

As one example, the interrupt condition may indicate: an interrupt event is generated when the amount of data stored in the FIFO memory 111 is not less than the data amount threshold.

Illustratively, the control module 12 generates an interrupt event to trigger the reading device to read the data stored in the FIFO memory 111 when the amount of data stored in the FIFO memory 111 is not less than the amount of data threshold. The reading device may not perform a read operation when the data amount of the data stored in the FIFO memory 111 is less than the data amount threshold, and may perform a plurality of read operations when the data amount of the data stored in the FIFO memory 111 is not less than the data amount threshold, thereby reducing the system power consumption. If the read device ignores the interrupt event, it may cause the memory space of the memory module 11 to be filled and then overflowed. The first timer 121 starts a first timing after the interrupt event is generated, and the target duration of the first timing is a first preset duration. The control module 12 generates the interrupt event again to trigger the reading device to read the data stored in the FIFO memory 111 again in case the first timer reaches the first preset duration and no read operation is detected.

As a more specific example, the maximum depth is 512, the data amount threshold may be set to 256, and when the FIFO memory 111 has stored data depth reaches 256, an interrupt event is generated to trigger the reading device to read the data stored in the FIFO memory 111. If the interrupt event generated is ignored by the reading device for various reasons, the writing device still writes data to the FIFO memory 111 without timely reading the data, which may cause the FIFO memory 111 to be full of data and overflow, thereby causing data loss. For this purpose, the first timer 121 starts the first timing after the interrupt event is generated; the control module 12 generates the interrupt event again when the first timer reaches the first preset duration and the read operation is not detected, clears the first timer 121 and restarts the first timer; in the case where a read operation is detected during the first timing, it is determined whether the data amount of the data stored in the FIFO memory 111 after the read operation is performed is greater than a data amount threshold (i.e., whether an interrupt condition is satisfied); in the case where the data amount of the data stored in the FIFO memory 111 after the read operation is performed is greater than the data amount threshold (i.e., the interrupt condition is satisfied), the first timer is cleared and restarted.

Second embodiment

As shown in fig. 4, the control module 12 includes a counter 122. The counter 122 is configured to start counting a number of times of a preset number of second operations for triggering an interrupt event after the interrupt event is generated; the control module 12 is adapted to generate the interrupt event again in case the count reaches a preset number and no first operation is detected. By adopting the embodiment, the operation triggering the interrupt event is counted after the interrupt event is generated, and the target device can be triggered again to perform the operation triggering the interrupt event under the condition that the operation triggering the interrupt event is not performed yet after the operation triggering the interrupt event is performed for a preset number.

In some examples, the counter 122 is also cleared and restarted if the count reaches a preset number and no first operation is detected. After restarting the above-mentioned counting, the interrupt event is generated again in case the counting reaches a preset number and the first operation is not detected.

In some examples, in the case that the first operation is detected during the counting, it is determined whether the data amount of the data stored in the FIFO memory 111 after the first operation is performed meets a corresponding interrupt condition (i.e., an interrupt condition corresponding to the interrupt event); when the interrupt condition is satisfied, the counter 122 is cleared and the count is restarted; if the interrupt condition is not satisfied, the count is not performed.

As one example, the first operation may be a read operation and the second operation may be a write operation. The data is written into the FIFO memory 111 for storage based on a write operation, which increases the data amount of the FIFO memory 111 storing the data. The data stored in the FIFO memory 111 is read based on a read operation, which reduces the data amount of the FIFO memory 111 storing data. The write operation causes the data amount of the FIFO memory 111 to increase, the control module 12 generates an interrupt event based on the data amount of the FIFO memory 111 and the interrupt condition, the counter 122 counts the write operation, generates the interrupt event again in the case where the write operation reaches the preset number and the read operation is not detected, and clears the counter 122, that is, after the interrupt event is generated, if the FIFO memory 111 stores data to a certain degree, generates the interrupt event again. If the read operation is not triggered while the write operation is continued, the interrupt event is generated again based on the count of the write operation, and the possibility of being full and overflowing can be reduced.

In this example, counting write operations corresponds to counting the number of FIFO data. In some cases, the bit width of each write operation is equal to the width of the FIFO, and illustratively, each write operation writes data with a bit width of 4 and the FIFO width of 4, each write operation is considered to write one FIFO data. The counting of write operations at this time corresponds to counting the number of write FIFO data. In other cases, the bit width of each write operation is less than the width of the FIFO, and illustratively, each write operation writes data with a bit width of 4 and the FIFO with a width of 8, then each 2 write operations is considered to write one FIFO data. At this time, the count of the write operation and the number of the write FIFO data have a correspondence, and when the bit width of the write data is 4 and the width of the FIFO is 8 in the write operation, the count of the number of times of the write operation is 2M corresponds to the count of the number of times of the write FIFO data is M.

In some examples, the interrupt condition may indicate: when the data amount of the data stored in the FIFO memory 111 is not less than the data amount threshold, an interrupt event is generated to trigger a read operation.

For example, the interrupt condition may indicate: when the data amount of the data stored in the FIFO memory 111 reaches the data amount threshold, an interrupt event is generated, and the reading device reads the data stored in the FIFO memory 111 in response to the interrupt event, the reading device may perform a plurality of reading operations to read a plurality of data, thereby reducing the system power consumption. In this example, the data amount is a stored data depth and the data amount threshold may be determined based on the maximum depth.

As a more specific example, the maximum depth is 512, the data amount threshold may be set to 256, and when the FIFO memory 111 has stored data to a depth of 256, an interrupt event is generated to trigger the reading device to read the data stored in the memory module 11. If the interrupt event generated is ignored by the reading device for various reasons, the writing device still writes data into the FIFO memory 111, which will cause the FIFO memory 111 to be full of data and overflow, and further cause problems such as data loss. To this end, the counter 122 counts write operations after generating an interrupt event; in the event that the count of write operations reaches the preset number and no read operations are detected, the control module 12 again generates the interrupt event and clears the counter 122 and resumes counting; in the case where a read operation is detected during counting, it is determined whether the data amount of the data stored in the FIFO memory 111 after the read operation is performed is smaller than a data amount threshold (i.e., whether an interrupt condition is satisfied); in the case where the data amount of the data stored in the FIFO memory 111 is not less than the data amount threshold (i.e., the interrupt condition is satisfied), the counter 122 is cleared and the count is restarted.

In some embodiments, as shown in fig. 5, the control module 12 may also include a second timer 123. The second timer 123 is configured to start a second timing after detecting the first operation, where a duration of the second timing is a second preset duration. A control module 12 for suspending generation of the interrupt event based on the data amount stored in the FIFO memory 111 and the interrupt condition, in the case where the second timing does not reach the second preset time period; continuing to generate an interrupt event based on the amount of data stored in the FIFO memory 111 and the interrupt condition when the second timing reaches a second preset duration; in the event that a new first operation is detected during the second timing, the second timer 123 is cleared and the second timing is restarted. By adopting the embodiment, the first operation triggered by the interrupt event can be reduced, and the interrupt event can be triggered again when the first operation triggered by the interrupt event is performed. This embodiment will be described with reference to an example.

Illustratively, the interrupt event is generated when the amount of data stored in the FIFO memory 111 is not less than the data amount threshold. After the reading device has just read the data below the data amount threshold in response to the interrupt event, new data is written into the FIFO memory 111, so that the data amount of the data stored in the FIFO memory 111 again reaches the data amount threshold, and the interrupt event is generated again.

For example, the maximum depth is 512, the data amount threshold is 256, after the data amount of the data stored in the fifo memory 111 is 256, the data amount after the reading device reads once is 255 after the interrupt event is generated, and since the two reading operations have a time interval, if the data amount is 256 again before the next reading operation is generated, the interrupt event is regenerated. At this time, the reading device is responding to the interrupt event, and the interrupt event is generated again, so that the system can make redundant judgment. To reduce this, a second timer is started in response to detecting a read operation; in the case where the second timing does not reach the second preset time period, suspending generation of the interrupt event based on the amount of data stored in the FIFO memory 11 and the interrupt condition; continuing to generate an interrupt event based on the amount of data stored in the FIFO memory 111 and the interrupt condition in the case when the second timing reaches the second preset time period; in the event that a new read operation is detected during the second timing, the second timer 123 is cleared and the second timing is restarted. By adopting the embodiment, the triggering of the interrupt event again when the read operation triggered by the interrupt event is performed can be reduced.

Fig. 6 shows a block diagram of a fifo buffer device according to an embodiment of the application, and as shown in fig. 6, a fifo buffer device 600 includes: a memory module 61 and a control module 62. The memory module 61 includes a FIFO memory 611. The storage module 61 stores data in the FIFO memory 611 based on a write operation, and reads the data stored in the FIFO memory 611 based on a read operation.

As shown in fig. 6, the control module 62 may include: a threshold judgment block 621 and a retransmission timer 622 (corresponding to the first timer 121 described above).

A write threshold (corresponding to the data amount threshold described in the present specification) is configured, and a retransmission time (corresponding to the first preset time period described in the present specification) is configured.

The threshold determination module 621 generates an interrupt event (referred to as a threshold event) when the write data reaches the configured write threshold to trigger the read device to perform a read operation. The read device performs a read operation in response to the threshold event to read data from the FIFO memory 611. The reading means may perform one or more read operations after receiving the threshold event.

After the interrupt event is generated, the retransmission timer 622 starts counting. After the retransmission timer 622 counts the configured retransmission time, if the read operation is not yet detected, an interrupt event (referred to as a retransmission event) is again generated, and the retransmission timer 622 is cleared and restarted, so that the retransmission event can be generated multiple times. When the read device generates a read operation, indicating that the read device has responded to a threshold event or a retransmission event, the retransmission timer 622 is cleared and timing is restarted. Each read operation will clear the retransmission timer 622. The retransmission timer 622 will continue to count when the read device stops reading data and the currently stored data is still greater than the write threshold to generate a retransmission event. When the stored data is less than the write threshold, the retransmission timer 622 is cleared and does not count, without affecting the threshold determination module 621 to generate a threshold event.

After the reading device just reads the data so that the stored data is lower than the writing threshold value, new data is written, so that the stored data reaches the writing threshold value again, and the threshold event is generated when the threshold event generating condition is met. For example, the depth is 512, the writing threshold is 256, after the stored data is 256, the stored data is 255 after being read once by the reading device, and a write operation is generated before the data is read next time, the stored data is 256 again, and the threshold event is regenerated. At this time, the reading device is responding to the threshold event, and the system can make redundant judgment by generating the threshold event again. To reduce this, as shown in fig. 6, the control module 62 may further include a mask timer 623 (corresponding to the second timer 123 described above).

The masking time (corresponding to the second preset time period described in the present specification) is configured. Each time the read device generates a read operation, the mask enable is turned on while the mask timer 623 is cleared and timing is restarted. When the mask timer 623 times to the configured mask time, the mask timer 623 stops counting, and the mask enable is turned off. During the mask enable open period, the generated threshold event is not valid. During the mask enable off period, the generated threshold event is valid.

As shown in fig. 6, the control module 62 further includes a logic module 624 for disabling the threshold event during a mask enable active on period; during mask enable off, a threshold event is output. The logic module 624 includes: a NOT gate 6241 for negating the mask enable; and gate 6242 for ANDing the threshold event with the output of NOT gate 6241.

FIG. 7 is a block diagram illustrating another embodiment of a FIFO buffer device according to the present invention, as shown in FIG. 7, the FIFO buffer device 700 may comprise: a storage module 71 and a control module 72. The storage module 71 stores data in the FIFO memory 711 based on a write operation, and reads data stored in the FIFO memory 711 based on a read operation.

As shown in fig. 7, the control module 72 may include: a threshold value judgment module 721 and a retransmission counter 722 (corresponding to the counter 122 described above).

A write threshold (corresponding to the data amount threshold described in the present specification) is configured, and the number of retransmissions (corresponding to the preset number described in the present specification) is configured. The threshold determination module 721 generates an interrupt event (referred to as a threshold event) to trigger the read device to perform a read operation when the write data reaches a configured write threshold. The read device performs a read operation in response to the threshold event to read data from the FIFO memory 711. The reading means may perform one or more read operations after receiving the threshold event.

After the threshold event is generated, the retransmission counter 722 starts counting, and when the reading device generates a reading operation, the retransmission counter 722 is cleared and starts counting again. The threshold judgment module 721 generates a threshold event (referred to as a retransmission event) again after the retransmission counter 722 counts up to the number of retransmissions. When the reading device reads data such that the amount of data stored in the FIFO memory 711 is below the write threshold, the retransmission counter 722 is cleared and will not count until the stored amount of data reaches the write threshold.

As shown in fig. 7, the control module 72 may further include a mask timer 723 (corresponding to the second timer 123 described above) and a logic module 724. The mask timer 723 and the logic module 724 are described with reference to fig. 6, and are not described in detail herein.

The embodiment of the application also provides a control method of the first-in first-out buffer device.

Fig. 8 is a flowchart illustrating a control method of the fifo buffer device according to the embodiment of the application, as shown in fig. 8, and the method includes steps S802 to S806.

In step S802, data is stored in the FIFO memory based on the write operation, and the data stored in the FIFO memory is read based on the read operation.

In step S804, an interrupt event is generated based on the data amount of the FIFO memory storage data and the interrupt condition.

In step S806, after the interrupt event is generated, a first operation triggered by the interrupt event is detected, and the interrupt event is generated again based on whether the first operation is detected.

Based on the method, after the interrupt event is generated, the operation triggered by the interrupt event is detected, and the interrupt event can be generated again based on whether the operation triggered by the interrupt event is detected or not, so that the problem of data reading and writing caused by the fact that the interrupt event is ignored can be reduced.

A control method applied to the fifo buffer device shown in fig. 3 is described below with reference to fig. 9.

Step S901 determines whether an interrupt event is generated based on the data amount of FIFO memory storage data and the interrupt condition.

In a case where the data amount of the FIFO memory storage data satisfies the interrupt condition, the flow advances to step S902. In the case where the data amount of the FIFO memory storage data does not satisfy the interrupt condition, the process returns to step S901.

In step S902, an interrupt event is generated.

In step S903, a first operation triggered by an interrupt event is detected, and a first timer starts a first timing. The first timing duration is a first preset duration.

Step S904, determining whether the first timing reaches a first preset duration and whether the first operation is detected.

If the first timer reaches the first preset duration and the first operation is not detected, the process returns to step S902 to generate the interrupt event again.

In the case where the first timing does not reach the first preset duration and the first operation is detected, it is determined whether the data amount of the FIFO memory storage data after the first operation satisfies the interrupt condition (step S905). In the case where the data amount of the FIFO memory storage data after the first operation satisfies the interrupt condition, the flow returns to step S903, the first operation triggered by the interrupt event is detected, and the first timer restarts the first timing. In the case where the data amount of the FIFO memory storage data after the first operation does not satisfy the interrupt condition, the process returns to step S901.

The following describes a control method applied to the fifo buffer device shown in fig. 4 with reference to fig. 10.

In step S1001, it is determined whether an interrupt event is generated based on the data amount of the FIFO memory storage data and the interrupt condition.

In a case where the data amount of the FIFO memory storage data satisfies the interrupt condition, the flow advances to step S1002. In the case where the data amount of the FIFO memory storage data does not satisfy the interrupt condition, the flow returns to step S1001.

In step S1002, an interrupt event is generated.

In step S1003, a first operation triggered by an interrupt event is detected, and a counter starts counting. Wherein the counted number is a preset number.

Step S1004, determines whether the count reaches a preset number and whether the first operation is detected.

In the case where the count reaches the preset number and the first operation is not detected, the process returns to step S1002 to generate the interrupt event again.

In the case where the count does not reach the preset number and the first operation is detected, it is determined whether the data amount of the FIFO memory storage data after the first operation satisfies the interrupt condition (step S1005). In the case where the data amount of the FIFO memory storage data after the first operation satisfies the interrupt condition, the flow returns to step S1003, the first operation triggered by the interrupt event is detected, and the counter restarts the above-described counting. In the case where the data amount of the FIFO memory storage data after the first operation does not satisfy the interrupt condition, the flow returns to step S1001.

The following describes a control method applied to the fifo buffer device shown in fig. 5 with reference to fig. 11.

Step S1101, it is determined whether an interrupt event is generated based on the data amount of the FIFO memory storage data and the interrupt condition.

In a case where the data amount of the FIFO memory storage data satisfies the interrupt condition, the flow advances to step S1102. In the case where the data amount of the FIFO memory storage data does not satisfy the interrupt condition, the flow returns to step S1101.

In step S1102, an interrupt event is generated.

In step S1103, a first operation triggered by the interrupt event is detected. The step S1103 may refer to the descriptions of fig. 9 and 10 for generating the interrupt event again based on whether the first operation is detected, which will not be described herein.

After the first operation is detected, the second timer starts the second timing (step S1104). The second timing duration is a second preset duration.

Step S1105, determining whether the second timing reaches a second preset duration.

In the event that the second timing has not reached the second preset duration, the generation of the interrupt event based on the amount of data stored in the FIFO memory and the interrupt condition is suspended.

When the second timing reaches the second preset time period, the process returns to step S1101 to continue generating an interrupt event based on the amount of data stored in the FIFO memory and the interrupt condition.

In the course of the second timing, it is determined whether a new first operation is detected (step S1106). If a new first operation is detected, the routine returns to step S1104, clears the second timer, and restarts the second timer.

The control method applied to the fifo buffer device shown in fig. 6 is described below.

A retransmission timer is added to configure the retransmission time. After the FIFO writing data reaches the configuration threshold value to generate a threshold event, a retransmission timer starts to count, and after the configured retransmission time is counted, a retransmission event is generated, the timer is cleared, and the timing is restarted, so that the retransmission event can be repeatedly generated.

When the read device generates a read operation, it indicates that the read device has cleared the retransmission timer in response to a threshold event or a retransmission event. Resetting the retransmission timer every time of reading operation, and when the reading equipment stops reading the FIFO data and the current FIFO stored data is still larger than the configuration threshold value, continuing to count the retransmission timer to generate a retransmission event; when the FIFO stored data is less than the configured threshold, the retransmission timer is cleared and does not count so as not to affect the normal threshold event.

After the read FIFO is just below the set threshold, new data is written into the FIFO so that the FIFO again reaches the threshold, generating a threshold event. For example, the FIFO depth 512 is set to 256, after the FIFO storage data is 256, the FIFO storage data is 255 after the read device reads once, and a write operation is generated before the FIFO data is read next time, the storage data is 256 again, and the threshold event is regenerated. However, such threshold event systems are desirably masked because the read device is now responding to the threshold event, and again generating the threshold event would make the system make redundant decisions. To avoid this, a configuration of masking time is added, masking enable is turned on each time the read device generates a read operation, while the masking timer is cleared and timing is restarted. When the mask timer times to the configured mask time, the mask timer stops counting, and the mask enable is closed. During the mask enable open period, the generated mask event is not valid.

The following describes a control method applied to the fifo buffer device shown in fig. 7.

When a threshold event occurs, the retransmission counter is cleared and begins counting. Every time 1 FIFO data is rewritten, the counter is incremented by 1, and a retransmission event is generated when the retransmission counter count value is equal to the configured count value.

E.g., FIFO depth 512, set the threshold to 256, and retransmit counter set to 20, the FIFO stores data to generate a retransmit event for every 20 data writes after generating a threshold event for 256.

When the reading device generates a reading operation, resetting the retransmission counter; when the read device reads data such that the FIFO stored data amount is below the threshold, the retransmission counter is cleared and will not count until the FIFO stored data amount reaches the threshold.

Similarly, immediately after the read FIFO falls below the set threshold, new data is written into the FIFO such that the FIFO again reaches the threshold, generating a threshold event. Such threshold event systems are desirably masked, and to avoid this, the masking method described above may be employed, which is not described in detail herein.

An exemplary scenario is described below.

In a part of FIFO application scenes, the write FIFO rate is lower, the read FIFO rate is higher, a data quantity threshold value can be set, when the data quantity of the FIFO stored data reaches the data quantity threshold value, an interrupt event is generated, the reading device is awakened and reminded to read the FIFO data, and after the reading device is awakened, a plurality of read operations can be performed to read a plurality of FIFO data, so that the system power consumption is reduced. For example, the FIFO depth is 512 and the data amount threshold is set to 256, then an interrupt event is generated when the data amount of FIFO stored data reaches 256. After receiving the event, the reading device for reading the FIFO reads the FIFO data in response to the interrupt event.

In this scenario, if the generated interrupt event is ignored by the reading device reading the FIFO for various reasons, the data in the FIFO is not read in time, which is likely to cause the FIFO to be full of data and overflow, resulting in data loss. By adopting any first-in first-out buffer device and control method, through the mechanism of generating interrupt event again, the read equipment for reading the FIFO can receive the interrupt event again after ignoring the interrupt event due to various abnormal conditions, and timely read the data in the FIFO, thereby avoiding overflow.

The embodiment of the application also provides a chip, which comprises the first-in first-out buffer device. The Chip is also referred to as an integrated circuit (Integrated Circuit, IC) and may be, but is not limited to, a SOC (System on Chip) Chip, a SIP (System in package) Chip. The chip resends the interrupt event based on whether the interrupt event triggered operation is detected, so that the problem of data reading and writing caused by the fact that the interrupt event is ignored is reduced.

The embodiment of the application also provides electronic equipment, which comprises an equipment main body and the chip arranged in the equipment theme. The electronic device may be, but is not limited to, a weight scale, a body fat scale, a nutritional scale, an infrared electronic thermometer, a pulse oximeter, a body composition analyzer, a mobile power supply, a wireless charger, a quick charger, an on-board charger, an adapter, a display, a USB (Universal Serial Bus ) docking station, a stylus, a real wireless headset, an automotive center control screen, an automobile, an intelligent wearable device, a mobile terminal, an intelligent home device. The intelligent wearing equipment comprises, but is not limited to, an intelligent watch, an intelligent bracelet and a cervical vertebra massage instrument. Mobile terminals include, but are not limited to, smartphones, notebook computers, tablet computers, POS (point of sales terminal, point of sale terminal) machines. The intelligent household equipment comprises, but is not limited to, an intelligent socket, an intelligent electric cooker, an intelligent sweeper and an intelligent lamp. The electronic device resends the interrupt event by detecting an operation triggered by the interrupt event, thereby reducing the occurrence of problems in data reading and writing caused by the fact that the interrupt event is ignored.

The foregoing description is not intended to limit the preferred embodiments of the present application, but is not intended to limit the scope of the present application, and any such modifications, equivalents and adaptations of the embodiments described above in accordance with the principles of the present application should and are intended to be within the scope of the present application, as long as they do not depart from the scope of the present application.

Claims (13)

1. A fifo buffer device, comprising:

a storage module for storing data in a FIFO memory based on a write operation, and reading the data stored in the FIFO memory based on a read operation;

a control module for generating an interrupt event based on the data amount of the FIFO memory storage data and an interrupt condition, wherein the interrupt event is used for triggering the FIFO memory to be operated; after the interrupt event is generated, detecting a first operation triggered by the interrupt event, and generating the interrupt event again based on whether the first operation is detected.

2. The fifo buffer device of claim 1, wherein the control module comprises: a first timer;

the first timer is used for starting first timing after the interrupt event is generated, wherein the duration of the first timing is a first preset duration;

the control module is configured to, when the first timing reaches the first preset duration and the first operation is not detected, generate the interrupt event again.

3. The fifo buffer device of claim 2, wherein the control module is further configured to:

judging whether the data amount of the data stored in the FIFO memory after the first operation is performed meets the interrupt condition or not under the condition that the first operation is detected in the first timing process;

and under the condition that the interrupt condition is met, resetting the first timer and restarting the first timing.

4. The fifo buffer device of claim 1, wherein the control module comprises: a counter;

the counter is used for starting to count a second operation triggering the interrupt event after the interrupt event is generated, wherein the counted times are preset numbers;

The control module is configured to, when the count reaches the preset number and the first operation is not detected, generate the interrupt event again.

5. The FIFO buffer device as recited in claim 4, wherein the control module is further configured to

Judging whether the data amount of the data stored in the FIFO memory after the first operation is performed meets the interrupt condition or not under the condition that the first operation is detected in the counting process;

and when the interrupt condition is met, the counter is cleared and the counting is restarted.

6. The fifo buffer device of any of claims 1-5, wherein the control module further comprises: a second timer;

the second timer is used for starting a second timing after the first operation is detected, wherein the duration of the second timing is a second preset duration;

wherein, the control module is used for:

suspending generating the interrupt event based on the amount of data stored in the FIFO memory and the interrupt condition if the second timing does not reach the second preset duration;

continuing to generate the interrupt event based on the amount of data stored in the FIFO memory and the interrupt condition if the second timing reaches the second preset duration;

And when the new first operation is detected in the process of the second timing, resetting the second timer and restarting the second timing.

7. The fifo buffer device of claim 1, wherein the first operation is the read operation.

8. The fifo buffer device of claim 4, wherein the first operation is the read operation and the second operation is the write operation.

9. The fifo buffer device of any of claims 1-5, 7, 8, wherein the interrupt condition indicates: the interrupt event is generated when the amount of data stored by the FIFO memory is not less than the data amount threshold.

10. The fifo buffer device of claim 9, wherein the rate of the write operation is less than the rate of the read operation, the first operation triggered by the interrupt event being the read operation.

11. A method for controlling a fifo buffer device, comprising:

storing data in a FIFO memory based on a write operation, reading the data stored in the FIFO memory based on a read operation;

Generating an interrupt event based on the data amount of the FIFO memory storage data and an interrupt condition, wherein the interrupt event is used for triggering the FIFO memory to be operated;

after the interrupt event is generated, detecting a first operation triggered by the interrupt event, and generating the interrupt event again based on whether the first operation is detected.

12. A chip comprising a first-in first-out buffer device according to any one of claims 1 to 10.

13. An electronic device comprising a device body and the chip of claim 12 provided on the device body.