CN115756950A

CN115756950A - IIC bus recovery method, device, equipment, medium and system

Info

Publication number: CN115756950A
Application number: CN202211166631.1A
Authority: CN
Inventors: 赵宇; 黄军
Original assignee: Huizhou Desay SV Intelligent Transport Technology Research Institute Co Ltd
Current assignee: Huizhou Desay SV Intelligent Transport Technology Research Institute Co Ltd
Priority date: 2022-09-23
Filing date: 2022-09-23
Publication date: 2023-03-07

Abstract

The invention discloses an IIC bus recovery method, an IIC bus recovery device, an IIC bus recovery equipment, an IIC bus recovery medium and an IIC bus recovery system. The method comprises the following steps: after a second device is determined in the plurality of devices, performing data interaction with the second device through an IIC bus, wherein the IIC bus comprises a data line and a clock line; when communication abnormality is detected, changing the waveform of a data signal to generate a termination signal after an IIC bus recovery mechanism is triggered, wherein the data signal is sent through the data line; sending the termination signal to the second device over the clock line to restore normal communication to the IIC bus. According to the method, the waveform of the data signal is changed to generate the termination signal after the IIC bus recovery mechanism is triggered, so that the time sequence of the current IIC bus recovery mechanism can be optimized, the error rewriting of a slave device register caused by the defect of the IIC bus recovery mechanism is avoided, the stability of the IIC bus is improved, and the stability and the safety of the device operation are further improved.

Description

IIC bus recovery method, device, equipment, medium and system

Technical Field

The embodiment of the invention relates to the technical field of communication, in particular to an IIC bus recovery method, device, equipment, medium and system.

Background

An Inter-Integrated Circuit (IIC) is a simple, bi-directional, two-wire, synchronous serial bus that is used primarily to connect the entire Circuit, i.e., multiple chips can be connected to the same bus structure.

During data interaction of the IIC bus, communication abnormality of the IIC bus can be caused for some reasons, and further operation abnormality of equipment can be caused. In the prior art, a master device sends out a plurality of clock pulses, so that a slave device releases an IIC bus after receiving a certain clock pulse of the plurality of clock pulses, so as to keep the IIC bus in normal communication.

However, in some cases, the slave device recognizes a plurality of clock pulses as a normal clock waveform, and analyzes the data signal based on the clock waveform, and then writes the analyzed data signal into the next register, resulting in an abnormal operation of the device.

Disclosure of Invention

The invention provides an IIC bus recovery method, an IIC bus recovery device, an IIC bus recovery medium and an IIC bus recovery system, and aims to solve the problem of error rewriting of a slave device register caused by the defect of an IIC bus recovery mechanism.

According to an aspect of the present invention, there is provided an IIC bus recovery method applied to a first device, including:

after a second device is determined in the plurality of devices, performing data interaction with the second device through an IIC bus, wherein the IIC bus comprises a data line and a clock line;

when communication abnormality is detected, the waveform of a data signal is changed to generate a termination signal after an IIC bus recovery mechanism is triggered, and the data signal is sent through the data line;

sending the termination signal to the second device over the clock line to resume normal communication with the IIC bus.

According to another aspect of the present invention, there is provided an IIC bus recovery method applied to a second device, including:

performing data interaction with first equipment through an IIC bus;

and when the first equipment detects that the communication is abnormal, receiving a termination signal sent by the first equipment so as to enable the IIC bus to recover normal communication.

The termination signal is generated by changing the waveform of a data signal after the first device triggers an IIC bus recovery mechanism.

According to another aspect of the present invention, there is provided an IIC bus recovery apparatus applied to a first device, including:

the interactive module is used for performing data interaction with the second equipment through an IIC bus after the second equipment is determined in the plurality of equipment, wherein the IIC bus comprises a data line and a clock line;

the generating module is used for changing the waveform of a data signal to generate a termination signal after an IIC bus recovery mechanism is triggered when communication abnormity is detected, and the data signal is sent through the data line;

and the sending module is used for sending the termination signal to the second equipment through the clock line so as to enable the IIC bus to recover normal communication.

According to another aspect of the present invention, there is provided an IIC bus recovery apparatus applied to a second device, including:

the interaction module is used for performing data interaction with the first equipment through the IIC bus;

and the receiving module is used for receiving a termination signal sent by the first equipment when the first equipment detects that the communication is abnormal, so that the IIC bus recovers normal communication.

According to an aspect of the present invention, there is provided a first device, the electronic device including: at least one processor; and

a memory communicatively coupled to the at least one processor; wherein the content of the first and second substances,

the memory stores a computer program executable by the at least one processor, the computer program being executable by the at least one processor to enable the at least one processor to perform an IIC bus recovery method according to an aspect of the present invention.

According to another aspect of the present invention, there is provided a second device, the electronic device including: at least one processor; and

a memory communicatively coupled to the at least one processor; wherein, the first and the second end of the pipe are connected with each other,

the memory stores a computer program executable by the at least one processor to enable the at least one processor to perform the IIC bus restoration method according to another aspect of the present invention.

According to another aspect of the present invention, there is provided a computer-readable storage medium storing computer instructions for causing a processor to implement a method of IIC bus restoration according to any one of the embodiments of the present invention when executed.

According to another aspect of the present invention, there is provided an IIC bus recovery system, including: a first device as described in one aspect of the invention, an IIC bus, and a second device as described in another aspect of the invention.

According to the technical scheme of the embodiment of the invention, after the second equipment is determined in the plurality of equipment, data interaction is carried out on the second equipment through an IIC bus, wherein the IIC bus comprises a data line and a clock line; when communication abnormality is detected, the waveform of a data signal is changed to generate a termination signal after an IIC bus recovery mechanism is triggered, and the data signal is sent through the data line; sending the termination signal to the second device over the clock line to restore normal communication to the IIC bus. According to the method, the waveform of the data signal is changed to generate the termination signal after the IIC bus recovery mechanism is triggered, so that the time sequence of the current IIC bus recovery mechanism can be optimized, the register error rewriting of the slave equipment caused by the defect of the IIC bus recovery mechanism is avoided, the stability of the IIC bus is improved, and the running stability and safety of the equipment are further improved.

It should be understood that the statements in this section do not necessarily identify key or critical features of the embodiments of the present invention, nor do they necessarily limit the scope of the invention. Other features of the present invention will become apparent from the following description.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.

FIG. 1 is a flow diagram of data interaction of an IIC bus in the prior art;

FIG. 2 is a communication timing diagram of an IIC bus of the prior art;

FIG. 3 is a schematic diagram illustrating a process of a jamming occurring in IIC bus data interaction in the prior art;

FIG. 4 is a flowchart illustrating an IIC bus recovery method according to an embodiment of the present invention;

FIG. 5 is a schematic diagram of a pulse contrast scheme according to an embodiment of the present invention;

FIG. 6 is a flowchart illustrating an IIC bus recovery method according to an exemplary embodiment of the present invention;

FIG. 7 is a flowchart illustrating an IIC bus recovery method according to a second embodiment of the present invention;

FIG. 8 is a schematic structural diagram of an IIC bus recovery apparatus according to a third embodiment of the present invention;

fig. 9 is a schematic structural diagram of an IIC bus recovery apparatus according to a fourth embodiment of the present invention;

fig. 10 is a schematic structural diagram of an IIC bus recovery system according to a fifth embodiment of the present invention;

fig. 11 is a schematic structural diagram of an IIC bus recovery apparatus according to a sixth embodiment of the present invention.

Detailed Description

In order to make the technical solutions of the present invention better understood, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention. It should be understood that the various steps recited in the method embodiments of the present invention may be performed in a different order and/or performed in parallel. Moreover, method embodiments may include additional steps and/or omit performing the illustrated steps. The scope of the invention is not limited in this respect.

The term "including" and variations thereof as used herein is intended to be open-ended, i.e., "including but not limited to". The term "based on" is "based at least in part on". The term "one embodiment" means "at least one embodiment"; the term "another embodiment" means "at least one additional embodiment"; the term "some embodiments" means "at least some embodiments". Relevant definitions for other terms will be given in the following description.

It should be noted that the terms "first," "second," and the like in the description and claims of the present invention and in the drawings described above are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used is interchangeable under appropriate circumstances such that the embodiments of the invention described herein are capable of operation in other sequences than those illustrated or described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.

It is noted that references to "a", "an", and "the" modifications in the present invention are intended to be illustrative rather than limiting, and that those skilled in the art will recognize that reference to "one or more" unless the context clearly dictates otherwise.

The names of messages or information exchanged between devices in the embodiments of the present invention are for illustrative purposes only, and are not intended to limit the scope of the messages or information.

Fig. 1 is a data interaction flow diagram of an IIC bus in the prior art, and as shown in fig. 1, the interaction flow may include the following processes: the master device sends a start signal to inform all slave devices on the bus to start transmission; the host sends the slave address, the slave matching the address is ready, and other slaves ignore the next transmission and wait for the start of the next transmission; after the master device addresses the slave device, the master device sends the register address in the slave device to be read or written by the master device, and the slave device searches a register according to the register address; the master device sends data to the slave device, and the slave device can write the data into the register; and after the data transmission is finished, the master equipment transmits a termination signal to the slave equipment, and the slave equipment stops data interaction after receiving the termination signal.

Fig. 2 is a communication timing diagram of an IIC bus in the prior art, as shown in fig. 2, signals transmitted between a master device and a slave device are determined by SDA, i.e., data signals, and SCL, i.e., clock signals, where SDA is transmitted through a data line on the IIC bus and SCL is transmitted through a clock line on the IIC bus, for example, a start signal sent from the master device to the slave device is composed of a high level of SCL and a falling edge of SAD; the termination signal sent by the master device to the slave device consists of the high level of SCL and the rising edge of SAD.

In the process of data interaction between the master device and the slave device through the IIC bus, the IIC bus is blocked due to some reasons, and if an IIC bus recovery mechanism is not adopted, the abnormal IIC communication can cause abnormal operation of machine equipment.

The IIC bus recovery mechanism includes that when the IIC master device detects the SDA jamming, the master device needs to control the SCL to generate 9 square waves, so that the slave device releases the IIC bus at a certain time within the 9 clock pulses, and the IIC bus is recovered. If the IIC bus cannot be restored, a hardware reset or a power-up cycle is used to clear the IIC bus.

Specifically, when the master device detects that the SDA data is stuck, the master device triggers an IIC bus recovery mechanism, the master device controls the SCL to send 9 CLK clock pulses, the SDA data maintains a default value of 0 at this time, and the slave device releases the IIC bus after detecting 9 pulses, so that the master device and the slave device reestablish a connection to recover normal communication. Fig. 3 is a schematic diagram illustrating a flow of a jam occurring in IIC bus data interaction in the prior art, as shown in fig. 3, when the master device triggers an IIC recovery mechanism when a stop signal is sent, since the SDA defaults to 0, the slave device recognizes the 9 clock pulses as a normal CLK waveform and parses SDA data based on the CLK waveform, writes the parsed SDA data into a next register, and at this time, the slave device writes the parsed SDA into a next register, and since the SDA data is incorrectly recognized, a value of the next register is rewritten, which causes an abnormal operation of the device.

To solve the above problem, an embodiment of the present invention provides an IIC bus recovery method.

Fig. 4 is a flowchart of an IIC bus recovery method according to an embodiment of the present invention, where the method is applicable to a case of performing IIC bus recovery when communication is abnormal, and the method may be executed by an IIC bus recovery apparatus, where the apparatus may be implemented by software and/or hardware and is generally integrated on a host device, where the host device includes but is not limited to: processors, memory, etc.

As shown in fig. 4, a method for recovering an IIC bus according to an embodiment of the present invention includes the following steps:

and S110, after the second equipment is determined in the plurality of equipment, performing data interaction with the second equipment through an IIC bus, wherein the IIC bus comprises a data line and a clock line.

In this embodiment, the master device may be a microcontroller on an IIC bus, where a plurality of slave devices may be connected to the IIC bus, and a slave device may be understood as a slave device that cannot operate autonomously and needs to operate depending on the master device.

Wherein, the data line can be understood as a route for transmitting data signals; a clock line may be understood as a route that transmits a clock signal.

The second device may be a device that performs data interaction with the first device among a plurality of slave devices.

In this embodiment, the manner in which the second device is determined is not limited. One possible way may be: and after the starting signal is sent to the second equipment, the address of the second equipment is sent to the plurality of equipment so as to determine the second equipment from the plurality of equipment.

Specifically, after the first device sends the start signal, the first device may send the address of the second device to all the slave devices, and find the corresponding second device from all the slave devices according to the address.

The IIC bus is an integrated circuit bus, and is a serial bus which is composed of a data line and a clock line and can transmit and receive data.

Specifically, the data interaction with the second device through the IIC bus includes: sending the register address to a second device so that the second device searches a register according to the register address; sending data to the second device to cause the second device to write the data to the register; and sending a termination signal to the second equipment to end the data interaction with the second equipment.

The first device sends an internal register address of the second device to be read or written to the second device, so that the second device finds a corresponding register according to the address; the first device sends the data to the second device, and the second device writes the data into the register; the first equipment sends a termination signal to the second equipment, and the second equipment stops data interaction with the first equipment after receiving the termination signal.

And S120, when the communication is detected to be abnormal, changing the waveform of the data signal to generate a termination signal after an IIC bus recovery mechanism is triggered, wherein the data signal is sent through the data line.

In this embodiment, the communication abnormality may include a plurality of abnormal situations, which is not specifically limited herein, and the communication abnormality may include a pause when the first device sends the termination signal, and may also include a pause when the first device sends data.

In this embodiment, the manner in which the first device detects the communication abnormality is not limited.

In this embodiment, the generating the termination signal by changing the waveform of the data signal after triggering the IIC bus recovery mechanism may include: and generating a clock signal after the IIC bus recovery mechanism is triggered, changing the waveform of the data signal, constructing a new data signal, and forming a new termination signal by matching the new data signal with the clock signal.

Further, the IIC bus recovery mechanism includes a predetermined number of clock pulses configured by the clock line, and accordingly, the generating of the termination signal by changing the waveform of the data signal after triggering the IIC bus recovery mechanism includes: constructing a preset number of clock pulses as clock signals through the clock lines; changing the waveform of the data signal according to the IIC bus protocol standard; and correspondingly generating a preset number of termination signals by matching the data signals with the changed waveforms with each clock pulse in the clock signals respectively.

The preset number may be a preset number of clock pulses to be configured, and for example, the preset number may be 9, that is, 9 clock pulses may be configured as a clock signal through a clock line.

Fig. 5 is a schematic diagram of pulse contrast according to an embodiment of the present invention. Part (a) in fig. 5 is a pulse signal formed in the prior art, when the master device detects that the SDA data is stuck, the master device triggers the IIC bus recovery mechanism, and the master device controls the SCL to send out 9 CLK clock pulses to form an SCL signal, where the SDA signal maintains a default value of 0; part (b) in fig. 5 is a pulse for forming a termination signal in this embodiment, after the master device detects a communication abnormality, the master device makes the SCL output 9 CLK pulses through the IIC recovery mechanism to construct SDA data, and during the period when the SCL is at a high level, the corresponding SDA transitions from low to high, and at this time, one termination signal is generated, and 9 termination signals can be generated in total.

And S130, sending the termination signal to the second equipment through the clock line so as to enable the IIC bus to recover normal communication.

In this embodiment, the first device sends the termination signal to the second device through the clock line, and the second device can correctly recognize the termination signal after receiving the termination signal, so that false recognition is not caused, and normal communication of the devices is ensured.

The embodiment provides an IIC bus recovery method, which includes the steps that first, after a second device is determined in a plurality of devices, data interaction is performed on the second device through an IIC bus, wherein the IIC bus comprises a data line and a clock line; then when communication abnormality is detected, changing the waveform of a data signal to generate a termination signal after an IIC bus recovery mechanism is triggered, wherein the data signal is sent through the data line; and finally, sending the termination signal to the second equipment through the clock line so as to enable the IIC bus to recover normal communication.

Fig. 6 is a flowchart of an IIC bus recovery method according to an exemplary embodiment of the present invention, as shown in fig. 6, when a master device is stuck in a process of sending a termination signal to a slave device, the master device may enable an SCL to output 9 CLK pulses as a clock signal according to an IIC recovery mechanism, and construct new SDA data, so that the SDA data and the clock signal cooperate to form 9 termination signals. Therefore, the termination signal can not be mistaken for data by the slave device to cause the next register value to be rewritten, the slave device can terminate data interaction with the master device after receiving the termination signal, and the device has no abnormity.

Example two

Fig. 7 is a flowchart of an IIC bus recovery method according to a second embodiment of the present invention, where the method is applicable to a case of performing an IIC bus recovery mechanism when communication is abnormal, and the method may be executed by an IIC bus recovery apparatus, where the apparatus may be implemented by software and/or hardware and is generally integrated on a slave device, and in this embodiment, a master device includes but is not limited to: processors, memory, etc.

As shown in fig. 7, a IIC bus recovery method according to a second embodiment of the present invention includes the following steps:

and S210, performing data interaction with the first equipment through the IIC bus.

In this embodiment, the data interaction may be understood as a process of receiving a register address, receiving data sent by the first device, and receiving a termination signal.

In this embodiment, the process of performing data interaction with the first device may include: the second equipment receives an internal register address of the second equipment to be read or written, which is sent by the first equipment, and the second equipment finds a corresponding register according to the address; the second device receives the data sent by the first device, and the second device writes the data into the register; and the second equipment receives the termination signal sent by the first equipment, and stops data interaction with the first equipment after receiving the termination signal.

S220, when the first equipment detects that the communication is abnormal, receiving a termination signal sent by the first equipment so as to enable the IIC bus to recover normal communication.

The termination signal is generated after the first device changes the waveform of the data signal after triggering the IIC bus recovery mechanism.

In this embodiment, the IIC bus recovery mechanism includes constructing a preset number of clock pulses through the clock line, and accordingly, the generating of the termination signal includes: constructing a preset number of clock pulses as clock signals through the clock lines; changing the waveform of the data signal according to the IIC bus protocol standard; and correspondingly generating a preset number of termination signals by matching the data signals with the changed waveforms with each clock pulse in the clock signals respectively.

The generation process of the termination signal can refer to the explanation of a corresponding part in the embodiments, which is not described herein.

In this embodiment, the second device may correctly identify the termination signal sent by the first device, and may not cause misidentification, so that normal communication of the devices may be ensured.

The second embodiment provides an IIC bus recovery method, which includes performing data interaction with a first device through an IIC bus, and then receiving a termination signal sent by the first device when the first device detects that communication is abnormal, so that the IIC bus recovers normal communication; the method comprises the steps that the first device triggers an IIC bus recovery mechanism, then the waveform of a data signal is changed, the termination signal sent by the first device is received, so that the IIC bus recovers normal communication, the time sequence of the current IIC bus recovery mechanism can be optimized, the error rewriting of a slave device register caused by the defect of the recovery mechanism is avoided, the stability of the IIC bus is improved, and the stability and the safety of the device operation are improved.

EXAMPLE III

Fig. 8 is a schematic structural diagram of an IIC bus recovery apparatus according to a third embodiment of the present invention, which is applicable to a case of IIC bus recovery in case of communication abnormality, where the apparatus may be implemented by software and/or hardware and is generally integrated on a host device.

As shown in fig. 8, the apparatus includes: an interaction module 110, a generation module 120, and a transmission module 130.

The interaction module 110 is configured to perform data interaction with a second device through an IIC bus after the second device is determined among the multiple devices, where the IIC bus includes a data line and a clock line;

a generating module 120, configured to, when a communication abnormality is detected, generate a termination signal by changing a waveform of a data signal after triggering an IIC bus recovery mechanism, where the data signal is sent through the data line;

a sending module 130, configured to send the termination signal to the second device through the clock line, so that the IIC bus resumes normal communication.

In this embodiment, the apparatus first determines a second device among the multiple devices through the interaction module 110, and then performs data interaction with the second device through an IIC bus, where the IIC bus includes a data line and a clock line; then, when the generation module 120 detects that the communication is abnormal, the waveform of the data signal is changed to generate a termination signal after the IIC bus recovery mechanism is triggered, and the data signal is sent through the data line; and finally, the termination signal is sent to the second device through the clock line by the sending module 130, so that the IIC bus recovers normal communication, the device avoids error rewriting of a slave device register caused by the defect of a recovery mechanism, improves the stability of the IIC bus, and further improves the stability and the safety of the operation of the device.

Further, the apparatus further comprises: and the determining module is used for sending the address of the second equipment to the plurality of equipment after sending the starting signal to the second equipment so as to determine the second equipment from the plurality of equipment.

Further, the interaction module 110 is specifically configured to:

sending the register address to a second device so that the second device finds a register according to the register address;

sending data to the second device to cause the second device to write the data to the register;

sending a termination signal to the second device to end data interaction with the second device.

Further, the IIC bus recovery mechanism includes constructing a preset number of clock pulses through the clock line, and correspondingly, the generating module 120 is specifically configured to:

constructing a preset number of clock pulses as clock signals through the clock lines;

changing the waveform of the data signal according to the IIC bus protocol standard;

and correspondingly generating a preset number of termination signals by matching the data signals with the changed waveforms with each clock pulse in the clock signals respectively.

The IIC bus recovery device can execute the IIC bus recovery method provided by any embodiment of the invention, and has corresponding functional modules and beneficial effects of the execution method.

Example four

Fig. 9 is a schematic structural diagram of an IIC bus recovery apparatus according to a fourth embodiment of the present invention, which is applicable to the case of performing IIC bus recovery in case of communication abnormality, where the apparatus may be implemented by software and/or hardware and is generally integrated on a slave device.

As shown in fig. 9, the apparatus includes: an interaction module 210 and a receiving module 220.

The interaction module 210 is configured to perform data interaction with a first device through an IIC bus;

a receiving module 220, configured to receive a termination signal sent by a first device when the first device detects that communication is abnormal, so that the IIC bus resumes normal communication;

In this embodiment, the apparatus performs data interaction with a first device through an IIC bus by an interaction module 210, and then receives a termination signal sent by the first device when the first device detects that communication is abnormal by a receiving module 220, so that the IIC bus recovers normal communication; the device avoids error rewriting of a slave device register caused by the defect of the recovery mechanism, improves the stability of the IIC bus, and further improves the stability and the safety of device operation.

Further, the IIC bus recovery mechanism includes constructing a preset number of clock pulses through a clock line, and correspondingly, the receiving module 220 is specifically configured to:

The IIC bus recovery device can execute the IIC bus recovery method provided by any embodiment of the invention, and has the corresponding functional modules and beneficial effects of the execution method.

EXAMPLE five

Fig. 10 is a schematic structural diagram of an IIC bus recovery system according to a fifth embodiment of the present invention, which is applicable to a case of performing IIC bus recovery when communication is abnormal, and includes a first device according to any embodiment of the present invention, an IIC bus, and a second device according to any embodiment of the present invention.

The IIC bus recovery system provided in the fifth embodiment of the present invention may perform the following steps:

after a second device is determined in the plurality of devices, performing data interaction with the second device through an IIC bus, wherein the IIC bus comprises a data line and a clock line; when communication abnormality is detected, changing the waveform of a data signal to generate a termination signal after an IIC bus recovery mechanism is triggered, wherein the data signal is sent through the data line;

sending the termination signal to the second device over the clock line to restore normal communication to the IIC bus.

The IIC bus recovery system provided by the fifth embodiment of the invention can optimize the time sequence of the current IIC bus recovery mechanism, avoid the error rewriting of the slave device register caused by the defect of the IIC bus recovery mechanism, improve the stability of the IIC bus, and further improve the stability and the safety of the device operation.

Example six

FIG. 11 shows a schematic block diagram of an apparatus 10 that may be used to implement an embodiment of the invention. The device 11 includes a first device and a second device. Devices are intended to represent various forms of digital computers, such as laptops, desktops, workstations, personal digital assistants, servers, blade servers, mainframes, and other appropriate computers. The first device may also represent various forms of mobile devices, such as personal digital assistants, cellular phones, smart phones, wearable devices (e.g., helmets, glasses, watches, etc.), and other similar computing devices. The components shown herein, their connections and relationships, and their functions, are meant to be exemplary only, and are not meant to limit implementations of the inventions described and/or claimed herein.

As shown in fig. 11, the device 10 includes at least one processor 11, and a memory communicatively connected to the at least one processor 11, such as a Read Only Memory (ROM) 12, a Random Access Memory (RAM) 13, and the like, wherein the memory stores a computer program executable by the at least one processor, and the processor 11 may perform various appropriate actions and processes according to the computer program stored in the Read Only Memory (ROM) 12 or the computer program loaded from the storage unit 18 into the Random Access Memory (RAM) 13. In the RAM 13, various programs and data necessary for the operation of the device 10 can also be stored. The processor 11, the ROM12, and the RAM 13 are connected to each other via a bus 14. An input/output (I/O) interface 15 is also connected to bus 14.

A number of components in the device 10 are connected to the I/O interface 15, including: an input unit 16 such as a keyboard, a mouse, or the like; an output unit 17 such as various types of displays, speakers, and the like; a storage unit 18 such as a magnetic disk, an optical disk, or the like; and a communication unit 19 such as a network card, modem, wireless communication transceiver, etc. The communication unit 19 allows the device 10 to exchange information/data with other devices via a computer network, such as the internet, and/or various telecommunication networks.

Processor 11 may be a variety of general and/or special purpose processing components having processing and computing capabilities. Some examples of processor 11 include, but are not limited to, a Central Processing Unit (CPU), a Graphics Processing Unit (GPU), various specialized Artificial Intelligence (AI) computing chips, various processors running machine learning model algorithms, a Digital Signal Processor (DSP), and any suitable processor, controller, microcontroller, or the like. Processor 11 performs the various methods and processes described above, such as an IIC bus recovery method.

In some embodiments, the IIC bus recovery method may be implemented as a computer program tangibly embodied on a computer-readable storage medium, such as storage unit 18. In some embodiments, part or all of the computer program may be loaded and/or installed on the device 10 via the ROM12 and/or the communication unit 19. When the computer program is loaded into RAM 13 and executed by processor 11, one or more steps of the IIC bus recovery method described above may be performed. Alternatively, in other embodiments, the processor 11 may be configured to perform the IIC bus recovery method by any other suitable means (e.g., by means of firmware).

Various implementations of the systems and techniques described here above may be implemented in digital electronic circuitry, integrated circuitry, field Programmable Gate Arrays (FPGAs), application Specific Integrated Circuits (ASICs), application Specific Standard Products (ASSPs), system on a chip (SOCs), load programmable logic devices (CPLDs), computer hardware, firmware, software, and/or combinations thereof. These various embodiments may include: implemented in one or more computer programs that are executable and/or interpretable on a programmable system including at least one programmable processor, which may be special or general purpose, receiving data and instructions from, and transmitting data and instructions to, a storage system, at least one input device, and at least one output device.

Computer programs for implementing the methods of the present invention can be written in any combination of one or more programming languages. These computer programs may be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus, such that the computer programs, when executed by the processor, cause the functions/acts specified in the flowchart and/or block diagram block or blocks to be performed. A computer program can execute entirely on a machine, partly on a machine, as a stand-alone software package partly on a machine and partly on a remote machine or entirely on a remote machine or server.

In the context of the present invention, a computer-readable storage medium may be a tangible medium that can contain, or store a computer program for use by or in connection with an instruction execution system, apparatus, or device. A computer readable storage medium may include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination of the foregoing. Alternatively, the computer readable storage medium may be a machine readable signal medium. More specific examples of a machine-readable storage medium would include an electrical connection based on one or more wires, a portable computer diskette, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

To provide for interaction with a user, the systems and techniques described here can be implemented on a device having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to a user; and a keyboard and a pointing device (e.g., a mouse or a trackball) by which a user may provide input to the device. Other kinds of devices may also be used to provide for interaction with a user; for example, feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user may be received in any form, including acoustic, speech, or tactile input.

The systems and techniques described here can be implemented in a computing system that includes a back-end component (e.g., as a data server), or that includes a middleware component (e.g., an application server), or that includes a front-end component (e.g., a user computer having a graphical user interface or a web browser through which a user can interact with an implementation of the systems and techniques described here), or any combination of such back-end, middleware, or front-end components. The components of the system can be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include: local Area Networks (LANs), wide Area Networks (WANs), blockchain networks, and the internet.

The computing system may include clients and servers. A client and server are generally remote from each other and typically interact through a communication network. The relationship of client and server arises by virtue of computer programs running on the respective computers and having a client-server relationship to each other. The server can be a cloud server, also called a cloud computing server or a cloud host, and is a host product in a cloud computing service system, so that the defects of high management difficulty and weak service expansibility in the traditional physical host and VPS service are overcome.

It should be understood that various forms of the flows shown above may be used, with steps reordered, added, or deleted. For example, the steps described in the present invention may be executed in parallel, sequentially, or in different orders, and are not limited herein as long as the desired results of the technical solution of the present invention can be achieved.

The above-described embodiments should not be construed as limiting the scope of the invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions may be made in accordance with design requirements and other factors. Any modification, equivalent replacement, and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. An IIC bus recovery method, applied to a first device, comprises the following steps:

when communication abnormality is detected, changing the waveform of a data signal to generate a termination signal after an IIC bus recovery mechanism is triggered, wherein the data signal is sent through the data line;

2. The method of claim 1, wherein determining the second device among the plurality of devices comprises:

and after the starting signal is sent to the second equipment, the address of the second equipment is sent to the plurality of equipment so as to determine the second equipment from the plurality of equipment.

3. The method of claim 1, wherein interacting with the second device over the IIC bus comprises:

sending data to the second device to cause the second device to write the data into the register;

and sending a termination signal to the second equipment to end the data interaction with the second equipment.

4. The method of claim 1, wherein the IIC bus recovery mechanism includes constructing a predetermined number of clock pulses via the clock line, and wherein correspondingly, the generating the termination signal by changing a waveform of the data signal after triggering the IIC bus recovery mechanism includes:

5. An IIC bus recovery method, applied to a second device, comprises the following steps:

data interaction is carried out with first equipment through an IIC bus;

when the first equipment detects that the communication is abnormal, receiving a termination signal sent by the first equipment so as to enable the IIC bus to recover normal communication;

6. The method of claim 5, wherein the IIC bus recovery mechanism comprises constructing a predetermined number of clock pulses over a clock line, and wherein the generating of the termination signal comprises:

7. An IIC bus recovery apparatus, applied to a first device, the apparatus comprising:

the interactive module is used for carrying out data interaction with the second equipment through an IIC bus after the second equipment is determined in the plurality of equipment, and the IIC bus comprises a data line and a clock line;

the generating module is used for changing the waveform of a data signal to generate a termination signal after triggering an IIC bus recovery mechanism when the communication is detected to be abnormal, and the data signal is sent through the data line;

8. An IIC bus recovery apparatus, applied to a second device, the apparatus comprising:

the receiving module is used for receiving a termination signal sent by first equipment when the first equipment detects that the communication is abnormal, so that the IIC bus recovers normal communication;

9. A first device, characterized in that the first device comprises:

at least one processor; and

the memory stores a computer program executable by the at least one processor, the computer program being executable by the at least one processor to enable the at least one processor to perform the IIC bus recovery method of any one of claims 1-4.

10. A second device, characterized in that the second device comprises:

at least one processor; and

the memory stores a computer program executable by the at least one processor to enable the at least one processor to perform the IIC bus restoration method of any one of claims 5-6.

11. A computer-readable storage medium having stored thereon computer instructions for causing a processor to execute the IIC bus restoration method of any one of claims 1 to 6.

12. An IIC bus recovery system, comprising a first device as claimed in any one of claims 1 to 4, an IIC bus and a second device as claimed in any one of claims 5 to 6.