CN116500855B

CN116500855B - Mask and semiconductor structure

Info

Publication number: CN116500855B
Application number: CN202310747629.1A
Authority: CN
Inventors: 徐丹; 廖君玮; 刘志拯
Original assignee: Changxin Memory Technologies Inc
Current assignee: Changxin Memory Technologies Inc
Priority date: 2023-06-21
Filing date: 2023-06-21
Publication date: 2023-11-24
Anticipated expiration: 2043-06-21
Also published as: CN116500855A

Abstract

The present disclosure relates to the field of semiconductor technology, and provides a mask and a semiconductor structure. The reticle includes at least one reticle set, the reticle set including: a plurality of sub-masks arranged in an array; each sub-mask is used for forming a corresponding sub-exposure area through a photoetching process, and a first stitching area is arranged between each sub-exposure area and an adjacent sub-exposure area; the mask plate group is used for forming corresponding exposure units through a photoetching process, and a second stitching area is arranged between each exposure unit and each adjacent exposure unit; at least part of the exposure units are internally provided with cutting channel patterns, and at least part of the cutting channel patterns are not in the first stitching region and the second stitching region. The chip is obtained after the cutting channel patterns are used for cutting, the problem that the cutting channel patterns cannot be considered when the stitching region is arranged in the chip and the cutting channel patterns are arranged between the chip can be solved, and meanwhile the cutting channel patterns between the stitching region in the chip and the chip are reserved.

Description

Mask and semiconductor structure

Technical Field

The present disclosure relates to the field of semiconductor technology, and in particular, to a reticle and a semiconductor structure.

Background

For larger area chips, stitching with multiple reticles is required to extend the reticle size limit. Thus, having stitching regions between adjacent reticles, how to provide scribe line patterns for reticles having stitching regions is a challenge to be addressed.

Disclosure of Invention

In view of the foregoing, embodiments of the present disclosure provide a mask and a semiconductor structure.

In order to achieve the above purpose, the technical scheme of the present disclosure is realized as follows:

in a first aspect, embodiments of the present disclosure provide a reticle comprising at least one reticle set comprising:

a plurality of sub-reticles arranged in an array along a first direction and a second direction; wherein the first direction and the second direction are both parallel to the sub-reticle surface and the first direction and the second direction intersect;

each sub-mask is used for forming a corresponding sub-exposure area on the semiconductor layer through a photoetching process, and a first stitching area is arranged between each sub-exposure area and each sub-exposure area adjacent to each other along the first direction and/or the second direction;

the mask plate group is used for forming corresponding exposure units on the semiconductor layer through a photoetching process; the exposure units are arranged in an array along the first direction and the second direction;

A second stitching region is arranged between each exposure unit and each exposure unit adjacent to each other along the first direction and/or the second direction; at least part of the exposure units are provided with cutting channel patterns, and at least part of the cutting channel patterns are not in the first stitching region and the second stitching region.

In some embodiments, the scribe line pattern includes a first overlay mark, a second overlay mark, and a third overlay mark therein; the first overlay mark is located in the first stitching region or the second stitching region, and the second overlay mark and the third overlay mark are not located in the first stitching region and the second stitching region.

In some embodiments, the first overlay mark is used for measuring overlay deviation between sub-exposure areas corresponding to two adjacent sub-reticles on the same layer;

the second overlay mark is used for measuring overlay deviation between sub-exposure areas corresponding to the current layer sub-mask and the front layer sub-mask;

and the third overlay mark is used for measuring overlay deviation between the sub-exposure area corresponding to the sub-mask and the semiconductor layer.

In some embodiments, the first stitched region and the second stitched region comprise an interconnect structure for connecting adjacent two of the sub-exposed regions; wherein the interconnect structure is not within the scribe line pattern.

In some embodiments, the dicing street pattern includes a set of test elements for testing the sub-exposed areas; wherein the set of test elements is not within the first stitched region and the second stitched region.

In some embodiments, each of the sub-reticles is identical in shape and size.

In some embodiments, the first stitched region comprises a first sub-stitched region extending along the first direction; the second stitched region includes a second sub-stitched region extending along the first direction; wherein the first sub-stitched region and the second sub-stitched region are the same size along the second direction;

the first stitched region further comprises a third sub-stitched region extending along the second direction; the second stitched region further comprises a fourth sub-stitched region extending along the second direction; wherein the third sub-stitched region and the fourth sub-stitched region are the same size in the first direction.

In some embodiments, the dimensions of the first sub-stitched region in the second direction, the dimensions of the second sub-stitched region in the second direction, the dimensions of the third sub-stitched region in the first direction, and the dimensions of the fourth sub-stitched region in the first direction are all the same.

In some embodiments, the exposure unit includes four sub-exposure areas arranged in an array along the first direction and the second direction; any three sub-exposure areas in the four sub-exposure areas of the exposure unit have a cutting path pattern, and the rest of the sub-exposure areas do not have a cutting path pattern.

In a second aspect, an embodiment of the present disclosure provides a semiconductor structure, where the semiconductor structure is obtained by performing a photolithography process using the reticle according to the above technical scheme.

The embodiment of the disclosure provides a mask and a semiconductor structure. The reticle includes at least one reticle set, the reticle set including: a plurality of sub-masks arranged in an array; each sub-mask is used for forming a corresponding sub-exposure area through a photoetching process, and a first stitching area is arranged between each sub-exposure area and an adjacent sub-exposure area; the mask plate group is used for forming corresponding exposure units through a photoetching process, and a second stitching area is arranged between each exposure unit and each adjacent exposure unit; at least part of the exposure units are internally provided with cutting channel patterns, and at least part of the cutting channel patterns are not in the first stitching region and the second stitching region. The mask provided by the embodiment of the disclosure has the advantages that the first stitching region is arranged between any two adjacent sub-exposure regions formed on the semiconductor layer through the photoetching process, the second stitching region is arranged between any two adjacent exposure units, at least part of exposure units are provided with the cutting channel patterns, and at least part of cutting channel patterns are not arranged in the first stitching region and the second stitching region. The chip is obtained after the cutting channel patterns are used for cutting, the problem that the cutting channel patterns cannot be considered when the stitching region is arranged in the chip and the cutting channel patterns are arranged between the chip can be solved, and meanwhile the cutting channel patterns between the stitching region in the chip and the chip are reserved.

Drawings

FIG. 1 is a schematic diagram of a reticle provided in an example;

FIG. 2 is a schematic diagram of an exemplary wafer;

fig. 3A is a schematic structural diagram of a reticle provided in an embodiment of the present disclosure;

fig. 3B is a schematic structural diagram of a reticle set according to an embodiment of the disclosure;

FIG. 4A is a schematic diagram of a plurality of exposure units formed after a reticle provided in an embodiment of the present disclosure is subjected to a photolithography process;

fig. 4B is a schematic structural diagram of an exposure unit formed after a mask set according to an embodiment of the present disclosure is subjected to a photolithography process;

FIG. 5A is a schematic diagram of a scribe line pattern in an exposure unit corresponding to a reticle set according to an embodiment of the disclosure;

fig. 5B is a schematic structural diagram of a scribe line pattern in an exposure unit corresponding to a reticle set according to an embodiment of the disclosure;

fig. 5C is a schematic structural diagram III of a scribe line pattern in an exposure unit corresponding to a reticle set according to an embodiment of the disclosure;

fig. 5D is a schematic structural diagram of a scribe line pattern in an exposure unit corresponding to a reticle set according to an embodiment of the disclosure.

Detailed Description

The following description of the embodiments of the present disclosure will be made clearly and fully with reference to the embodiments of the present disclosure and the accompanying drawings, it being apparent that the described embodiments are only some, but not all, of the embodiments of the present disclosure. All other embodiments, which can be made by one of ordinary skill in the art without inventive effort, based on the embodiments in this disclosure are intended to be within the scope of this disclosure.

In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present disclosure. However, it will be apparent to one skilled in the art that the present disclosure may be practiced without one or more of these details. In other instances, well-known features have not been described in order to avoid obscuring the present disclosure; that is, not all features of an actual implementation are described in detail herein, and well-known functions and constructions are not described in detail.

In the drawings, the size of layers, regions, elements and their relative sizes may be exaggerated for clarity. Like numbers refer to like elements throughout.

It will be understood that when an element or layer is referred to as being "on" … …, "" adjacent to "… …," "connected to" or "coupled to" another element or layer, it can be directly on, adjacent to, connected to or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on" … …, "" directly adjacent to "… …," "directly connected to" or "directly coupled to" another element or layer, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present disclosure. When a second element, component, region, layer or section is discussed, it does not necessarily mean that the first element, component, region, layer or section is present in the present disclosure.

Spatially relative terms, such as "under … …," "under … …," "below," "under … …," "above … …," "above," and the like, may be used herein for ease of description to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements or features described as "under" or "beneath" other elements would then be oriented "on" the other elements or features. Thus, the exemplary terms "under … …" and "under … …" may include both an upper and a lower orientation. The device may be otherwise oriented (rotated 90 degrees or other orientations) and the spatially relative descriptors used herein interpreted accordingly.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.

For a thorough understanding of the present disclosure, detailed steps and detailed structures will be presented in the following description in order to illustrate the technical aspects of the present disclosure. Preferred embodiments of the present disclosure are described in detail below, however, the present disclosure may have other implementations in addition to these detailed descriptions.

Before describing embodiments of the present disclosure, two directions describing structures that may be used by embodiments of the present disclosure are defined, and the two directions may include an X direction and a Y direction, each of which is parallel to a sub-reticle surface. It should be noted that a first direction and a second direction intersecting each other may be defined. In some embodiments, the first direction and the second direction may be perpendicular to each other. In other embodiments, the first direction and the second direction may not be perpendicular. In the embodiment of the disclosure, the first direction is defined as the X direction, and the second direction is defined as the Y direction.

Referring to fig. 1 and 2, fig. 1 is a schematic structural diagram of a reticle provided by an example, and fig. 2 is a schematic structural diagram of a wafer provided by an example. The structure of the wafer as illustrated in fig. 2 is formed on the wafer by a photolithography process using the reticle illustrated in fig. 1. As shown in fig. 1, the mask 100 may include, for example, four chip patterns 101 arranged in an array in the X-direction and the Y-direction, and a scribe line pattern 102 located between any adjacent two of the chip patterns 101; the chip pattern 101 may form a chip (Die) on a wafer through a photolithography process, and the Scribe Line pattern 102 may form a Scribe Line (SL) on the wafer through a photolithography process. That is, the size of the reticle is larger than the size of the chip pattern, and one reticle may include a plurality of chip patterns.

Fig. 1 illustrates that one reticle includes four chip patterns, and in practice, the number of chip patterns included in one reticle is not limited thereto.

As shown in fig. 1 and 2, an exposure unit 203 is formed on a wafer 200 by using the mask 100 illustrated in fig. 1 through a photolithography process, wherein after the chip pattern 101 on the mask 100 is formed on the wafer 200 through the photolithography process, chips 201 are correspondingly formed, and four chips 201 are arranged in an array along an X direction and a Y direction; the scribe line pattern 102 on the reticle 100 is subjected to a photolithography process to form a scribe line pattern 202 on the wafer 200, and the scribe line pattern 202 is located between any two adjacent chips 201. The mask 100 illustrated in fig. 1 is used to perform a plurality of photolithography processes, a plurality of exposure units 203 are correspondingly formed on a wafer 200, and a scribe line pattern may be formed between any two adjacent exposure units 203. That is, the size of the exposure unit is larger than the size of the chip, and one exposure unit may include a plurality of chips. More specifically, after one exposure treatment using the mask, a plurality of chips can be formed, and scribe line patterns can be formed between the plurality of chips in the exposure unit and between any two adjacent exposure units.

Fig. 2 illustrates that the exposure unit corresponding to one reticle includes four chips, and in practice, the number of chips included in the exposure unit corresponding to one reticle is not limited thereto.

As described above, the mask correspondingly forms the exposure units on the wafer through the photolithography process, each exposure unit includes a plurality of chips and scribe line patterns located between any two adjacent chips, and the scribe line patterns are used to provide a space for moving the scribe line during the dicing process, and after dicing the wafer, a plurality of chips can be obtained.

However, for forming larger sized chips (i.e., the size of the chip is larger than the size of the reticle), the photolithographic process using only one reticle cannot be completed. At this time, it is necessary to expand the size of the reticle with stitching of a plurality of reticles. Thus, having a stitching region (Stitch) between two adjacent reticles, how to provide a scribe line pattern becomes a challenge for reticles having stitching regions.

In view of the foregoing, embodiments of the present disclosure provide a mask and a semiconductor structure. The mask provided by the embodiment of the disclosure has the advantages that the first stitching region is arranged between any two adjacent sub-exposure regions formed on the semiconductor layer through a photoetching process, the second stitching region is arranged between any two adjacent exposure units, at least part of exposure units are provided with the cutting channel patterns, and at least part of cutting channel patterns are not arranged in the first stitching region and the second stitching region. The chip is obtained after the cutting channel patterns are used for cutting, the problem that the cutting channel patterns cannot be considered when the stitching region is arranged in the chip and the cutting channel patterns are arranged between the chip can be solved, and meanwhile the cutting channel patterns between the stitching region in the chip and the chip are reserved.

Referring to fig. 3A and 3B, fig. 3A is a schematic structural diagram of a reticle provided by an embodiment of the disclosure, and fig. 3B is a schematic structural diagram of a reticle set provided by an embodiment of the disclosure. Fig. 3B is an enlarged schematic view of the first reticle set illustrated in fig. 3A. Referring to fig. 4A and fig. 4B, fig. 4A is a schematic structural diagram of a plurality of exposure units formed by a mask blank according to an embodiment of the disclosure after a photolithography process, and fig. 4B is a schematic structural diagram of an exposure unit formed by a mask blank set according to an embodiment of the disclosure after a photolithography process. The structure of the plurality of exposure units as illustrated in fig. 4A may be formed on the semiconductor layer through a photolithography process using the reticle illustrated in fig. 3A. The structure of the exposure unit as illustrated in fig. 4B may be formed on the semiconductor layer through a photolithography process using the reticle set illustrated in fig. 3B. The reticles provided by embodiments of the present disclosure will be described in detail below in conjunction with fig. 3A, 3B, 4A, and 4B.

As shown in fig. 3A, an embodiment of the present disclosure provides a reticle 300 comprising at least one reticle set; for example, the reticle 300 illustrated in fig. 3A includes four reticle sets (shown by dashed boxes in fig. 3A) arranged in an array, i.e., a first reticle set 301, a second reticle set 302, a third reticle set 303, and a fourth reticle set 304. Taking the first reticle set 301 as an example for illustration, the first reticle set 301 includes: a plurality of sub-masks arranged in an array along the X direction and the Y direction; for example, the first reticle set 301 illustrated in fig. 3A includes four sub-reticles arranged in an array, i.e., a first sub-reticle 311, a second sub-reticle 312, a third sub-reticle 313, and a fourth sub-reticle 314.

It should be noted that, the reticle provided in the embodiments of the present disclosure includes at least one reticle set, for example, the reticle may include four reticle sets, and there is no specific relative positional relationship between the four reticle sets. To facilitate description of the formation of corresponding patterns on the semiconductor layer by a photolithography process using a reticle, more specifically, to facilitate description of the correspondence between the reticle set and the exposure unit, fig. 3A illustrates a reticle 300 including four reticle sets arranged in an array. The relative positional relationship between the four reticle sets illustrated in fig. 3A is only one example that can be implemented, and does not constitute a limitation of the relative positional relationship between the reticle sets provided by the embodiments of the present disclosure.

In the embodiment of the disclosure, the first stitching region 321 is disposed between any two adjacent sub-reticles, that is, the first stitching region 321 is disposed between each sub-reticle and the sub-reticle adjacent in the X-direction and/or the Y-direction. For example, the stitching regions between the first sub-reticle 311 and the second sub-reticle 312, between the first sub-reticle 311 and the third sub-reticle 313, between the third sub-reticle 313 and the fourth sub-reticle 314, and between the second sub-reticle 312 and the fourth sub-reticle 314 are all referred to as first stitching regions 321.

In the embodiment of the disclosure, in the case that a plurality of reticle sets are arranged in an array along the X-direction and the Y-direction, a second stitching region 322 is provided between any two adjacent reticle sets, that is, each reticle set has a second stitching region 322 between each reticle set and the reticle set adjacent along the X-direction and/or the Y-direction. For example, the stitching regions between the first reticle set 301 and the second reticle set 302, between the first reticle set 301 and the third reticle set 303, between the third reticle set 303 and the fourth reticle set 304, and between the second reticle set 302 and the fourth reticle set 304 are all referred to as second stitching regions 322. Of course, the plurality of mask sets may not be arranged in an array, so that any two adjacent mask sets do not have a second stitching region, and the relative positional relationship between the plurality of mask sets in the embodiment of the present disclosure is not particularly limited.

Of course, the number of reticle sets comprised by a reticle may be 2, 3, 4, 5, 6 or even more. The number of reticle sets included in the reticle is not particularly limited in the embodiments of the present disclosure. Of course, the number of sub-reticles included in a reticle set may also be 2, 3, 4, 5, 6 or even more. The number of sub-reticles included in a reticle set is not particularly limited in embodiments of the present disclosure.

As shown in fig. 3A and fig. 4A, each reticle set is used for forming a corresponding exposure unit on a semiconductor layer through a photolithography process, and a plurality of exposure units arranged in an array along an X direction and a Y direction are formed on the semiconductor layer; for example, four exposure units (shown as a dotted line box in fig. 4A), i.e., a first exposure unit 401, a second exposure unit 402, a third exposure unit 403, and a fourth exposure unit 404, are formed on the semiconductor layer illustrated in fig. 4A. Each sub-mask is used for forming a corresponding sub-exposure area on the semiconductor layer through a photoetching process, and each exposure unit comprises a plurality of sub-exposure areas which are arranged in an array along the X direction and the Y direction. Taking the first exposure unit 401 as an example for illustration, the first exposure unit 401 illustrated in fig. 4A includes four sub-exposure areas arranged in an array, i.e., a first sub-exposure area 411, a second sub-exposure area 412, a third sub-exposure area 413, and a fourth sub-exposure area 414.

It should be noted that, whether or not the plurality of reticle sets are arranged in an array along the X direction and the Y direction, the plurality of exposure units formed on the semiconductor layer are arranged in an array along the X direction and the Y direction.

In the embodiment of the present disclosure, the first stitching region 421 is disposed between any two adjacent sub-exposure regions, i.e., each sub-exposure region has the first stitching region 421 disposed between the sub-exposure regions adjacent in the X-direction and/or the Y-direction. For example, the stitched area between the first sub-exposure area 411 and the second sub-exposure area 412, between the first sub-exposure area 411 and the third sub-exposure area 413, between the third sub-exposure area 413 and the fourth sub-exposure area 414, and between the second sub-exposure area 412 and the fourth sub-exposure area 414 is referred to as a first stitched area 421.

It should be noted that, the first sub-mask 311 forms the first sub-exposure region 411 on the semiconductor layer through the photolithography process, and the second sub-mask 312 forms the second sub-exposure region 412 on the semiconductor layer through the photolithography process, that is, the first stitching region 421 between the first sub-exposure region 411 and the second sub-exposure region 412 belongs to the repetitive exposure region, and the number of exposure times of the first stitching region 421 is greater than or equal to two. Similarly, a first stitching region is provided between any two adjacent sub-exposure regions within the exposure unit.

In the embodiment of the present disclosure, the second stitching region 422 is disposed between any two adjacent exposure units, i.e., the second stitching region 422 is disposed between each exposure unit and an adjacent exposure unit along the X-direction and/or the Y-direction. For example, stitched areas between the first exposure unit 401 and the second exposure unit 402, between the first exposure unit 401 and the third exposure unit 403, between the third exposure unit 403 and the fourth exposure unit 404, and between the second exposure unit 402 and the fourth exposure unit 404 are all referred to as second stitched areas 422.

It should be noted that, the first reticle set 301 forms the first exposure unit 401 on the semiconductor layer through the photolithography process, and the second reticle set 302 forms the second exposure unit 402 on the semiconductor layer through the photolithography process, that is, the second stitching region 422 between the first exposure unit 401 and the second exposure unit 402 belongs to the repetitive exposure region, and the number of exposure times of the second stitching region 422 is greater than or equal to two. Similarly, any adjacent exposure units have a second stitching region therebetween.

Note that the stitching region refers to an overlapping region (overlay) between any adjacent two sub-reticles (or sub-exposure regions), or an overlapping region between any adjacent two reticle sets (or exposure units). The number of overlapping layers of the first stitching region between any adjacent two sub-exposure regions and the second stitching region between any adjacent two exposure units is at least two, i.e., the number of exposures of the first stitching region and the second stitching region is at least two.

In the embodiment of the disclosure, each sub-reticle has the same shape and size.

Here, the shape and the size of each sub-reticle are the same, and the shape and the size of a reticle set composed of a plurality of sub-reticles are the same. Correspondingly, the shape and the size of each sub-exposure area are the same, and the shape and the size of each exposure unit are the same.

In the embodiment of the present disclosure, after the exposure processing is performed on the first sub-exposure area 411, the exposure processing may be continuously performed on the second sub-exposure area 412 by moving the first preset value along the positive direction of the X direction, or the exposure processing may be continuously performed on the third sub-exposure area 413 by moving the second preset value along the negative direction of the Y direction. Similarly, after the exposure process is performed on the first exposure unit 401, the exposure process may be continued on the second exposure unit 402 by moving the first preset value in the positive direction of the X direction, or the exposure process may be continued on the third exposure unit 403 by moving the second preset value in the negative direction of the Y direction. There are no empty gaps (i.e., areas where exposure treatment is not required) between the plurality of array-arranged exposure units formed on the semiconductor layer, and there are also no empty gaps (i.e., areas where exposure treatment is not required) between the plurality of array-arranged sub-exposure areas within each exposure unit, that is, the entire surface of the semiconductor layer is seamlessly exposed by the photolithography process.

In a specific example, the semiconductor layer may include a wafer.

The first stitching region between any two adjacent sub-reticles, the second stitching region between any two adjacent reticle sets, the first stitching region between any two adjacent sub-exposure regions, and the second stitching region between any two adjacent exposure units will be described in detail below with reference to fig. 3B and 4B.

In the embodiment of the disclosure, as shown in fig. 3B, the first stitching region 321 between any two adjacent sub-reticles includes a first sub-stitching region 321a extending along the X direction, and the second stitching region 322 between any two adjacent reticle sets includes a second sub-stitching region 322a extending along the X direction; wherein the first sub-stitch area 321a and the second sub-stitch area 322a are the same in size in the Y direction; the first stitching region 321 between any two adjacent sub-reticles further includes a third sub-stitching region 321b extending in the Y-direction, and the second stitching region 322 between any two adjacent reticle sets further includes a fourth sub-stitching region 322b extending in the Y-direction; wherein the third sub-stitch area 321b and the fourth sub-stitch area 322b have the same size in the X direction.

In the embodiment of the present disclosure, as shown in fig. 4B, the first stitching region 421 between any adjacent two sub-exposure regions includes a first sub-stitching region 421a extending in the X direction; the second stitching region 422 between any adjacent two of the exposure units includes a second sub-stitching region 422a extending in the X-direction; wherein the first sub-stitch area 421a and the second sub-stitch area 422a are the same in size in the Y direction; the first stitching region 421 between any adjacent two sub-exposure regions further includes a third sub-stitching region 421b extending in the Y-direction; the second stitching region 422 between any adjacent two of the exposure units further includes a fourth sub-stitching region 422b extending in the Y-direction; wherein the third sub-stitch area 421b and the fourth sub-stitch area 422b have the same dimension in the X direction.

Here, after the exposure process is performed on the first sub-exposure area 411, the exposure process may be continued on the second sub-exposure area 412 by moving a first preset value along the positive direction of the X direction, where the first preset value is the size of the first sub-exposure area 411 along the X direction minus the size of the third sub-stitching area 421b along the X direction; after the second sub-exposure area 412 is exposed, the first preset value may be moved along the positive direction of the X direction to continue the exposure process on the sub-exposure area in the second exposure unit, where the first preset value is the dimension of the second sub-exposure area 412 along the X direction minus the dimension of the fourth sub-stitching area 422b along the X direction. After each exposure treatment is carried out on one sub-exposure area, a first preset value is moved to the next sub-exposure area along the X direction; the distance moved along the X direction is a first preset value each time, namely, the distance moved along the X direction each time is the same. Because only a single moving distance is set, the moving change of the mask plate carrier and the light source in the exposure machine is relatively low, and the photoetching error is reduced.

Here, after the exposure process is performed on the first sub-exposure area 411, the exposure process may be continued on the third sub-exposure area 413 by moving a second preset value along the negative direction of the Y direction, where the second preset value is the dimension of the first sub-exposure area 411 along the Y direction minus the dimension of the first sub-stitching area 421a along the Y direction; after the third sub-exposure area 413 is exposed, a second preset value may be moved along the negative direction of the Y direction to continue the exposure process on the sub-exposure area in the third exposure unit, where the second preset value is the dimension of the third sub-exposure area 413 along the Y direction minus the dimension of the second sub-stitching area 422a along the Y direction. After each exposure treatment is carried out on one sub-exposure area, a second preset value is moved to the next sub-exposure area along the Y direction; the distance moved along the Y direction is a second preset value each time, that is, the distance moved along the Y direction each time is the same.

In the embodiment of the present disclosure, the size of the first sub-stitching region 421a in the Y direction, the size of the second sub-stitching region 422a in the Y direction, the size of the third sub-stitching region 421b in the X direction, and the size of the fourth sub-stitching region 422b in the X direction are the same.

Here, after each exposure treatment is performed on one sub-exposure area, moving a first preset value to the next sub-exposure area along the X direction; after each exposure treatment is carried out on one sub-exposure area, a second preset value is moved to the next sub-exposure area along the Y direction; the first preset value and the second preset value may be the same.

After the exposure process illustrated in fig. 2, a scribe line pattern needs to be maintained between chips, so that dicing can be performed to separate different chips during subsequent processes. However, for larger sized chips, it is necessary to stitch them with multiple sub-reticles. Thus, a plurality of exposure units which are arranged in an array along the X direction and the Y direction are formed on the semiconductor layer, and a second stitching region is arranged between any two adjacent exposure units; each exposure unit comprises a plurality of sub-exposure areas which are arranged in an array along the X direction and the Y direction, a first stitching area is arranged between any two adjacent sub-exposure areas, and the whole surface of the semiconductor layer is exposed in a seamless manner. Then, how to provide the scribe line pattern on the semiconductor layer, that is, how to provide the scribe line pattern between the chip and the stitching region in the chip, is a problem to be solved.

The scribe line pattern 330 of the reticle 300 will be described in detail below with reference to fig. 3A and 3B; and, as shown in fig. 4A and 4B, the scribe line pattern 430 on the semiconductor layer is described in detail.

In the embodiment of the present disclosure, the reticle 300 includes a scribe line pattern 330, and the scribe line pattern 330 forms a scribe line pattern 430 on the semiconductor layer through a photolithography process. Each sub-exposure region includes a first stitched region 421, a second stitched region 422, and other regions (i.e., non-stitched regions) other than the first stitched region 421 and the second stitched region 422. Wherein, the first stitching region 421 and the second stitching region 422 both belong to the repeated exposure region, the exposure times are greater than or equal to two times, the non-stitching region belongs to the single exposure region, and the exposure times are only one time. The scribe line pattern 430 includes a partial scribe line pattern 430 located in the first and second stitched regions 421 and 422 (i.e., located in the repeatedly exposed regions) and a partial scribe line pattern 430 located in the non-stitched region (i.e., located in the single exposed region). In other words, at least part of the scribe line pattern 430 is not within the first and second stitched regions 421 and 422.

In the embodiments of the present disclosure, the scribe line pattern and the first stitched region do not completely coincide on the XY plane, i.e., do not cut along the first stitched region; also, the dicing street pattern and the second stitched area do not completely overlap on the XY plane, i.e., dicing is not performed along the second stitched area. Therefore, the chip is obtained after the cutting channel pattern is used for cutting, the problem that the cutting channel pattern cannot be considered when the stitching region is arranged in the chip and the cutting channel pattern is arranged between the chip can be solved, and meanwhile, the cutting channel pattern between the stitching region in the chip and the chip is reserved.

As shown in fig. 3B, the first reticle set 301 includes four sub-reticles arranged in an array along the X-direction and the Y-direction, that is, a first sub-reticle 311, a second sub-reticle 312, a third sub-reticle 313, and a fourth sub-reticle 314, any three of the four sub-reticles having a scribe line pattern, and the remaining one sub-reticle not having a scribe line pattern. Fig. 3B illustrates that the first sub-reticle 311, the second sub-reticle 312, and the third sub-reticle 313 each have a scribe line pattern, and the fourth sub-reticle 314 does not have a scribe line pattern.

In the disclosed embodiment, the first reticle set 301 includes a first scribe line pattern extending in the X direction and a second scribe line pattern extending in the Y direction; the first and second scribe line patterns may be perpendicular to each other. More specifically, the first scribe line pattern includes a first sub-scribe line pattern 331 located in the first sub-reticle 311 and a third sub-scribe line pattern 333 located in the second sub-reticle 312; the second scribe line pattern includes a second sub-scribe line pattern 332 located in the first sub-reticle 311 and a fourth sub-scribe line pattern 334 located in the third sub-reticle 313.

In the embodiment of the disclosure, as shown in fig. 4B, the first exposure unit 401 includes four sub-exposure areas arranged in an array along the X direction and the Y direction, that is, a first sub-exposure area 411, a second sub-exposure area 412, a third sub-exposure area 413, and a fourth sub-exposure area 414, any three of the four sub-exposure areas have a scribe line pattern, and the remaining one sub-exposure area does not have a scribe line pattern. Fig. 4B illustrates that the first sub-exposure area 411, the second sub-exposure area 412, and the third sub-exposure area 413 each have a scribe line pattern, and the fourth sub-exposure area 414 does not have a scribe line pattern.

In the embodiment of the present disclosure, the first exposure unit 401 includes a first scribe line pattern extending in the X direction and a second scribe line pattern extending in the Y direction; the first and second scribe line patterns may be perpendicular to each other. More specifically, the first scribe line pattern includes a first sub-scribe line pattern 431 located in the first sub-exposure area 411 and a third sub-scribe line pattern 433 located in the second sub-exposure area 412; the second scribe line pattern includes a second sub-scribe line pattern 432 located in the first sub-exposure area 411 and a fourth sub-scribe line pattern 434 located in the third sub-exposure area 413.

Of course, the shapes of the scribe line patterns in the embodiments of the present disclosure are not particularly limited, the first scribe line pattern and the second scribe line pattern may be linear, the first scribe line pattern and the second scribe line pattern may be saw tooth type, and the first scribe line pattern and the second scribe line pattern may be curved; the first and second scribe line patterns may be perpendicular to each other, or the first and second scribe line patterns may be non-perpendicular. Thus, after cutting by the cutting channel pattern, the formed chip is a special-shaped chip.

In some embodiments, the dicing street pattern is used to obtain chips, and the size of the chips may be the same as or different from the size of the exposure unit. The dimensions of the cut chips shown in fig. 4A are the same as the dimensions of the exposure units, and are the sum of the dimensions of the four sub-exposure areas partially overlapped.

It should be noted that, under the condition that the size of the chip is the same as that of the exposure units, a cutting channel pattern is arranged in each exposure unit; in the case where the size of the chip and the size of the exposure unit are different, or in the case where the size of the chip is larger than the size of the exposure unit, a scribe line pattern is provided in a part of the exposure unit.

As previously described, the scribe line pattern 430 includes a partial scribe line pattern 430 located in the first and second stitched regions 421 and 422 (i.e., located in the repeatedly exposed regions) and a partial scribe line pattern 430 located in the non-stitched region (i.e., located in the single exposed region). The first sub-exposure region 411 includes a first sub-slit pattern 431 extending in the X direction and a second sub-slit pattern 432 extending in the Y direction, a portion of the first sub-slit pattern 431 being located in the non-stitching region of the first sub-exposure region 411 and a portion of the first sub-slit pattern 431 being located in the third sub-stitching region 421 b; a portion of the first sub-slit pattern 431 located within the third sub-stitch area 421B is referred to as a first overlap area 441 (shown by a dashed circle in fig. 4B). Wherein, the exposure times of the part of the first sub-slit pattern 431 located in the non-stitching region of the first sub-exposure region 411 are one, and the exposure times of the part of the first sub-slit pattern 431 located in the third sub-stitching region 421b (i.e., the first overlapping region 441) are at least two.

A part of the second sub-slit pattern 432 is located in the non-sewing region of the first sub-exposure region 411 and a part of the second sub-slit pattern 432 is located in the first sub-sewing region 421 a; the portion of the second sub-slit pattern 432 located within the first sub-stitch area 421a is referred to as a second overlap area 442 (as shown by the dashed circle in fig. 4B). Wherein, the exposure times of the partial second sub-slit pattern 432 located in the non-stitching region of the first sub-exposure region 411 are one, and the exposure times of the partial second sub-slit pattern 432 located in the first sub-stitching region 421a (i.e., the second overlap region 442) are at least two.

The second sub-exposure region 412 includes a third sub-slit pattern 433 extending in the X direction, a portion of the third sub-slit pattern 433 being located in the non-stitched region of the second sub-exposure region 412, a portion of the third sub-slit pattern 433 being located in the third sub-stitched region 421b, and a portion of the third sub-slit pattern 433 being located in the fourth sub-stitched region 422 b; the portion of the third sub-slit pattern 433 located within the third sub-stitch region 421B is referred to as a third overlap region 443 (shown by the dotted circle in fig. 4B), and the portion of the third sub-slit pattern 433 located within the fourth sub-stitch region 422B is referred to as a fourth overlap region 444 (shown by the dotted circle in fig. 4B). Wherein the number of times of exposure of the portion of the third sub-slit pattern 433 located in the non-stitch region of the second sub-exposure region 412 is one, and the number of times of exposure of the portion of the third sub-slit pattern 433 located in the third sub-stitch region 421b (i.e., the third stitch region 443) and the portion of the third sub-slit pattern 433 located in the fourth sub-stitch region 422b (i.e., the fourth stitch region 444) is at least two.

The third sub-exposure region 413 includes a fourth sub-slit pattern 434 extending in the Y direction, a portion of the fourth sub-slit pattern 434 being located in the non-stitched region of the third sub-exposure region 413, a portion of the fourth sub-slit pattern 434 being located in the first sub-stitched region 421a, and a portion of the fourth sub-slit pattern 434 being located in the second sub-stitched region 422 a; the portion of the fourth sub-slit pattern 434 located within the first sub-stitch area 421a is referred to as a fifth overlap area 445 (as shown by the dashed circle in fig. 4B), and the portion of the fourth sub-slit pattern 434 located within the second sub-stitch area 422a is referred to as a sixth overlap area 446 (as shown by the dashed circle in fig. 4B).

Note that, the orthographic projections of the first overlapping region 441 and the third overlapping region 443 on the XY plane illustrated in fig. 4B overlap, and the orthographic projections of the second overlapping region 442 and the fifth overlapping region 445 on the XY plane overlap.

In the embodiment of the disclosure, the number of exposure times of the scribe line pattern in the non-stitched area of the sub-exposure areas is one, and the number of exposure times of the scribe line pattern in the first stitched area between the sub-exposure areas and the second stitched area between the exposure units is at least two.

Referring to fig. 5A to 5D, fig. 5A to 5D are schematic structural diagrams of a scribe line pattern in an exposure unit corresponding to a reticle set according to an embodiment of the disclosure, respectively. The structure of the scribe line patterns in the exposure units corresponding to the reticle set will be described in detail with reference to fig. 5A to 5D.

As shown in fig. 5A, the first sub-exposure region 411 and the second sub-exposure region 412 are juxtaposed in the X direction, the third sub-exposure region 413 and the fourth sub-exposure region 414 are juxtaposed in the X direction, the first sub-exposure region 411 and the third sub-exposure region 413 are juxtaposed in the Y direction, and the second sub-exposure region 412 and the fourth sub-exposure region 414 are juxtaposed in the Y direction; wherein the first sub-exposure area 411, the second sub-exposure area 412, the third sub-exposure area 413 and the fourth sub-exposure area 414 together form the first exposure unit 401. The first sub-exposure area 411 is located at the upper left of the first exposure unit 401, the second sub-exposure area 412 is located at the upper right of the first exposure unit 401, the third sub-exposure area 413 is located at the lower left of the first exposure unit 401, and the fourth sub-exposure area 414 is located at the lower right of the first exposure unit 401. In other words, the second sub-exposure region 412 is located in the positive direction of the X direction of the first sub-exposure region 411, and the third sub-exposure region 413 is located in the negative direction of the Y direction of the first sub-exposure region 411; the second sub-exposure region 412 is located in the positive direction of the Y direction of the fourth sub-exposure region 414, and the third sub-exposure region 413 is located in the negative direction of the X direction of the fourth sub-exposure region 414.

The first sub-exposure region 411 includes a first sub-slit pattern 431 extending in the X direction and a second sub-slit pattern 432 extending in the Y direction; the first sub-scribe line pattern 431 and the second sub-scribe line pattern 432 may be perpendicular to each other. The second sub-exposure region 412 includes a third sub-scribe line pattern 433 extending in the X direction; wherein the first sub-scribe line pattern 431 and the third sub-scribe line pattern 433 extending in the X direction may collectively form a scribe line pattern extending in the X direction. The third sub-exposure region 413 includes a fourth sub-scribe line pattern 434 extending in the Y direction; wherein the second sub-scribe line pattern 432 and the fourth sub-scribe line pattern 434 extending in the Y direction may collectively form a scribe line pattern extending in the Y direction. The fourth sub-exposure area 414 does not have a scribe line pattern. Here, the scribe line patterns in the exposure unit formed by the first sub-exposure region 411, the second sub-exposure region 412, the third sub-exposure region 413, and the fourth sub-exposure region 414 together exhibit a cross shape, and an intersection point between the scribe line pattern extending in the X direction and the scribe line pattern extending in the Y direction is located in the first sub-exposure region 411.

As shown in fig. 5B, the second sub-exposure region 412 and the first sub-exposure region 411 are juxtaposed in the X direction, the fourth sub-exposure region 414 and the third sub-exposure region 413 are juxtaposed in the X direction, the second sub-exposure region 412 and the fourth sub-exposure region 414 are juxtaposed in the Y direction, and the first sub-exposure region 411 and the third sub-exposure region 413 are juxtaposed in the Y direction; wherein the first sub-exposure area 411, the second sub-exposure area 412, the third sub-exposure area 413 and the fourth sub-exposure area 414 together form the first exposure unit 401. The first sub-exposure area 411 is located at the upper right of the first exposure unit 401, the second sub-exposure area 412 is located at the upper left of the first exposure unit 401, the third sub-exposure area 413 is located at the lower right of the first exposure unit 401, and the fourth sub-exposure area 414 is located at the lower left of the first exposure unit 401. In other words, the first sub-exposure region 411 is located in the positive direction of the X direction of the second sub-exposure region 412, and the fourth sub-exposure region 414 is located in the negative direction of the Y direction of the second sub-exposure region 412; the first sub-exposure area 411 is located in the positive direction of the Y direction of the third sub-exposure area 413, and the fourth sub-exposure area 414 is located in the negative direction of the X direction of the third sub-exposure area 413.

The arrangement of the first, second, third, and fourth sub-exposure regions 411, 412, 413, and 414 illustrated in fig. 5B and the arrangement of the first, second, third, and fourth sub-exposure regions 411, 412, 413, and 414 illustrated in fig. 5A are axisymmetric along the symmetry axis of the Y direction. The scribe line pattern illustrated in fig. 5B and the scribe line pattern illustrated in fig. 5A are axisymmetric along the symmetry axis in the Y direction.

As shown in fig. 5C, the fourth sub-exposure region 414 and the third sub-exposure region 413 are juxtaposed in the X direction, the second sub-exposure region 412 and the first sub-exposure region 411 are juxtaposed in the X direction, the fourth sub-exposure region 414 and the second sub-exposure region 412 are juxtaposed in the Y direction, and the third sub-exposure region 413 and the first sub-exposure region 411 are juxtaposed in the Y direction; wherein the first sub-exposure area 411, the second sub-exposure area 412, the third sub-exposure area 413 and the fourth sub-exposure area 414 together form the first exposure unit 401. The first sub-exposure area 411 is located at the lower right of the first exposure unit 401, the second sub-exposure area 412 is located at the lower left of the first exposure unit 401, the third sub-exposure area 413 is located at the upper right of the first exposure unit 401, and the fourth sub-exposure area 414 is located at the upper left of the first exposure unit 401. In other words, the third sub-exposure region 413 is located in the positive direction of the X direction of the fourth sub-exposure region 414, and the second sub-exposure region 412 is located in the negative direction of the Y direction of the fourth sub-exposure region 414; the third sub-exposure region 413 is located in the positive direction of the Y direction of the first sub-exposure region 411, and the second sub-exposure region 412 is located in the negative direction of the X direction of the first sub-exposure region 411.

The arrangement of the first, second, third, and fourth sub-exposure regions 411, 412, 413, and 414 illustrated in fig. 5C and the arrangement of the first, second, third, and fourth sub-exposure regions 411, 412, 413, and 414 illustrated in fig. 5B are axisymmetric along the symmetry axis of the X direction. The scribe line pattern illustrated in fig. 5C and the scribe line pattern illustrated in fig. 5B are axisymmetric along the symmetry axis of the X direction.

As shown in fig. 5D, the third sub-exposure region 413 and the fourth sub-exposure region 414 are juxtaposed in the X direction, the first sub-exposure region 411 and the second sub-exposure region 412 are juxtaposed in the X direction, the first sub-exposure region 411 and the third sub-exposure region 413 are juxtaposed in the Y direction, and the second sub-exposure region 412 and the fourth sub-exposure region 414 are juxtaposed in the Y direction; wherein the first sub-exposure area 411, the second sub-exposure area 412, the third sub-exposure area 413 and the fourth sub-exposure area 414 together form the first exposure unit 401. The first sub-exposure area 411 is located at the lower left of the first exposure unit 401, the second sub-exposure area 412 is located at the lower right of the first exposure unit 401, the third sub-exposure area 413 is located at the upper left of the first exposure unit 401, and the fourth sub-exposure area 414 is located at the upper right of the first exposure unit 401. In other words, the fourth sub-exposure region 414 is located in the positive direction of the X direction of the third sub-exposure region 413, and the first sub-exposure region 411 is located in the negative direction of the Y direction of the third sub-exposure region 413; the fourth sub-exposure region 414 is located in the positive direction of the Y direction of the second sub-exposure region 412, and the first sub-exposure region 411 is located in the negative direction of the X direction of the second sub-exposure region 412.

The arrangement of the first, second, third, and fourth sub-exposure regions 411, 412, 413, and 414 illustrated in fig. 5D and the arrangement of the first, second, third, and fourth sub-exposure regions 411, 412, 413, and 414 illustrated in fig. 5C are axisymmetric along the symmetry axis of the Y direction. The scribe line pattern illustrated in fig. 5D and the scribe line pattern illustrated in fig. 5C are axisymmetric along the symmetry axis of the Y direction.

In the embodiment of the disclosure, overlay marks (Overlay Mark) may be disposed in the scribe line pattern, and in the process of processing the semiconductor layer to form the semiconductor structure, alignment is required by using the Overlay marks, and after the semiconductor structure is formed, the semiconductor structure may be cut through the scribe line pattern without retaining the Overlay marks.

In an embodiment of the disclosure, the scribe line pattern may include a first overlay mark, where the first overlay mark is located in the first stitching region or the second stitching region; the first overlay mark is used for measuring overlay deviation between sub-exposure areas corresponding to two adjacent sub-masks on the same layer.

Here, there is a first stitched region (or a second stitched region) between two adjacent sub-reticles (or two adjacent reticle sets) located on the same layer, and then alignment is required between the two adjacent sub-reticles (or two adjacent reticle sets) located on the same layer. Correspondingly, a first stitching region (or a second stitching region) is located between two adjacent sub-exposure regions (or two adjacent exposure units) of the same layer, and then alignment is required between the two adjacent sub-exposure regions (or two adjacent exposure units) of the same layer.

In embodiments of the present disclosure, the first overlay mark (i.e., the same layer overlay mark) may be located within the scribe line pattern, and the first overlay mark is located within the first stitching region or the second stitching region. For example, as shown in fig. 3B and 4B, a first sub-exposure region 411 may be formed on the semiconductor layer using the first sub-reticle 311, and a first overlay mark may be formed in the first sub-exposure region 411 of the semiconductor layer, where the first overlay mark may be located in the first overlap region 441; a second sub-exposure region 412 may also be formed on the semiconductor layer using the second sub-reticle 312, and a first overlay mark may also be formed in the second sub-exposure region 412 of the semiconductor layer, where the first overlay mark may be located in the third overlay region 443; by measuring the overlay deviation between the first overlay mark located in the first overlap region 441 and the first overlay mark located in the third overlap region 443, the overlay deviation between the first sub-exposure region 411 and the second sub-exposure region 412 can be obtained. In embodiments of the present disclosure, the first overlay mark may be located within the repeatedly exposed region of the scribe line pattern.

In an embodiment of the disclosure, the scribe line pattern may further include a second overlay mark, where the second overlay mark is not in the first and second stitching regions; the second overlay mark is used for measuring overlay deviation between the sub-mask plate of the current layer and the sub-exposure area corresponding to the sub-mask plate of the front layer.

Here, alignment is required between the front layer sub-reticle (or front layer reticle set) and the current layer sub-reticle (or current layer reticle set). Correspondingly, alignment is also required between the front layer sub-exposure area (or front layer exposure unit) and the layer sub-exposure area (or layer exposure unit). Because the second overlay mark is not in the stitching region, the second overlay mark is only exposed for a single time, deformation of the overlay mark caused by multiple exposure is avoided, and the alignment precision is improved.

In embodiments of the present disclosure, the second overlay mark (i.e., the front layer overlay mark) may be located within the scribe line pattern, and the second overlay mark is not located within the first stitched region and the second stitched region, i.e., the second overlay mark is located within the non-stitched region of the scribe line pattern. For example, a first sub-exposure region of the front layer may be formed on the semiconductor layer using a first sub-mask of the front layer, and a second overlay mark may be formed in the first sub-exposure region of the front layer of the semiconductor layer, where the second overlay mark may be located in a non-stitched region of the first sub-exposure region of the front layer; a first sub-exposure area of the current layer can be formed on the semiconductor layer by using the first sub-mask of the current layer, and a second overlay mark is also formed in the first sub-exposure area of the current layer of the semiconductor layer, wherein the second overlay mark can be positioned in a non-stitching area of the first sub-exposure area of the current layer; by measuring the overlay deviation between the second overlay mark located in the first sub-exposure area of the front layer and the second overlay mark located in the first sub-exposure area of the current layer, the overlay deviation between the first sub-exposure area of the front layer and the first sub-exposure area of the current layer can be obtained.

In the embodiment of the disclosure, since the second overlay mark is formed in the first sub-exposure area of the front layer, that is, the second overlay mark is formed on the semiconductor layer before the first sub-exposure area of the front layer is formed, the second overlay mark is disposed in the non-stitched area of the scribe line pattern. For example, as shown in fig. 4B, the second overlay mark may be located at other areas of the first sub-slit pattern 431 and the second sub-slit pattern 432 of the first sub-exposure area 411 than the first overlapping area 441 and the second overlapping area 442. In embodiments of the present disclosure, the second overlay mark may be located within a single exposure region of the scribe line pattern.

In an embodiment of the disclosure, the scribe line pattern may further include a third overlay mark, where the third overlay mark is not in the first and second stitching regions; the third overlay mark is used for measuring overlay deviation between the sub-exposure area corresponding to the sub-mask and the semiconductor layer.

Here, alignment is required between the sub-reticle (or reticle set) and the semiconductor layer. Correspondingly, alignment is also required between the sub-exposure area (or exposure unit) and the semiconductor layer. The third overlay Mark may also be referred to as an Alignment Mark (Alignment Mark).

In an embodiment of the disclosure, the third overlay mark may be located within the scribe line pattern, and the third overlay mark is not located within the first and second stitched regions, i.e., the third overlay mark is located within the non-stitched region of the scribe line pattern. For example, a third overlay mark has been formed on the semiconductor layer, a first sub-exposure region may be formed on the semiconductor layer using the first sub-reticle, and the third overlay mark may be formed in the first sub-exposure region of the semiconductor layer, where the third overlay mark may be located in a non-stitching region of the first sub-exposure region; by measuring the overlay deviation between the third overlay mark on the semiconductor layer and the third overlay mark located in the first sub-exposure area, the overlay deviation between the first sub-exposure area and the semiconductor layer can be obtained.

In the embodiment of the disclosure, since the third overlay mark is already formed on the semiconductor layer, that is, before the first sub-exposure region is formed, the third overlay mark is already formed on the semiconductor layer, and therefore, the third overlay mark may be disposed in the non-stitched region of the scribe line pattern. For example, as shown in fig. 4B, the third overlay mark may be located at other areas of the first sub-slit pattern 431 and the second sub-slit pattern 432 of the first sub-exposure area 411 than the first overlapping area 441 and the second overlapping area 442. In embodiments of the present disclosure, the third overlay mark may be located within a single exposure region of the scribe line pattern.

In embodiments of the present disclosure, the first stitched region and the second stitched region may include an interconnect structure for connecting adjacent two sub-exposed regions; wherein the interconnect structure is not within the scribe line pattern.

Here, the size limit of the sub-reticle may be expanded with a plurality of sub-reticle stitching. For example, as shown in fig. 3A and fig. 4A, four sub-masks arranged in an array along the X-direction and the Y-direction are used to form four corresponding sub-exposure areas through a photolithography process, and adjacent sub-exposure areas need to be connected through an interconnection structure. Wherein, two adjacent sub-exposure areas can belong to the same exposure unit or can belong to different exposure units.

In the embodiment of the disclosure, the interconnection structure may be located in the first stitching region and the second stitching region, and the interconnection structure is not located in the dicing lane pattern, i.e., the interconnection structure is located in other regions than the dicing lane pattern in the first stitching region and the second stitching region. For example, as shown in fig. 3B and 4B, the first sub-exposure region 411 may be formed on the semiconductor layer using the first sub-reticle 311, and an interconnection structure may be formed in the third sub-stitching region 421B of the first sub-exposure region 411 of the semiconductor layer, in which case the interconnection structure may be located in other regions than the first sub-dicing street pattern 431 in the third sub-stitching region 421B; a second sub-exposure region 412 may be formed on the semiconductor layer using the second sub-reticle 312, and an interconnection structure may be formed in a third sub-stitch region 421b of the second sub-exposure region 412 of the semiconductor layer, in which case the interconnection structure may be located in other regions than the third sub-scribe line pattern 433 in the third sub-stitch region 421 b; the connection between the adjacent first sub-exposure region 411 and second sub-exposure region 412 may be achieved by the interconnection structure located in the other region than the first sub-slit pattern 431 within the third sub-stitch region 421b and the interconnection structure located in the other region than the third sub-slit pattern 433 within the third sub-stitch region 421 b.

In an embodiment of the present disclosure, a test element group (Test Element Group, TEG) may be further included in the scribe line pattern, the test element group being used to test the sub-exposure area; wherein the test element group is not in the first stitching region and the second stitching region.

Here, a test element group pattern is set in the scribe line pattern of the sub-reticle, which forms a test element group in the sub-exposure region by a photolithography process; wherein the set of test elements may comprise various test elements. After processing the semiconductor layer to form a semiconductor structure, the semiconductor structure may be tested, e.g., electrically, by a set of test elements located within the scribe line pattern. A probe card having a plurality of probes may be used to make pin contacts to test elements among the test elements to measure electrical characteristics of the test elements, and finally confirm whether the manufacturing process of the semiconductor structure is normal or meets design requirements. After the test is completed, dicing can be performed through the dicing street pattern without leaving the test element groups.

In the disclosed embodiments, the test element group may be located within the scribe line pattern, and the test element group is not located within the first and second stitched regions, i.e., the test element group is located within the non-stitched region of the scribe line pattern. For example, as shown in fig. 3B and 4B, a first sub-exposure region 411 may be formed on the semiconductor layer using the first sub-reticle 311, and a test element group may be formed in the first sub-exposure region 411, in which case the test element group may be located in a non-stitched region of the first sub-exposure region 411. Wherein, the test element group may be located in other areas of the first sub-slit pattern 431 and the second sub-slit pattern 432 of the first sub-exposure area 411 than the first overlapping area 441 and the second overlapping area 442. In embodiments of the present disclosure, the set of test elements may be located within a single exposure area of the scribe line pattern.

It should be noted that the test element group may also be located in a repeatedly exposed region of the scribe line pattern, for example, a first stitched region between two adjacent sub-exposed regions or a second stitched region between two adjacent exposed units. Even if the test element group pattern is located in the first stitching region or the second stitching region of the sub-reticle, repeated exposure of the test element group pattern needs to be avoided, so that damage to the test element group is avoided, for example, a manner of depositing a barrier layer may be used. Specifically, when the test element group pattern is located in the first stitching region between the first sub-reticle and the second sub-reticle, after the first sub-exposure region is formed on the semiconductor layer by using the first sub-reticle, before the second sub-exposure region is formed on the semiconductor layer by using the second sub-reticle, a barrier layer may be formed on the formed test element group, and after the barrier layer is formed, the second sub-exposure region is formed on the semiconductor layer by using the second sub-reticle. Therefore, the blocking layer can block the light in the process of forming the second sub-exposure area, and the problem of repeated exposure is avoided.

The embodiment of the disclosure also provides a semiconductor structure, which is obtained by carrying out a photoetching process on the mask plate in the technical scheme.

Here, a plurality of exposure units arranged in an array along an X direction and a Y direction are formed on a semiconductor layer through a photolithography process using the mask provided by the embodiment of the present disclosure, each exposure unit including a plurality of sub-exposure regions arranged in an array along the X direction and the Y direction; wherein, a first stitching region is arranged between each sub-exposure region and the sub-exposure region adjacent to each other along the X direction and the Y direction, and a second stitching region is arranged between each exposure unit and the exposure unit adjacent to each other along the X direction and the Y direction; a scribe line pattern is also formed on the semiconductor layer, at least a portion of the exposure unit having the scribe line pattern therein, and at least a portion of the scribe line pattern not being in the first and second stitching regions. And cutting by using the cutting channel pattern to obtain a chip, wherein a first sewing region and a second sewing region are arranged in the chip.

In some embodiments, the semiconductor layer may be a wafer, sub-exposure regions (or exposure units) are formed on the wafer by a photolithography process using a sub-reticle (or reticle set), and dicing is performed along the dicing street pattern to obtain a plurality of chips. The mask provided by the embodiment of the disclosure can be used for forming a chip with a larger area.

In other embodiments, the semiconductor layer may be an interposer, and the target pattern may be formed on the interposer by a photolithography process using a reticle. The mask provided by the embodiment of the disclosure can be used for forming an interposer with a larger area. Here, the interposer may include through silicon vias (Through Silicon Via, TSV) and rewiring layers (Redistribution Layer, RDL).

It should be appreciated that reference throughout this specification to "one embodiment" or "an embodiment" means that a particular feature, structure or characteristic described in connection with the embodiment is included in at least one embodiment of the present disclosure. Thus, the appearances of the phrases "in one embodiment" or "in an embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. It should be understood that, in various embodiments of the present disclosure, the sequence numbers of the foregoing processes do not mean the order of execution, and the order of execution of the processes should be determined by their functions and internal logic, and should not constitute any limitation on the implementation of the embodiments of the present disclosure. The foregoing embodiment numbers of the present disclosure are merely for description and do not represent advantages or disadvantages of the embodiments.

The foregoing description is only of the preferred embodiments of the present disclosure, and is not intended to limit the scope of the present disclosure, but rather, the equivalent structural changes made by the present disclosure and the accompanying drawings under the inventive concept of the present disclosure, or the direct/indirect application in other related technical fields are included in the scope of the present disclosure.

Claims

1. A reticle, the reticle comprising at least one reticle set, the reticle set comprising:

each sub-mask is used for forming a corresponding sub-exposure area on the semiconductor layer through a photoetching process, and a first stitching area is arranged between each sub-exposure area and each sub-exposure area adjacent to each other along the first direction and/or the second direction; an overlapping region between each of the sub-exposure regions and a sub-exposure region adjacent in the first direction and/or the second direction forms the first stitched region;

a second stitching region is arranged between each exposure unit and each exposure unit adjacent to each other along the first direction and/or the second direction; an overlapping region between the exposure units and the exposure units adjacent in the first direction and/or the second direction forms the second stitching region; wherein at least part of the exposure units are provided with cutting channel patterns, and at least part of the cutting channel patterns are not in the first stitching region and the second stitching region; and the size of a chip formed after cutting along the cutting path pattern is larger than or equal to that of the exposure unit.

2. The reticle of claim 1, wherein the scribe line pattern includes a first overlay mark, a second overlay mark, and a third overlay mark therein; the first overlay mark is located in the first stitching region or the second stitching region, and the second overlay mark and the third overlay mark are not located in the first stitching region and the second stitching region.

3. The reticle of claim 2, wherein the first overlay mark is configured to measure overlay deviation between sub-exposure areas corresponding to two adjacent sub-reticles on the same layer;

4. The reticle of claim 1, wherein the first stitched region and the second stitched region comprise an interconnect structure for connecting adjacent two of the sub-exposed regions; wherein the interconnect structure is not within the scribe line pattern.

5. The reticle of claim 1, wherein the scribe line pattern includes a set of test elements therein for testing the sub-exposed regions; wherein the set of test elements is not within the first stitched region and the second stitched region.

6. The reticle of claim 1, wherein each of the sub-reticles is identical in shape and size.

7. The reticle of claim 6, wherein the first stitched region comprises a first sub-stitched region extending along the first direction; the second stitched region includes a second sub-stitched region extending along the first direction; wherein the first sub-stitched region and the second sub-stitched region are the same size along the second direction;

8. The reticle of claim 7, wherein a dimension of the first sub-stitch region in the second direction, a dimension of the second sub-stitch region in the second direction, a dimension of the third sub-stitch region in the first direction, and a dimension of the fourth sub-stitch region in the first direction are all the same.

9. The reticle of claim 1, wherein the exposure unit comprises four sub-exposure regions arranged in an array along the first direction and the second direction; any three sub-exposure areas in the four sub-exposure areas of the exposure unit have a cutting path pattern, and the rest of the sub-exposure areas do not have a cutting path pattern.

10. A semiconductor structure obtained by performing a lithographic process with a reticle according to any one of claims 1 to 9.