CN116500573A - Four-path parallel SAR imaging data transposition system based on DDR SDRAM - Google Patents

Abstract

The invention discloses a four-path parallel SAR imaging data transposition system based on DDR SDRAM. The invention divides the data matrix into 4X 4 small matrix blocks for data processing, so that the 4 beats of data processed in the distance direction and the 4 beats of data processed in the azimuth direction are just the same 4X 4 matrix, and the invention mainly solves the problems of more DDR line feed times, low efficiency and large RAM cache requirement during 4-path parallel processing. The implementation steps are as follows: writing the sequentially-entered original data into the DDR SDRAM memory in a block storage mode; the data read out by the asynchronous FIFO are stored into the RAM after passing through the shift register for three times to obtain 4 small matrix blocks with the size of 4 multiplied by 4 for distance data processing; writing the data of each 4×4 small matrix block into the DDR SDRAM memory by a serial-parallel conversion module and an asynchronous FIFO again in a block storage mode; each data read out through the asynchronous FIFO is just a small 4 x 4 matrix block, which is stored in RAM and then processed in azimuth.

Description

Four-path parallel SAR imaging data transposition system based on DDR SDRAM

Technical Field

The invention belongs to the field of radar imaging signal processing, and particularly relates to a system for rapidly transposing four paths of parallel data in radar imaging signal processing.

Background

The synthetic aperture radar (Synthetic Aperture Radar, SAR) has all-weather working characteristics and high-resolution imaging precision all over the day, and has a great effect on the aspects of remote sensing and mapping in cloudy and foggy areas, military reconnaissance, national economy construction and the like. In recent years, with rapid development of hardware manufacturing level, SAR real-time imaging system design is receiving more and more research. The SAR imaging signal processing process involves the transmission and storage of large data volume, and the transposition efficiency directly relates to the speed of SAR imaging signal processing because the access of data in the imaging processing process needs to be switched between distance dimension and azimuth dimension.

The advantages of large memory capacity, high speed, low power consumption, low cost and the like of the current DDR SDRAM (double rate synchronous dynamic random access memory) are increasingly applied to SAR imaging signal processing. In the SAR imaging processing system based on DDR SDRAM, there is a two-page or three-page transposition method in the previous study, which implements matrix transposition by circularly accessing two or three pieces of SDRAM. The paper published by Nanjing institute of electronic technology Wu Qinwen, which is a high-efficiency matrix transposition method based on FPGA and DDR, disassembles data from row dimensions, and arranges the original row data into a new small matrix so as to balance the read-write efficiency. The paper published by the western electronic engineering institute Liu Chen et al, CTM algorithm and implementation based on DDR SDRAM, proposes the fastest column reading matrix transposition algorithm, firstly receives two azimuth data, and alternately amalgamates and writes the two azimuth data into DDR SDRAM. The transposition methods in the above documents are designed for one path of data processing system, and data is input to corresponding sub-modules in rows or columns, however, in some imaging algorithm flows, multiple data transposition is required, and in FPGA-based implementations, multiple parallel data processing designs are often adopted, which also results in that data cannot be input to corresponding sub-modules in rows or columns any more during the data processing process.

Disclosure of Invention

The invention mainly aims at the problems that the reading and writing efficiency is low and a large amount of RAM (random access memory) is required to buffer redundant data when parallel data are processed by adopting a traditional transfer scheme, optimizes the transposition scheme, and greatly reduces the operations of RAM buffer and line changing and column changing by decomposing echo data into 4X 4 data matrixes for processing, thereby greatly improving the operation efficiency of the system.

The implementation technical scheme of the invention is as follows:

the four-path parallel SAR imaging data transposition system based on the DDR SDRAM comprises a distance data processing module and an azimuth data processing module, wherein the distance data processing module comprises a first DDR SDRAM, a first asynchronous FIFO, a shift register group, a first RAM group and a distance data processing unit;

the first DDR SDRAM is used for receiving radar echo data, the burst length of the first DDR SDRAM is 8, the data bit width is 64 bits, the radar echo data bit width is 32 bits, a matrix with the radar echo data of 8192 multiplied by 8192 is defined, the radar echo data is written into the first DDR SDRAM in a block storage mode, each row of the radar echo data is averagely divided into 512 parts, each part is 16 32bit numbers, namely 512bits, and the 512bit data written in each time occupies 8 address spaces of the first DDR SDRAM, and the method comprises the following steps: writing the first row of data from address 0, and writing 16 32-bit data at intervals of 32 addresses; then, the second row of data starts from the address 8, and then 16 32bit numbers are written into every 32 addresses; then, starting the third row of data from the address 16, and then writing 16 32 bits of data into the memory every 32 addresses; finally, starting the fourth row of data from the address 24, and then writing 16 32 bits at intervals of 32 addresses; the addresses 0-16383 of the first DDR SDRAM are fully written; writing 4 rows each time in the same sequence until all radar echo data are written;

the first asynchronous FIFO is used for sequentially reading data in the first DDR SDRAM, and specifically comprises the following steps: first the first 16 data of the first row are read out, then the first 16 data of the second row are read out, then the first 16 data of the third row are read out, then the first 16 data of the fourth row are read out; then, the 17 th to 32 th data of the first row are read out, and the data are sequentially read out in this order;

the data read out by the first asynchronous FIFO sequentially pass through a shift register group, wherein the shift register group comprises 3 shift registers with 512bits, and the data passing through the shift register group is stored into a first RAM group, specifically: writing the current output of the 3 shift registers with 512bits and the asynchronous FIFO every four register processing clocks, namely 16 columns of data of four lines into 64 32-bit RAMs;

the first RAM group comprises 64 32-bit RAMs, the data stored in the RAMs are 4 rows and 16 columns of 32-bit data each time, the data are 4 matrix blocks of 4 multiplied by 4, and each clock reads out the same column data input distance of four rows of data from the first RAM group and processes the data to the data processing unit;

the azimuth data processing module comprises a register serial-parallel conversion unit, a second asynchronous FIFO, a second DDR SDRAM, a third asynchronous FIFO, a second RAM group and an azimuth data processing unit;

the register serial-parallel conversion unit combines the distance-oriented processed data into 512-bit data at every 4 data processing clocks, and writes the 512-bit data into a second DDR SDRAM through a second asynchronous FIFO, specifically: writing 16 4×4 matrix blocks every 26262820 addresses from address 0 of the second DDR SDRAM, writing 16 4×4 matrix blocks every 2626262820 addresses from address 128, and adding 128 to the initial address after each 2048 times of writing in this order until all 4×4 matrix blocks are written;

the third asynchronous FIFO is configured to read out the data blocks in the second DDR SDRAM and store the data blocks into the second RAM group, where the 4×4 matrix block read out each time is just data processed in 4 azimuth directions, specifically: starting from address 0 of the second DDR SDRAM, firstly reading 16 32-bit data of the address 0, and then sequentially reading every 128 addresses until all data of the first row of 2048×2048 512-bit matrix blocks, namely the first four rows of data of 8192×8192 matrix, are read; then reading 16 32bit data of the address 8, and sequentially reading every 128 addresses until the second row of all data of 2048×2048 512bit matrix blocks, namely 5 th to 8 th row data of 8k×8k matrix, are read; in this order, until all data is read;

the second RAM group comprises 2 RAM units, each RAM unit comprises 16 32-bit RAMs, and data in the second DDR SDRAM is stored in the 2 RAM units in a ping-pong manner by taking the 16 32-bit data as a whole;

the azimuth data processing unit reads 16 32-bit data from each clock in the second RAM group, and each data processing clock outputs 4 rows of 4 data of 4 columns for azimuth data processing.

In the scheme of the invention, the echo data matrix of 8192×8192 is divided into 2048×2048 small matrices of 4 rows and 4 columns, and each 4-time distance or azimuth data processing is just one of the data matrices of 4 rows and 4 columns, so that a large amount of data redundancy and line changing times of the traditional single-row single-column processing are avoided. The DDR SDRAM burst length is 8, the data bit width is 64 bits, namely, the read-write command corresponds to output 512bits of data, namely, the DDR write address can only be an integer multiple of 8. The radar echo data bit width is 32 bits, namely, one read/write of the DDR SDRAM is equivalent to reading out 16 data of 32 bits. The system is divided into a distance data processing module and an azimuth data processing module. The distance data processing module comprises a DDR group 1 memory module and an address control module, an input asynchronous FIFO, 3 shift registers with 512bits and 64 RAMs with 32 bits; the azimuth data transposition module comprises a 128-bit to 512-bit serial-parallel conversion module, a distance-to-output asynchronous FIFO, a DDR group 2 storage module, an address control module, an azimuth data input asynchronous FIFO and 16 32-bit RAMs.

The DDR SDRAM burst length is 8, the data bit width is 64 bits, namely, the read-write command corresponds to output 512bits of data, namely, the DDR write address can only be an integer multiple of 8. The radar echo data bit width is 32 bits, namely, one read/write of the DDR SDRAM is equivalent to reading out 16 data of 32 bits. The asynchronous FIFO has a data input bit width equal to 16 times the original data bit width, i.e., 512bits, and a data output bit width equal to 16 times the original data bit width, i.e., equal to the data bit width of DDR.

The data stored in the RAM is 4 rows and 16 columns of 32bit data each time, namely, 4 matrix blocks with the size of 4 multiplied by 4, and one column of data, namely, 4 32bit data, is read out from the data processing every clock distance. A 4 x 4 matrix block is obtained every 4 clocks.

The matrix blocks with the size of 4 multiplied by 4 are obtained through asynchronous FIFO and written into the DDR SDRAM memory with the mode of block storage.

The 16 4×4 matrix blocks are written every 262626144 addresses from address 0 of the DDR, and then, after 2048 times, the 16 4×4 matrix blocks are written every 262626144 addresses from address 128 of the DDR. In this order, after each 2048 writes, the initial address is incremented by 128 until the entire 4×4 matrix block is written.

The data in DDR is read out in blocks through asynchronous FIFO, and the 4X 4 matrix block read out each time is just 4 times of data processed in azimuth.

Starting from address 0 of DDR, 1 data matrix block of 4×4 is read out every 128 addresses; every 2048 times, adding 8 to the initial address, and reading out 1 data matrix block of 4×4 at intervals of 128 addresses again; until the 16 times 2048 4×4 matrix blocks are read, the data are read out in the same order from the next address until all the data are read out.

Compared with the prior art, the invention has the following advantages:

firstly, the DDR read-write efficiency of the parallel transposition system is improved by optimizing the transposition scheme. In the current mainstream parallel transposition system, 4-path parallel processing at a time at least needs to read 4 different addresses by performing 4 burst operations on DDR. The invention can meet 4 paths of parallel processing by a blocking mode in one burst; compared with a mainstream parallel transposition system, the invention greatly reduces the line feed activation operation of DDR, greatly improves the read-write efficiency of DDR and greatly reduces the power consumption.

Secondly, the invention avoids the use of a large amount of RAM for caching redundant data in the traditional transpose system. The main stream of transposition scheme still needs to read 512bit data each time after transposition, but only 128bit data is used each time, the rest data needs to be cached, and the rest data can not be used continuously until the whole column of 8912 data is read, so that a large amount of RAM is consumed to cache redundant data. The invention divides the 8192×8192 data matrix into 2048×2048 4 matrix blocks, so that the 4 processing in the distance direction and the 4 processing in the azimuth direction are just the same 4×4 matrix block. After transposition, only the current 512bit data is cached for processing, so that occupation of a large amount of RAM is avoided.

Thirdly, according to the fact that the number of the distance direction and the azimuth direction points of radar imaging processing data is the nth power of 2, the 4×4 small matrix blocks are used as units, so that the number of the distance direction and the azimuth direction points can meet the power multiple of 4, and therefore most imaging scene requirements can be met. And the matrix blocks of 4 rows and 4 columns are just consistent with 4-way parallel processing, data caching is not needed, and the direct pipeline operation can be realized.

Fourth, the invention can ensure that the distance direction and the azimuth direction process input data are uninterrupted, and the input data are stored in the DDR without loss and read out, thereby ensuring the pipelining high-speed operation of the whole data processing flow.

Drawings

FIG. 1 is a block diagram of an implementation of a DDR SDRAM-based four-way parallel SAR imaging data transpose system of the present invention;

FIG. 2 is a schematic diagram of 4-way parallel data processing in the present invention.

FIG. 3 is a flow chart of distance-oriented data readout in the present invention;

FIG. 4 is a distance data arrangement in DDR in the present invention;

FIG. 5 is a schematic diagram of distance-wise data readout in accordance with the present invention;

FIG. 6 is a schematic diagram of matrix partitioning in the present invention;

FIG. 7 is a flow chart of the azimuthal transpose data read process in accordance with the present invention.

FIG. 8 is an arrangement of azimuth data in DDR in the present invention;

Detailed Description

The invention is further described with reference to the drawings and detailed description.

As shown in FIG. 1, the four-path parallel SAR imaging data transposition system based on DDR SDRAM provided by the invention is divided into a distance data processing module and an azimuth data processing module. The distance data processing module comprises a DDR group 1 memory module and an address control module, an input asynchronous FIFO, 3 shift registers with 512bits and 64 RAMs with 32 bits; the azimuth data transposition module comprises a 128-bit to 512-bit serial-parallel conversion module, a distance-to-output asynchronous FIFO, a DDR group 2 storage module, an address control module, an azimuth data input asynchronous FIFO and 16 32-bit RAMs.

The other modules are realized on the FPGA except the DDR SDRAM, and the FPGA adopts an xc7vx690tffg1761-3 chip of XILINX company. The DDR SDRAM chip model is MT8JTF12864HZ-1G6, is DDR3 SDRAM, and the burst transmission length is set to 8. The development environment is Vivado 2019.2 of XILINX, and the ddr SDRAM read-write interface uses MIG cores provided by Vivado.

In this embodiment, the matrix to be transposed has a size of 8192×8192, and is divided into distance-wise processing before transposition and azimuth-wise processing after transposition.

As shown in fig. 2, the present system performs 4-way parallel processing: when the distance direction is processed, each clock processes 4 32bit data in the same column of 4 rows; during azimuth processing, each clock processes 4 32bit data in the same row of 4 columns:

the specific operation is as follows, and distance data processing is performed first, as shown in fig. 3.

After 8192×8192 echo data is written into DDR, it is read out by asynchronous FIFO, then written into shift register in turn, every 4 75M clocks the obtained 16 column data of 4 lines are written into RAM, and then read out by 16 300M clocks.

The sequence of echo data writing into the DDR is shown in fig. 4.

Each line of echo data is divided equally into 512 parts, each of which is 16 32-bit numbers, i.e. 512 bits. 512bits of data per write occupies 8 address spaces of the DDR. When writing data into DDR, firstly writing 16 32bit numbers into address 0, then writing 16 32bit numbers into every 32 addresses until the first row is written; writing the second row of data into the address 8, and then writing 16 32 bits at intervals of 32 addresses; writing the third row of data into the address 16, and then writing 16 32bit numbers every 32 addresses; finally, writing the fourth row of data into the address 24, and then writing 16 32 bits at intervals of 32 addresses; addresses 0-16383 of DDR are all written. DDR is written in 4 rows and 4 columns in the same order until all echo data is written.

In the actual address of the DDR, the echo data are the first 16 data of the 1 st row, the 2 nd row, the 3 rd row and the 4 th row, then the next 16 data of the 1 st row, the 2 nd row, the 3 rd row and the 4 th row, namely the 17 th to the 32 th data, are stored in the actual address of the DDR, and all the data of one to four rows are stored in the actual address of the DDR according to the sequence; then, the data of the 5 th to 8 th lines of echo data are stored in this order, and all the echo data are stored in this order.

The FPGA controls 16 32bit data in DDR as a whole, reads the data through asynchronous FIFO according to natural sequence, and outputs the same column data of 4 lines through serial-parallel conversion each data processing clock to perform distance data processing

As shown in fig. 4, first 16 pieces of data of the first row are read out, then first 16 pieces of data of the second row are read out, then first 16 pieces of data of the third row are read out, and then first 16 pieces of data of the fourth row are read out; next, 17 th to 32 th data of the first row are read out, and sequentially read out in this order.

As shown in fig. 5. The shift registers are sequentially read out and written in this order, and the current outputs of the 3 512-bit shift registers and the asynchronous FIFO, i.e. the 16-column data of four lines, are written into the 64 32-bit RAMs every four register processing clocks. The FPGA controls the same column data of four lines of data read out from the RAM by each clock to perform data processing, and each 16 data processing clocks process all four lines of 16 column data in the RAM, namely 64 32bit data. At this time, the four register clocks are right passed, and the FPGA writes the next 4 rows and 16 columns of data into the RAM.

As shown in fig. 6. The data of 8k×8k are divided into a matrix of 2k×2k 4 rows and 4 columns, and 16 32bit data obtained by the FPGA every 4 data processing clocks are the matrix data of 2k×2k 4 rows and 4 columns. The 16 32-bit data processed every 4 data processing clocks in the azimuth direction is just 16 32-bit data processed every 4 data processing clocks in the azimuth direction. Each 4 x 4 data matrix is divided as a whole, i.e. an 8k x 8k data matrix into 2048 x 2048 512bit data blocks.

The FPGA control combines the distance-wise processed data into 512bit data every 4 data processing clocks, i.e. a 4 row 4 column matrix as described above, and then writes into the DDR.

Azimuth data processing as shown in fig. 7, after the distance 8192×8192 is written to DDR to the processed data, it is read out through asynchronous FIFO and then ping pong is written to RAM bank 1 and RAM bank 2.

The distance-wise processed data is written into DDR in the order shown in FIG. 8, where A (x, y) is a 4 row 4 column matrix. According to the segmented 512bit data blocks, first 16 512bit data blocks of the first row are written into the DDR, then the address is added 26144, the 17 th to 32 nd 512bie data blocks of the first row are written, and the address is added 26144 again until all data of the first row are written; the second row is then written to address 128 for the first 16 512bit blocks, followed by address addition 26144. The sequence loops until the full portion is written with 2048 rows of 512bit data.

The FPGA controls 16 pieces of 32-bit data in the DDR as a whole, the data are read out through an asynchronous FIFO, ping pong is stored in the RAM group 1 and the RAM group 2, the RAM group 1 and the RAM group 2 both comprise 16 pieces of 32-bit RAMs, when the RAM group 1 writes the data, the RAM group 2 reads the data, and when the RAM group 2 writes the data, the RAM group 1 reads the data, so that the uninterrupted data are ensured.

Reading 16 32-bit data of address 0 from DDR, and sequentially reading every 128 addresses until all data of the first row of 2048×2048 512-bit matrix blocks, namely the first four rows of 8192×8192 matrix blocks are read; the 16 32bit data of address 8 are then read from the DDR, followed by every 128 address sequences until all the second row of 2048 x 2048 512bit matrix blocks, i.e., the 5 th to 8 th row of the 8k x 8k matrix, is read. In this order, until all data is read.

Each register clock reads 16 32bit data, and each data processing clock outputs 4 rows of 4 data of 4 columns for azimuth data processing.

Claims (1)

1. The four-path parallel SAR imaging data transposition system based on the DDR SDRAM is characterized by comprising a distance-oriented data processing module and an azimuth-oriented data processing module, wherein the distance-oriented data processing module comprises a first DDR SDRAM, a first asynchronous FIFO, a shift register group, a first RAM group and a distance-oriented data processing unit;

the first DDR SDRAM is used for receiving radar echo data, the burst length of the first DDR SDRAM is 8, the data bit width is 64 bits, the radar echo data bit width is 32 bits, a matrix with the radar echo data of 8192 multiplied by 8192 is defined, the radar echo data is written into the first DDR SDRAM in a block storage mode, each row of the radar echo data is averagely divided into 512 parts, each part is 16 32bit numbers, namely 512bits, and the 512bit data written in each time occupies 8 address spaces of the first DDR SDRAM, and the method comprises the following steps: writing the first row of data from address 0, and writing 16 32-bit data at intervals of 32 addresses; then, the second row of data starts from the address 8, and then 16 32bit numbers are written into every 32 addresses; then, starting the third row of data from the address 16, and then writing 16 32 bits of data into the memory every 32 addresses; finally, starting the fourth row of data from the address 24, and then writing 16 32 bits at intervals of 32 addresses; the addresses 0-16383 of the first DDR SDRAM are fully written; writing 4 rows each time in the same sequence until all radar echo data are written;

the first asynchronous FIFO is used for sequentially reading data in the first DDR SDRAM, and specifically comprises the following steps: first the first 16 data of the first row are read out, then the first 16 data of the second row are read out, then the first 16 data of the third row are read out, then the first 16 data of the fourth row are read out; then, the 17 th to 32 th data of the first row are read out, and the data are sequentially read out in this order;

the data read out by the first asynchronous FIFO sequentially pass through a shift register group, wherein the shift register group comprises 3 shift registers with 512bits, and the data passing through the shift register group is stored into a first RAM group, specifically: writing the current output of the 3 shift registers with 512bits and the asynchronous FIFO every four register processing clocks, namely 16 columns of data of four lines into 64 32-bit RAMs;

the first RAM group comprises 64 32-bit RAMs, the data stored in the RAMs are 4 rows and 16 columns of 32-bit data each time, the data are 4 matrix blocks of 4 multiplied by 4, and each clock reads out the same column data input distance of four rows of data from the first RAM group and processes the data to the data processing unit;

the azimuth data processing module comprises a register serial-parallel conversion unit, a second asynchronous FIFO, a second DDR SDRAM, a third asynchronous FIFO, a second RAM group and an azimuth data processing unit;

the register serial-parallel conversion unit combines the distance-oriented processed data into 512-bit data at every 4 data processing clocks, and writes the 512-bit data into a second DDR SDRAM through a second asynchronous FIFO, specifically: writing 16 4×4 matrix blocks every 26262820 addresses from address 0 of the second DDR SDRAM, writing 16 4×4 matrix blocks every 2626262820 addresses from address 128, and adding 128 to the initial address after each 2048 times of writing in this order until all 4×4 matrix blocks are written;

the third asynchronous FIFO is configured to read out the data blocks in the second DDR SDRAM and store the data blocks into the second RAM group, where the 4×4 matrix block read out each time is just data processed in 4 azimuth directions, specifically: starting from address 0 of the second DDR SDRAM, firstly reading 16 32-bit data of the address 0, and then sequentially reading every 128 addresses until all data of the first row of 2048×2048 512-bit matrix blocks, namely the first four rows of data of 8192×8192 matrix, are read; then reading 16 32bit data of the address 8, and sequentially reading every 128 addresses until the second row of all data of 2048×2048 512bit matrix blocks, namely 5 th to 8 th row data of 8k×8k matrix, are read; in this order, until all data is read;

the second RAM group comprises 2 RAM units, each RAM unit comprises 16 32-bit RAMs, and data in the second DDR SDRAM is stored in the 2 RAM units in a ping-pong manner by taking the 16 32-bit data as a whole;

the azimuth data processing unit reads 16 32-bit data from each clock in the second RAM group, and each data processing clock outputs 4 rows of 4 data of 4 columns for azimuth data processing.