CN116500419A - Chip test gear determining system and method based on dichotomy - Google Patents
Chip test gear determining system and method based on dichotomy Download PDFInfo
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- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
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Abstract
The invention discloses a system and a method for determining a chip test gear based on a dichotomy, wherein the system comprises: the data acquisition module is used for acquiring gear data and corresponding current data of a plurality of test chips by using the testing machine; the data sorting module is used for sorting the gear data according to the size of the current data; the dichotomy searching module is used for regulating the gear data into the same array; searching the data in the array by a dichotomy until the optimal current gear of the plurality of test chips is found. According to the invention, aiming at the chip test gear and the current data of the nonlinear sequence, the current data are rearranged into a monotonically increasing or decreasing sequence, and then the gear data are searched by using a dichotomy method, so that the optimal test gear is quickly found, the test time is further shortened, and the test cost of the product is reduced.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a system and a method for determining a chip test gear based on a dichotomy.
Background
Chip testing is the first station for semiconductor back-end packaging testing to ensure that each chip substantially meets the device's characteristics or design specifications. Because the process change can affect the performance of the chip circuit and cause the deviation of the actual current value and the target current value of the chip, the simulation parameters of the chip need to be trimmed in the test process of the chip, a plurality of trimming gears are usually designed for each simulation parameter when the chip is manufactured, then the current value closest to the target current value is found in the plurality of trimming gears of the simulation parameters and the corresponding current values thereof and the trimming gear corresponding to the current value is found for trimming in the later chip test.
In the prior art, one of the most commonly used methods for trimming the analog parameters of a chip is: testing current values corresponding to all trimming gears of the simulation parameters, finding out a target trimming gear corresponding to the closest target trimming amount, and trimming the simulation parameters of the chip by using the target trimming gear; the trimming mode has high trimming precision, but needs to test all trimming gears, so that the test time is long and the trimming efficiency is low. In order to increase the test efficiency, a plurality of sample chips are usually tested at the same time, so that the conventional test method consumes more test time.
Disclosure of Invention
In order to solve the technical problems, the invention provides a chip test gear determining system and method based on a dichotomy, aiming at a chip test gear and current data of a nonlinear sequence, the current data are rearranged into a monotonically increasing or decreasing sequence, and then the dichotomy is used for searching gear data, so that the optimal test gear is quickly found, the test time is further shortened, and the test cost of a product is reduced.
Specifically, the technical scheme of the invention is as follows:
in a first aspect, the invention discloses a dichotomy-based chip test gear determination system, comprising:
the data acquisition module is used for acquiring gear data and corresponding current data of a plurality of test chips by using the testing machine;
the data sorting module is used for sorting the gear data according to the size of the current data;
the dichotomy searching module is used for regulating the gear data into the same array; searching the data in the array by a dichotomy until the optimal current gear of the plurality of test chips is found.
In some embodiments, the dichotomy finding module comprises:
a target current obtaining sub-module for obtaining a target current value;
the data normalization sub-module is used for sequentially arranging the ordered gear data into the same array;
the intermediate value searching sub-module is used for searching the intermediate position of the array and dividing the array into a front array and a rear array based on the intermediate position; acquiring a gear corresponding to the intermediate position as a reference gear;
the data acquisition module is also used for acquiring the current value corresponding to the reference gear of each test chip;
the current value comparison sub-module is used for comparing the current value corresponding to the target current value and the reference gear to obtain the standard gear of each test chip;
and the gear determining submodule is used for determining the optimal current gear of the plurality of test chips based on the standard gear of each test chip.
In some embodiments, when the order of the current data is from small to large, the current value comparison submodule is specifically configured to:
if the target current value is in the range of the current value interval corresponding to the reference gear, the reference gear is the standard gear of the test chip;
if the target current value is larger than the current value interval range corresponding to the reference gear, the intermediate value searching sub-module searches the intermediate position in the rear array again so as to acquire a new reference gear for comparison;
and if the target current value is smaller than the current value interval range corresponding to the reference gear, searching the middle position in the front array again through the middle value searching sub-module so as to acquire a new reference gear for comparison.
In some embodiments, the gear determination submodule specifically includes:
the statistics unit is used for counting the number of the test chips corresponding to each standard gear based on the standard gear of each test chip;
and the judging unit is used for selecting the standard gear with the largest number of the corresponding test chips as the optimal current gear of the plurality of test chips.
In a second aspect, the invention also discloses a method for determining the gear of the chip test based on the dichotomy, which comprises the following steps:
acquiring gear data and corresponding current data of a plurality of test chips by using a testing machine;
sequencing the gear data according to the size of the current data;
the gear data are ordered into the same array; searching the data in the array by a dichotomy until the optimal current gear of the plurality of test chips is found.
In some embodiments, the data in the array is searched by a dichotomy; the method comprises the following steps:
obtaining a target current value;
sequentially arranging the ordered gear data into the same array;
searching the middle position of the array, and dividing the array into a front array and a rear array based on the middle position; acquiring a gear corresponding to the intermediate position as a reference gear;
obtaining the current value corresponding to the reference gear of each test chip;
comparing the magnitude of the current value corresponding to the target current value and the reference gear to obtain the standard gear of each test chip;
and determining the optimal current gear of the plurality of test chips based on the standard gear of each test chip.
In some embodiments, comparing the magnitude of the current value corresponding to the target current value and the reference gear to obtain a standard gear of each test chip; the method specifically comprises the following steps:
when the arrangement sequence of the current data is from small to large, comparing the magnitude of the current value corresponding to the target current value and the reference gear;
if the target current value is in the range of the current value interval corresponding to the reference gear, the reference gear is the standard gear of the test chip;
if the target current value is larger than the current value interval range corresponding to the reference gear, searching the middle position in the rear array again so as to acquire a new reference gear for comparison;
and if the target current value is smaller than the current value interval range corresponding to the reference gear, searching the middle position in the front array again so as to acquire a new reference gear for comparison.
In some embodiments, the determining the optimal current gear of the plurality of test chips based on the standard gear of each test chip specifically includes:
based on the standard gear of each test chip, counting the number of the test chips corresponding to each standard gear;
and selecting the standard gear with the largest number of the corresponding test chips as the optimal current gear of the plurality of test chips.
Compared with the prior art, the invention has at least one of the following beneficial effects:
1. the original nonlinear mode of gradually scanning each gear is changed into a linear relation by aiming at the data of the non-monotonic sequence, so that quick reference gear searching can be realized by adopting a dichotomy mode, the optimal gear is obtained, and the test time and the test cost are saved.
2. According to the invention, the testing efficiency can be improved, a plurality of chip samples can be tested in batches, the number of the test chips corresponding to each standard gear is counted based on the standard gears of each test chip, and the standard gear with the largest number of the corresponding test chips is selected as the optimal current gear of the plurality of test chips, so that after the optimal current gear is found, the parameters of the optimal gear are modified, and the testing efficiency is improved.
Drawings
The above features, technical features, advantages and implementation of the present invention will be further described in the following description of preferred embodiments with reference to the accompanying drawings in a clear and easily understood manner.
FIG. 1 is a block diagram illustrating one embodiment of a dichotomy-based chip test shift determination system of the invention;
FIG. 2 is a block diagram of another embodiment of a dichotomy-based chip test gear determination system of the invention;
FIG. 3 is a nonlinear trend graph of chip shift and corresponding current for one embodiment of a dichotomy-based chip test shift determination method of the present invention;
FIG. 4 is a linear trend graph of chip gear and corresponding current after sorting current data according to one embodiment of a method for determining chip test gear based on dichotomy of the present invention;
FIG. 5 is a flowchart of another embodiment of a dichotomy-based chip test gear determination method of the invention;
FIG. 6 is a sub-flowchart of step S300 in a dichotomy-based chip test gear determination method of the invention;
fig. 7 is a sub-flowchart of another embodiment of step S300 in the method for determining a gear of a chip test based on dichotomy according to the present invention.
Detailed Description
In the following description, for purposes of explanation and not limitation, specific details are set forth, such as particular system configurations, techniques, etc. in order to provide a thorough understanding of the embodiments of the present application. However, it will be apparent to one skilled in the art that the present application may be practiced in other embodiments that depart from these specific details. In other instances, detailed descriptions of well-known systems, devices, circuits, and methods are omitted so as not to obscure the description of the present application with unnecessary detail.
It should be understood that the terms "comprises" and/or "comprising," when used in this specification and the appended claims, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
For simplicity of the drawing, only the parts relevant to the invention are schematically shown in each drawing, and they do not represent the actual structure thereof as a product. Additionally, in order to simplify the drawing for ease of understanding, components having the same structure or function in some of the drawings are shown schematically with only one of them, or only one of them is labeled. Herein, "a" means not only "only this one" but also "more than one" case.
It should be further understood that the term "and/or" as used in this specification and the appended claims refers to any and all possible combinations of one or more of the associated listed items, and includes such combinations.
In this context, it should be noted that the terms "mounted," "connected," and "connected" are to be construed broadly, and may be, for example, fixedly connected, detachably connected, or integrally connected, unless explicitly stated or limited otherwise; can be mechanically or electrically connected; can be directly connected or indirectly connected through an intermediate medium, and can be communication between two elements. The specific meaning of the above terms in the present invention will be understood in specific cases by those of ordinary skill in the art.
In particular implementations, the terminal devices described in embodiments of the present application include, but are not limited to, other portable devices such as mobile phones, laptop computers, home teaching machines, or tablet computers having a touch-sensitive surface (e.g., a touch screen display and/or a touch pad). It should also be appreciated that in some embodiments, the terminal device is not a portable communication device, but rather a desktop computer having a touch-sensitive surface (e.g., a touch screen display and/or a touch pad).
In addition, in the description of the present application, the terms "first," "second," and the like are used merely to distinguish between descriptions and are not to be construed as indicating or implying relative importance.
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following description will explain the specific embodiments of the present invention with reference to the accompanying drawings. It is evident that the drawings in the following description are only examples of the invention, from which other drawings and other embodiments can be obtained by a person skilled in the art without inventive effort.
Referring to fig. 1 of the specification, an embodiment of a system for determining a gear of a chip test based on dichotomy provided by the present invention includes:
the data acquisition module 10 is configured to acquire gear data and corresponding current data of a plurality of test chips by using a testing machine.
Specifically, the gear data refers to a plurality of trimming gears designed according to the simulation parameters of the chip test, and can be indicated by numerical numbers. When the chip is tested, the corresponding test analog quantity is generated by a plurality of trimming gears of the analog parameters, the analog quantity refers to current data, and the situation that other data are used as the analog quantity is also within the protection scope of the invention.
The data sorting module 20 is configured to sort the gear data according to the magnitude of the current data.
Specifically, the data of the nonlinear sequence are reordered according to the current data, and the current data can be ordered from small to large, so that the current data shows an increasing trend; the current data may also be ordered from large to small, with a decreasing trend. The data sorting is from big to small or from small to big, which affects the selection of dividing the array during the subsequent dichotomy searching, and the data sorting is required to be correspondingly set according to the test requirement.
The dichotomy searching module 30 is configured to normalize the gear data into the same array; searching the data in the array by a dichotomy until the optimal current gear of the plurality of test chips is found.
Specifically, compared with the traditional mode of scanning the nonlinear gear data successively, the dichotomy searching method improves the testing efficiency by multiple times. The array is divided into halves for many times, half of the needed data is screened out, and then the half division is performed, so that standard gears of all test chips can be rapidly positioned. Thereby finding out the optimal current gear of the plurality of test chips.
Another embodiment of a system for determining a gear of a chip test based on a dichotomy of the present invention, as shown in fig. 2 of the specification, in one embodiment of the above system, the system further comprises, based on a dichotomy search module 30:
a target current acquisition sub-module 31 for acquiring a target current value.
Specifically, the target current value, namely the target analog quantity, is the existing reference data, and the acquisition of the target current value is the direct application of the existing data.
The data normalization submodule 32 is configured to sequentially arrange the ordered gear data into the same array.
Specifically, after the current data is ordered from small to large or from large to small, the current data shows an increasing or decreasing trend. And mapping the rearranged gears into an array, wherein the data contained in the array are the gear numbers after the current magnitude sequencing.
An intermediate value searching sub-module 33 is configured to search for an intermediate position of the array, and divide the array into a front array and a rear array based on the intermediate position. And acquiring a gear data corresponding to the intermediate position as a reference gear.
Specifically, if the total number of gears is an odd number, the middle position of the array is a gear number, namely only one reference gear is provided; if the total number of gears is even, the middle position of the array is two gear numbers, namely, the reference gears are two.
The array before the intermediate position is divided into a front array, and the array after the intermediate position is divided into a rear array.
The data acquisition module 10 is further configured to acquire a current value corresponding to the reference gear of each test chip.
Specifically, the gear corresponding to the array intermediate position value needs to be set in the chip data acquisition module 10, and then the current value returned by the data acquisition module 10 is compared with the target value.
And the current value comparison sub-module 34 is used for comparing the current value corresponding to the target current value and the reference gear to obtain the standard gear of each test chip.
Specifically, the method is also used for determining to execute different actions in the next step according to different comparison results, so that the standard gear of each test chip is deduced.
A gear determination submodule 35 for determining an optimal current gear of the plurality of test chips based on the standard gear of each test chip.
Specifically, when a plurality of samples are tested simultaneously, different samples have deviation of corresponding current values under the same test gear, so that the optimal current gear of a plurality of test chips needs to be selected from the standard gears of each test chip, the number of the test chips falling on the standard gear is determined, and the standard gear with the largest number of the corresponding test chips can be regarded as the optimal current gear of the plurality of test chips.
In another implementation of the above embodiment, the gear determination submodule 35 includes:
and the statistics unit 351 is configured to count the number of test chips corresponding to each standard gear based on the standard gear of each test chip.
And the judging unit 352 is used for selecting the standard gear with the largest number of the corresponding test chips as the optimal current gear of the plurality of test chips.
In another embodiment of the system for determining a gear of a chip test based on the dichotomy of the present invention, in one embodiment of the above system, when the arrangement order of the current data is from small to large, the current value comparison submodule 34 is specifically configured to:
and if the target current value is in the range of the current value interval corresponding to the reference gear, the reference gear is the standard gear of the test chip.
Specifically, the range of the current value is determined by the current corresponding to the reference gear of the chip sample and the current corresponding to the front gear and the rear gear of the chip sample. For example, in the process of binary search, the current data corresponding to the reference gear of the first chip sample is 5.1 microamps, the current data corresponding to the front gear is 4.1 microamps, and the current data corresponding to the rear gear is 6.0 microamps, so that the current value interval range corresponding to the reference gear can be calculated as follows: between (5.1+4.1)/2 and (6.0+5.1)/2, i.e. 4.6-5.55 microamps. If the magnitude of the target current value is within this range at this time, the reference gear may be regarded as a standard gear of the test chip.
And if the target current value is larger than the current value interval range corresponding to the reference gear, searching the middle position in the rear array again through the middle value searching sub-module so as to acquire a new reference gear for comparison.
Specifically, when the arrangement sequence of the current data is from small to large, the target current value is larger, and the later array is required to be used as a new array, and the steps are repeated to search again.
Similarly, if the arrangement sequence of the current data is from big to small, the target current value is larger, and the searched array is the previous array.
And if the target current value is smaller than the current value interval range corresponding to the reference gear, searching the middle position in the front array again through the middle value searching sub-module so as to acquire a new reference gear for comparison.
Specifically, the case where the target current value is larger is opposite to the case where the target current value is smaller, and will not be described here again.
The invention discloses an embodiment of a chip test gear determining method based on a dichotomy.
S1, taking ISA Trimming as an example, the chip changes from ISA current corresponding to gears 0-31 to nonlinear trend. As shown in figure 3 of the specification.
Specifically, ISA chinese is interpreted as a current sense amplifier. The current value output by the chip can be measured by a tester.
S2, reordering gears of the ISA to enable the ISA current values to be distributed in a monotonically increasing trend, wherein the distribution is shown in an attached figure 4 of the specification.
S3, mapping the reordered gear positions into an array, wherein the array can be expressed as:
Intdac_Array[32]＝{19,18,17,16,23,22,24,20,27,26,25,24,31,30,29,28,3,2,1,0,7,6,5,4,11,10,9,8,15,14,13,12}；
s4, setting the gear corresponding to the intermediate value of the array subscript into the chip, comparing the current value returned by the chip with the target value, if the current value is smaller, searching the chip again in the half of the array smaller than the intermediate value, otherwise, searching the chip again in the half of the array larger than the intermediate value until the optimal gear of each test chip is found.
S5, setting the gear corresponding to the new data index into the chip, and repeating the step of the last step until the gear corresponding to the optimal ISA current value is found.
Based on the same technical conception, the invention also discloses a chip test gear determining method based on the dichotomy, which can be realized by adopting any of the chip test gear determining system embodiments based on the dichotomy, and specifically, the chip test gear determining method embodiment based on the dichotomy, as shown in the attached figure 5 of the specification, comprises the following steps:
s100, acquiring gear data and corresponding current data of a plurality of test chips by using a testing machine.
Specifically, the gear data refers to a plurality of trimming gears designed according to the simulation parameters of the chip test, and can be indicated by numerical numbers. When the chip is tested, the corresponding test analog quantity is generated by a plurality of trimming gears of the analog parameters, the analog quantity refers to current data, and the situation that other data are used as the analog quantity is also within the protection scope of the invention.
And S200, sorting the gear data according to the size of the current data.
Specifically, the data of the nonlinear sequence are reordered according to the current data, and the current data can be ordered from small to large, so that the current data shows an increasing trend; the current data may also be ordered from large to small, with a decreasing trend. The data sorting is from big to small or from small to big, which affects the selection of dividing the array during the subsequent dichotomy searching, and the data sorting is required to be correspondingly set according to the test requirement.
S300, the gear data are ordered into the same array. Searching the data in the array by a dichotomy until the optimal current gear of the plurality of test chips is found.
Specifically, compared with the traditional mode of scanning the nonlinear gear data successively, the dichotomy searching method improves the testing efficiency by multiple times. The array is divided into halves for many times, half of the needed data is screened out, and then the half division is performed, so that standard gears of all test chips can be rapidly positioned. Thereby finding out the optimal current gear of the plurality of test chips.
In another embodiment of the method for determining the gear of the chip test based on the dichotomy, as shown in fig. 6 of the specification, in the embodiment of the method, S300, the gear data are ordered into the same array, and the data in the array are searched by the dichotomy until the optimal current gear of the plurality of test chips is found; on the basis of (a), further comprising:
s310, obtaining a target current value.
Specifically, the target current value, namely the target analog quantity, is the existing reference data, and the acquisition of the target current value is the direct application of the existing data.
S320, sequentially arranging the ordered gear data into the same array.
Specifically, after the current data is ordered from small to large or from large to small, the current data shows an increasing or decreasing trend. And mapping the rearranged gears into an array, wherein the data contained in the array are the gear numbers after the current magnitude sequencing.
S330, searching the middle position of the array, and dividing the array into a front array and a rear array based on the middle position; and acquiring a gear data corresponding to the intermediate position as a reference gear.
Specifically, if the total number of gears is an odd number, the middle position of the array is a gear number, namely only one reference gear is provided; if the total number of gears is even, the middle position of the array is two gear numbers, namely, the reference gears are two.
The array before the intermediate position is divided into a front array, and the array after the intermediate position is divided into a rear array.
S340, obtaining the current value corresponding to the reference gear of each test chip.
Specifically, the gear corresponding to the array intermediate position value needs to be set in the chip data acquisition module 10, and then the current value returned by the data acquisition module 10 is compared with the target value.
S350, comparing the current values corresponding to the target current value and the reference gear to obtain the standard gear of each test chip.
Specifically, the method is also used for determining to execute different actions in the next step according to different comparison results, so that the standard gear of each test chip is deduced.
S360, determining the optimal current gear of the plurality of test chips based on the standard gear of each test chip.
Specifically, when a plurality of samples are tested simultaneously, different samples have deviation of corresponding current values under the same test gear, so that the optimal current gear of a plurality of test chips needs to be selected from the standard gears of each test chip, the number of the test chips falling on the standard gear is determined, and the standard gear with the largest number of the corresponding test chips can be regarded as the optimal current gear of the plurality of test chips.
In another embodiment of the method for determining the chip test gear based on the dichotomy, as shown in fig. 7 of the specification, in the embodiment of the method, S350, comparing the magnitude of the current value corresponding to the reference gear with the magnitude of the current value of the target current value to obtain the standard gear of each test chip; on the basis of (a), further comprising:
s351, comparing the magnitude of the current value corresponding to the target current value and the reference gear when the arrangement sequence of the current data is from small to large;
specifically, the range of the current value is determined by the current corresponding to the reference gear of the chip sample and the current corresponding to the front gear and the rear gear of the chip sample.
S352, if the target current value is in the range of the current value interval corresponding to the reference gear, the reference gear is the standard gear of the test chip;
specifically, for example, in the process of binary search, the current data corresponding to the reference gear of the first chip sample is 5.1 microamps, the current data corresponding to the front gear is 4.1 microamps, and the current data corresponding to the rear gear is 6.0 microamps, so that the current value interval range corresponding to the reference gear can be calculated as follows: between (5.1+4.1)/2 and (6.0+5.1)/2, i.e. 4.6-5.55 microamps. If the magnitude of the target current value is within this range at this time, the reference gear may be regarded as a standard gear of the test chip.
S353, if the target current value is greater than the current value interval range corresponding to the reference gear, searching the middle position in the rear array again so as to acquire a new reference gear for comparison;
specifically, when the arrangement sequence of the current data is from small to large, the target current value is larger, and the later array is required to be used as a new array, and the steps are repeated to search again.
Similarly, if the arrangement sequence of the current data is from big to small, the target current value is larger, and the searched array is the previous array.
S354, if the target current value is smaller than the current value interval range corresponding to the reference gear, the middle position is searched again in the front array so as to acquire a new reference gear for comparison.
Specifically, the case where the target current value is large is opposite to the case where the target current value is small.
In another implementation of the foregoing embodiment, the S360 determines an optimal current gear of the plurality of test chips based on a standard gear of each test chip; the method specifically comprises the following steps:
s361, based on the standard gears of all the test chips, counting the number of the test chips corresponding to each standard gear;
s362, selecting the standard gear with the largest number of the corresponding test chips as the optimal current gear of the test chips.
The system and the method for determining the chip test gear based on the dichotomy have the same technical conception, and the technical details of the two embodiments can be mutually applicable, so that repetition is reduced, and the description is omitted.
The present invention is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems) and computer program products according to embodiments of the invention. It will be understood that each flowchart and/or block of the flowchart illustrations and/or block diagrams, and combinations of flowcharts and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
While preferred embodiments of the present invention have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. It is therefore intended that the following claims be interpreted as including the preferred embodiments and all such alterations and modifications as fall within the scope of the invention.
It will be apparent to those skilled in the art that various modifications and variations can be made to the present invention without departing from the spirit or scope of the invention. Thus, it is intended that the present invention also include such modifications and alterations insofar as they come within the scope of the appended claims or the equivalents thereof.
Claims (8)
1. A dichotomy-based chip test gear determination system, comprising:
the data acquisition module is used for acquiring gear data and corresponding current data of a plurality of test chips by using the testing machine;
the data sorting module is used for sorting the gear data according to the size of the current data;
the dichotomy searching module is used for regulating the gear data into the same array; searching the data in the array by a dichotomy until the optimal current gear of the plurality of test chips is found.
2. The system for determining a gear of a chip test based on a dichotomy of claim 1, wherein said dichotomy search module comprises:
a target current obtaining sub-module for obtaining a target current value;
the data normalization sub-module is used for sequentially arranging the ordered gear data into the same array;
the intermediate value searching sub-module is used for searching the intermediate position of the array and dividing the array into a front array and a rear array based on the intermediate position; acquiring a gear corresponding to the intermediate position as a reference gear;
the data acquisition module is also used for acquiring the current value corresponding to the reference gear of each test chip;
the current value comparison sub-module is used for comparing the current value corresponding to the target current value and the reference gear to obtain the standard gear of each test chip;
and the gear determining submodule is used for determining the optimal current gear of the plurality of test chips based on the standard gear of each test chip.
3. The dichotomy-based chip test gear determination system of claim 2, wherein when the current data is arranged in a small-to-large order, the current value comparison submodule is specifically configured to:
if the target current value is in the range of the current value interval corresponding to the reference gear, selecting the reference gear as the standard gear of the test chip;
if the target current value is larger than the current value interval range corresponding to the reference gear, the intermediate value searching sub-module searches the intermediate position in the rear array again so as to acquire a new reference gear for comparison;
and if the target current value is smaller than the current value interval range corresponding to the reference gear, searching the middle position in the front array again through the middle value searching sub-module so as to acquire a new reference gear for comparison.
4. The dichotomy-based chip test gear determination system of claim 2, wherein the gear determination submodule specifically comprises:
the statistics unit is used for counting the number of the test chips corresponding to each standard gear based on the standard gear of each test chip;
and the judging unit is used for selecting the standard gear with the largest number of the corresponding test chips as the optimal current gear of the plurality of test chips.
5. The chip test gear determining method based on the dichotomy is characterized by comprising the following steps of:
acquiring gear data and corresponding current data of a plurality of test chips by using a testing machine;
sequencing the gear data according to the size of the current data;
the gear data are ordered into the same array; searching the data in the array by a dichotomy until the optimal current gear of the plurality of test chips is found.
6. The method for determining a gear of a chip test based on a dichotomy of claim 5, wherein the data in the array is searched by the dichotomy; the method specifically comprises the following steps:
obtaining a target current value;
sequentially arranging the ordered gear data into the same array;
searching the middle position of the array, and dividing the array into a front array and a rear array based on the middle position; acquiring a gear corresponding to the intermediate position as a reference gear;
obtaining the current value corresponding to the reference gear of each test chip;
comparing the magnitude of the current value corresponding to the target current value and the reference gear to obtain the standard gear of each test chip;
and determining the optimal current gear of the plurality of test chips based on the standard gear of each test chip.
7. The dichotomy-based chip test gear determination method of claim 6, wherein the comparing the magnitude of the current value corresponding to the target current value and the reference gear obtains a standard gear of each test chip; the method specifically comprises the following steps:
when the arrangement sequence of the current data is from small to large, comparing the magnitude of the current value corresponding to the target current value and the reference gear;
if the target current value is in the range of the current value interval corresponding to the reference gear, selecting the reference gear as the standard gear of the test chip;
if the target current value is larger than the current value interval range corresponding to the reference gear, searching the middle position in the rear array again so as to acquire a new reference gear for comparison;
and if the target current value is smaller than the current value interval range corresponding to the reference gear, searching the middle position in the front array again so as to acquire a new reference gear for comparison.
8. The dichotomy-based chip test gear determination method of claim 6, wherein determining the optimal current gear of the plurality of test chips based on the standard gear of each test chip comprises:
based on the standard gear of each test chip, counting the number of the test chips corresponding to each standard gear;
and selecting the standard gear with the largest number of the corresponding test chips as the optimal current gear of the plurality of test chips.
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| CN202310452661.7A CN116500419A (en) | 2023-04-25 | 2023-04-25 | Chip test gear determining system and method based on dichotomy |
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