CN114461466A - Method, device, equipment and storage medium for fine tuning of reference circuit of flash memory chip - Google Patents
Method, device, equipment and storage medium for fine tuning of reference circuit of flash memory chip Download PDFInfo
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- 238000009966 trimming Methods 0.000 claims description 30
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Abstract
The embodiment of the invention discloses a method, a device, equipment and a storage medium for fine tuning a reference circuit of a flash memory chip, wherein the scheme comprises the following steps: acquiring probability distribution information of history data of the fine-adjustment gears of the flash memory chip; setting a first interval range of fine shift gear values, and discretizing the fine shift gear values in the first interval range according to a preset step length to obtain a first number of fine shift gear values; based on the magnitude sequence of the probability values in the probability distribution information, sequencing all fine-adjustment gear values in the first number of fine-adjustment gear values to obtain a second number of fine-adjustment gear values consistent with the first number of values; and selecting to-be-set fine shift values from the second number of fine shift values in sequence for the flash memory chips to be tested, testing the flash memory chips to be tested based on the to-be-set fine shift values, and setting the to-be-set fine shift values as first target fine shift values when the absolute value of the difference between the measured value obtained by testing and the preset target value is smaller than a preset threshold value.
Description
Technical Field
The present disclosure relates to the field of non-volatile memory technologies, and in particular, to a method, an apparatus, a device, and a storage medium for trimming a reference circuit of a flash memory chip.
Background
Flash memory is a long-life, non-volatile memory that retains stored data information when power is off, and because it retains data when power is off, flash memory is commonly used to retain settings, such as data in computers, personal digital assistants, digital cameras, and the like.
The flash memory chip design includes a memory area and a peripheral control circuit, wherein an internal voltage reference unit controls the voltage distribution of the chip. In order to eliminate the influence of process parameter fluctuation on the precision of the reference voltage, the circuit is designed into a micro adjustable mode, for example, before the flash memory chip leaves a factory, the programming voltage in the programming state or the erasing voltage in the erasing state needs to be tested and fine-tuned, and the program voltage or the erasing voltage after the fine tuning is stored in an internal memory of the embedded flash memory. The prior art generally tests the fine adjustment gear of the flash memory chip based on a linear scanning method, so that each time the fine adjustment gear is gradually increased from zero until a target fine adjustment gear value is found, more test time and test cost are needed.
Therefore, it is desirable to provide an efficient method for testing the trim gear value of a flash memory chip.
Disclosure of Invention
Embodiments of the present disclosure provide a method and an apparatus for trimming a reference circuit of a flash memory chip, so as to provide an efficient method for testing a trimming stage value of the flash memory chip.
In order to solve the above technical problem, the embodiments of the present specification are implemented as follows:
an embodiment of the present disclosure provides a method for trimming a reference circuit of a flash memory chip, including:
acquiring probability distribution information of history data of the fine-adjustment gears of the flash memory chip;
setting a first interval range of fine adjustment gear values, and discretizing the fine adjustment gear values in the first interval range according to a preset step length to obtain a first number of fine adjustment gear values;
sorting all fine-adjustment gear values in the first number of fine-adjustment gear values based on the magnitude sequence of the probability values in the probability distribution information to obtain a second number of fine-adjustment gear values consistent with the first number of values;
and selecting to-be-set fine shift values from the second number of fine shift values for the flash memory chips to be tested in sequence, testing the flash memory chips to be tested based on the to-be-set fine shift values, and setting the to-be-set fine shift values as first target fine shift values when the absolute value of the difference between a measured value obtained by testing and a preset target value is smaller than a preset threshold value.
Preferably, the obtaining probability distribution information of the fine shift register value of the flash memory chip in advance specifically includes:
pre-acquiring a preset number of flash memory chips, and setting a second interval range consistent with the first interval range;
based on the second interval range, testing the fine adjustment gear values of the preset number of flash memory chips by a linear scanning method to obtain a second target fine adjustment gear value consistent with the preset number of values;
and analyzing the statistical rule of the second target fine adjustment gear value consistent with the preset number of numerical values to obtain the probability distribution information of the actual fine adjustment gear values of the preset number of flash memory chips.
Preferably, the probability distribution information of the actual fine shift gear position is normal distribution probability information of the actual fine shift gear position.
Preferably, the predetermined number of the flash memory chips ranges from 1000 to 20000.
An embodiment of the present disclosure provides a trimming apparatus for a flash memory chip reference circuit, including:
the fine-adjustment gear value probability distribution acquisition module is used for acquiring probability distribution information of the fine-adjustment gear historical data of the flash memory chip;
the fine shift value discretization module is used for setting a first interval range of fine shift values, and discretizing the fine shift values in the first interval range according to preset step length to obtain a first number of fine shift values;
the fine shift value sequencing module is used for sequencing all fine shift values in the first number of fine shift values based on the magnitude sequence of the probability values in the probability distribution information to obtain a second number of fine shift values consistent with the first number of values;
and the fine shift value testing module is used for selecting a fine shift value to be set from the second number of fine shift values in sequence for the flash memory chips to be tested, testing the flash memory chips to be tested based on the fine shift value to be set, and setting the fine shift value to be set as a first target fine shift value when the absolute value of the difference between the measured value obtained by testing and a preset target value is smaller than a preset threshold value.
An embodiment of the present specification provides a trimming apparatus for a flash memory chip reference circuit, including:
at least one processor; and the number of the first and second groups,
a memory communicatively coupled to the at least one processor; wherein,
the memory stores instructions executable by the at least one processor to cause the at least one processor to:
acquiring probability distribution information of history data of the fine-adjustment gears of the flash memory chip;
setting a first interval range of fine adjustment gear values, and discretizing the fine adjustment gear values in the first interval range according to a preset step length to obtain a first number of fine adjustment gear values;
sorting all fine-adjustment gear values in the first number of fine-adjustment gear values based on the magnitude sequence of the probability values in the probability distribution information to obtain a second number of fine-adjustment gear values consistent with the first number of values;
and selecting to-be-set fine shift values from the second number of fine shift values for the flash memory chips to be tested in sequence, testing the flash memory chips to be tested based on the to-be-set fine shift values, and setting the to-be-set fine shift values as first target fine shift values when the absolute value of the difference between a measured value obtained by testing and a preset target value is smaller than a preset threshold value.
Embodiments of the present specification provide a computer readable medium having stored thereon computer readable instructions executable by a processor to implement a method for trimming a reference circuit of a flash memory chip.
One embodiment of the present description achieves the following advantageous effects:
in the technical scheme of the embodiment, the fine adjustment gear position value of the flash memory chip to be tested is tested based on the probability distribution of the fine adjustment gear position value of the flash memory chip, so that the fine adjustment gear position value meeting the error requirement with the target value of the fine adjustment gear position value can be quickly tested based on the statistical rule, the test time is saved, and the test cost is saved.
Drawings
In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments described in the present application, and for those skilled in the art, other drawings can be obtained according to the drawings without any creative effort.
Fig. 1 is a schematic illustration of a trimming circuit in a trimming method for a reference circuit of a flash memory chip according to an embodiment of the present disclosure;
fig. 2 is a normal distribution diagram of a target value of a trimming stage value obtained through several chip tests in a trimming method of a flash memory chip reference circuit provided in an embodiment of the present disclosure;
FIG. 3 is a flowchart of a trimming method for a reference circuit of a flash memory chip according to an embodiment of the present disclosure;
FIG. 4 is a schematic diagram of a trimming apparatus for a reference circuit of a flash memory chip according to an embodiment of the present disclosure;
fig. 5 is a schematic structural diagram of a trimming device of a flash memory chip reference circuit according to an embodiment of the present disclosure.
Detailed Description
To make the objects, technical solutions and advantages of one or more embodiments of the present disclosure more apparent, the technical solutions of one or more embodiments of the present disclosure will be described in detail and completely with reference to the specific embodiments of the present disclosure and the accompanying drawings. It is to be understood that the embodiments described are only a few embodiments of the present specification, and not all embodiments. All other embodiments that can be derived by a person skilled in the art from the embodiments given herein without making any creative effort fall within the scope of protection of one or more embodiments of the present specification.
The technical solutions provided by the embodiments of the present description are described in detail below with reference to the accompanying drawings.
As shown in fig. 1, fig. 1 is a schematic illustration of a trimming circuit in a trimming method of a flash memory chip reference circuit provided in an embodiment of the present disclosure, and a design principle of trimming of the flash memory chip reference circuit is that a flash memory chip design includes a storage area and a peripheral control circuit, where an internal voltage reference unit controls voltage distribution of a chip. In order to eliminate the influence of the fluctuation of process parameters on the precision of the reference old voltage, the circuit is designed into a micro adjustable mode, and the basic principle is that an NMOS switch circuit selects different divider resistors, so that high-precision voltage control is realized.
The prior art generally tests the fine adjustment gear of the flash memory chip based on a linear scanning method, so that each time the fine adjustment gear is gradually increased from zero until a target fine adjustment gear value is found, more test time and test cost are needed.
In order to solve the defects in the prior art, the scheme provides the following embodiments:
fig. 3 is a schematic flowchart of an overall scheme of a trimming method for a reference circuit of a flash memory chip according to an embodiment of the present disclosure. As shown in fig. 3, the scheme may include:
step S302: and acquiring probability distribution information of the fine-adjustment gear historical data of the flash memory chip.
In the technical solution of this embodiment, the historical data may refer to actual target values of the trimming gear values of the flash memory chips obtained through a certain method test, and then probability distribution information of the actual target values is obtained by using a statistical method, in other words, the purpose of this step is to obtain the probability distribution information of the actual target values of the flash memory chips through the historical data. Taking fig. 2 as an example, fig. 2 is a normal distribution diagram of a target value of a trimming range value obtained through a plurality of chip tests in the trimming method of a flash memory chip reference circuit provided in the embodiment of the present disclosure, and a probability distribution of the target value of the trimming range value can be clearly known through the normal distribution diagram.
Step S304: setting a first interval range of fine shift gear values, and discretizing the fine shift gear values in the first interval range according to a preset step length to obtain a first number of fine shift gear values.
In the technical solution of this embodiment, the first interval range may refer to a candidate value interval of a preset fine shift value, because an actual target value of the fine shift value cannot be determined in advance, an actual fine shift value, that is, a target value of the fine shift value, needs to be tested in the first interval range by a certain method. Because various tests have errors, the upper error limit can be preset, and when the test value of the fine gear value obtained by the test and the target value are smaller than the upper error limit, the test value can be considered to meet the requirement.
Because the numerical values in the first interval range are continuous from the mathematical point of view, the numerical values in the interval range need to be dispersed for the practical engineering requirement to obtain a plurality of discrete values,
step S306: and sequencing all the fine adjustment gear values in the first number of fine adjustment gear values based on the magnitude sequence of the probability values in the probability distribution information to obtain a second number of fine adjustment gear values consistent with the first number of values.
Because the probability distribution information of the fine shift range history data of the flash memory chip has already been obtained in step S302,
in this step, the probability values in the probability distribution information obtained in step S302 are ranked, the probability value with the larger probability value is ranked in the front, the probability value with the smaller probability value is ranked in the back, for example, the probability corresponding to the fine adjustment gear position value of the value 10 is 30%, and the probability is the highest, then the probability of 30% is ranked in the front, in other words, the specific fine adjustment gear position value of the value 10 is ranked in the front.
S308: and selecting to-be-set fine shift values from the second number of fine shift values for the flash memory chips to be tested in sequence, testing the flash memory chips to be tested based on the to-be-set fine shift values, and setting the to-be-set fine shift values as first target fine shift values when the absolute value of the difference between a measured value obtained by testing and a preset target value is smaller than a preset threshold value.
In this step, for a specific flash memory chip, in order to quickly test and obtain a target value of the fine adjustment gear position value of the flash memory chip, the specific flash memory chips are tested one by one based on the fine adjustment gear position value corresponding to the probability value sorted in step S306. Because a certain engineering error exists, a threshold value is preset in the step, when a specific flash memory chip is tested based on a certain fine adjustment gear value, and when the absolute value of the difference value between the measured value obtained by the test and the preset target value is smaller than the preset threshold value, the fine adjustment gear value to be set is set as a first target fine adjustment gear value.
In the technical scheme of the invention, a certain specific fine-tuning gear position value is set for a certain newly manufactured flash memory chip, then the test value of the flash memory chip is measured through a high-precision source table and is compared with a preset target value, and if the absolute value of the difference value is smaller than a certain preset difference value, the test is qualified.
In the technical scheme of the embodiment, the fine adjustment gear position value of the flash memory chip to be tested is tested based on the probability distribution of the fine adjustment gear position value of the flash memory chip, so that the fine adjustment gear position value meeting the error requirement with the target value of the fine adjustment gear position value can be quickly tested based on the statistical rule, the test time is saved, and the test cost is saved.
Further, the optimizing method, wherein the pre-obtaining of the probability distribution information of the fine-tuning shift value of the flash memory chip specifically includes:
pre-acquiring a preset number of flash memory chips, and setting a second interval range consistent with the first interval range;
based on the second interval range, testing the trimming gear values of the preset number of flash memory chips by a linear scanning method to obtain a second target trimming gear value consistent with the preset number of values;
and analyzing the statistical rule of the second target fine adjustment gear value consistent with the preset number of numerical values to obtain the probability distribution information of the actual fine adjustment gear values of the preset number of flash memory chips.
In this step, the target values of the fine adjustment gear values of a large number of flash memory chips are obtained by testing the fine adjustment gear values of the large number of flash memory chips through a linear scanning method, so that the distribution rule of the fine adjustment gear values of the flash memory chips is obtained according to the data and a statistical method.
And further optimizing the scheme, wherein the probability distribution information of the actual fine-adjustment gear position is normal distribution probability information of the actual fine-adjustment gear position.
In a further preferred embodiment, the predetermined number of flash memory chips is in the range of 1000 to 20000.
In the technical scheme of the embodiment, the statistical regularity of the target value of the fine-adjustment gear is expected to be obtained from the target values of the fine-adjustment gears of the plurality of flash memory chips, so that the statistical regularity is conveniently utilized in the subsequent stage, and when the fine-adjustment gear value of a specific flash memory chip is tested, the specific fine-adjustment gear target value of the flash memory chip is quickly tested. According to statistical principles, statistical regularity, i.e. the inherent regularity exhibited in a large number of repeated tests or observations, is only revealed when there are a sufficient number of test samples. Therefore, in the technical solution of the present embodiment, it is optional to limit the number of the predetermined number of flash memory chips to be in a range of 1000 to 20000. Taking the number of the flash memory chips with the preset number as 1000 as an example, the historical data of the fine-adjustment gear target value of the flash memory chips produced in a production workshop can be recorded and obtained, taking the number of the flash memory chips with the preset number as 20000 as an example, the number value is large, the historical data of the fine-adjustment gear target value of the flash memory chips with the same production environment and the same model in different batches in a factory can be recorded and obtained, and specifically, the historical data of the fine-adjustment gear target value can be obtained according to the linear scanning method described above.
It should be noted that, in the technical solution of the present embodiment, it is not intended to indicate that the number of flash memory chips used for obtaining the history data of the fine adjustment target value must be between 1000 and 20000, which is only the range of the number of flash memory chips that the inventor needs to test in advance, according to the model and the production environment of the flash memory chip aimed at by the inventor, the obtained distribution rule capable of obtaining the fine adjustment target value in actual engineering practice. The number of the flash memory chips required for obtaining the distribution rule of the fine adjustment gear target value may be changed due to different production environments for producing the flash memory chips, different specific models of the produced flash memory chips and the like, so that according to the technical concept of the invention, the number range of other flash memory chips required for obtaining the distribution rule of the fine adjustment gear target value is also within the protection range of the technical scheme of the invention.
Based on the same idea, the embodiment of the present specification further provides a device corresponding to the above method. Fig. 4 is a schematic structural diagram of a trimming apparatus of a flash memory chip reference circuit corresponding to fig. 3 according to an embodiment of the present disclosure. As shown in fig. 4, the apparatus may include:
a fine gear value probability distribution obtaining module 402, configured to obtain probability distribution information of the historical data of the fine gear of the flash memory chip.
And the fine adjustment gear value discretization module 404 is used for setting a first interval range of the fine adjustment gear value, discretizing the fine adjustment gear value in the first interval range according to a preset step length, and obtaining the fine adjustment gear values of the first quantity.
And a fine shift value sorting module 406, configured to sort all fine shift values in the first number of fine shift values based on a magnitude order of the probability values in the probability distribution information, so as to obtain a second number of fine shift values that are consistent with the first number of values.
And the fine adjustment gear value testing module 408 is configured to select, for the flash memory chips to be tested, a fine adjustment gear value to be set from the second number of fine adjustment gear values in sequence, test the flash memory chips to be tested based on the fine adjustment gear value to be set, and set the fine adjustment gear value to be set as a first target fine adjustment gear value when an absolute value of a difference between a measured value obtained by the test and a preset target value is smaller than a predetermined threshold value.
Based on the same idea, the embodiment of the present specification further provides a device corresponding to the above method.
Fig. 5 is a schematic structural diagram of a trimming device corresponding to the flash memory chip reference circuit of fig. 3 according to an embodiment of the present disclosure. As shown in fig. 5, the apparatus 500 may include:
at least one processor 510; and the number of the first and second groups,
a memory 530 communicatively coupled to the at least one processor; wherein,
the memory 530 stores instructions 520 executable by the at least one processor 510 to enable the at least one processor 510 to:
acquiring probability distribution information of history data of the fine-adjustment gears of the flash memory chip;
setting a first interval range of fine adjustment gear values, and discretizing the fine adjustment gear values in the first interval range according to a preset step length to obtain a first number of fine adjustment gear values;
sorting all fine-adjustment gear values in the first number of fine-adjustment gear values based on the magnitude sequence of the probability values in the probability distribution information to obtain a second number of fine-adjustment gear values consistent with the first number of values;
and selecting to-be-set fine shift values from the second number of fine shift values for the flash memory chips to be tested in sequence, testing the flash memory chips to be tested based on the to-be-set fine shift values, and setting the to-be-set fine shift values as first target fine shift values when the absolute value of the difference between a measured value obtained by testing and a preset target value is smaller than a preset threshold value.
Based on the same idea, the embodiment of the present specification further provides a computer-readable medium corresponding to the above method. The computer readable medium has computer readable instructions stored thereon that are executable by a processor to implement the method of:
acquiring probability distribution information of history data of the fine-adjustment gears of the flash memory chip;
setting a first interval range of fine adjustment gear values, and discretizing the fine adjustment gear values in the first interval range according to a preset step length to obtain a first number of fine adjustment gear values;
sorting all fine-adjustment gear values in the first number of fine-adjustment gear values based on the magnitude sequence of the probability values in the probability distribution information to obtain a second number of fine-adjustment gear values consistent with the first number of values;
and selecting to-be-set fine shift values from the second number of fine shift values for the flash memory chips to be tested in sequence, testing the flash memory chips to be tested based on the to-be-set fine shift values, and setting the to-be-set fine shift values as first target fine shift values when the absolute value of the difference between a measured value obtained by testing and a preset target value is smaller than a preset threshold value.
All the embodiments in the present specification are described in a progressive manner, and the same and similar parts among the embodiments may be referred to each other, and the related parts may be referred to the parts of the description of the method embodiments.
In the 90's of the 20 th century, improvements to a technology could clearly distinguish between improvements in hardware (e.g., improvements to circuit structures such as diodes, transistors, switches, etc.) and improvements in software (improvements to process flow). However, as technology advances, many of today's process flow improvements have been seen as direct improvements in hardware circuit architecture. Designers almost always obtain the corresponding hardware circuit structure by programming an improved method flow into the hardware circuit. Thus, it cannot be said that an improvement in the process flow cannot be realized by hardware physical modules. For example, a Programmable Logic Device (PLD), such as a Field Programmable Gate Array (FPGA), is an integrated circuit whose Logic functions are determined by programming the Device by a user. A digital character system is "integrated" on a PLD by the designer's own programming without requiring the chip manufacturer to design and fabricate a dedicated integrated circuit chip. Furthermore, nowadays, instead of manually making an Integrated Circuit chip, such Programming is often implemented by "logic compiler" software, which is similar to a software compiler used in program development and writing, but the original code before compiling is also written by a specific Programming Language, which is called Hardware Description Language (HDL), and HDL is not only one but many, such as abel (advanced Boolean Expression Language), ahdl (alternate Hardware Description Language), traffic, pl (core universal Programming Language), HDCal (jhdware Description Language), lang, Lola, HDL, laspam, hardward Description Language (vhr Description Language), vhal (Hardware Description Language), and vhigh-Language, which are currently used in most common. It will also be apparent to those skilled in the art that hardware circuitry that implements the logical method flows can be readily obtained by merely slightly programming the method flows into an integrated circuit using the hardware description languages described above.
The controller may be implemented in any suitable manner, for example, the controller may take the form of, for example, a microprocessor or processor and a computer-readable medium storing computer-readable program code (e.g., software or firmware) executable by the (micro) processor, logic gates, switches, an Application Specific Integrated Circuit (ASIC), a programmable logic controller, and an embedded microcontroller, examples of which include, but are not limited to, the following microcontrollers: ARC 625D, Atmel AT91SAM, Microchip PIC18F26K20, and Silicone Labs C8051F320, the memory controller may also be implemented as part of the control logic for the memory. Those skilled in the art will also appreciate that, in addition to implementing the controller as pure computer readable program code, the same functionality can be implemented by logically programming method steps such that the controller is in the form of logic gates, switches, application specific integrated circuits, programmable logic controllers, embedded microcontrollers and the like. Such a controller may thus be considered a hardware component, and the means included therein for performing the various functions may also be considered as a structure within the hardware component. Or even means for performing the functions may be conceived to be both a software module implementing the method and a structure within a hardware component.
The systems, devices, modules or units illustrated in the above embodiments may be implemented by a computer chip or an entity, or by a product with certain functions. One typical implementation device is a computer. In particular, the computer may be, for example, a personal computer, a laptop computer, a cellular telephone, a camera phone, a smartphone, a personal digital assistant, a media player, a navigation device, an email device, a game console, a tablet computer, a wearable device, or a combination of any of these devices.
For convenience of description, the above devices are described as being divided into various units by function, and are described separately. Of course, the functionality of the units may be implemented in one or more software and/or hardware when implementing the present application.
As will be appreciated by one skilled in the art, embodiments of the present invention may be provided as a method, system, or computer program product. Accordingly, the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present invention may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.
The present invention is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
In a typical configuration, a computing device includes one or more processors (CPUs), input/output interfaces, network interfaces, and memory.
The memory may include forms of volatile memory in a computer readable medium, Random Access Memory (RAM) and/or non-volatile memory, such as Read Only Memory (ROM) or flash memory (flash RAM). Memory is an example of a computer-readable medium.
Computer-readable media, including both non-transitory and non-transitory, removable and non-removable media, may implement information storage by any method or technology. The information may be computer readable instructions, data structures, modules of a program, or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), Static Random Access Memory (SRAM), Dynamic Random Access Memory (DRAM), other types of Random Access Memory (RAM), Read Only Memory (ROM), Electrically Erasable Programmable Read Only Memory (EEPROM), flash memory or other memory technology, compact disc read only memory (CD-ROM), Digital Versatile Disks (DVD) or other optical storage, magnetic cassettes, magnetic tape disk storage or other magnetic storage devices, or any other non-transmission medium which can be used to store information which can be accessed by a computing device. As defined herein, a computer readable medium does not include a transitory computer readable medium such as a modulated data signal and a carrier wave.
It should also be noted that the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
As will be appreciated by one skilled in the art, embodiments of the present application may be provided as a method, system, or computer program product. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.
The application may be described in the general context of computer-executable instructions, such as program modules, being executed by a computer. Generally, program modules include routines, programs, objects, components, data structures, etc. that perform particular tasks or implement particular abstract data types. The application may also be practiced in distributed computing environments where tasks are performed by remote processing devices that are linked through a communications network. In a distributed computing environment, program modules may be located in both local and remote computer storage media including memory storage devices.
The above description is only an example of the present application and is not intended to limit the present application. Various modifications and changes may occur to those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included in the scope of the claims of the present application.
Claims (7)
1. A method for trimming a reference circuit of a flash memory chip, the method comprising:
acquiring probability distribution information of history data of the fine-adjustment gears of the flash memory chip;
setting a first interval range of fine adjustment gear values, and discretizing the fine adjustment gear values in the first interval range according to a preset step length to obtain a first number of fine adjustment gear values;
sorting all fine-adjustment gear values in the first number of fine-adjustment gear values based on the magnitude sequence of the probability values in the probability distribution information to obtain a second number of fine-adjustment gear values consistent with the first number of values;
and selecting to-be-set fine shift values from the second number of fine shift values for the flash memory chips to be tested in sequence, testing the flash memory chips to be tested based on the to-be-set fine shift values, and setting the to-be-set fine shift values as first target fine shift values when the absolute value of the difference between a measured value obtained by testing and a preset target value is smaller than a preset threshold value.
2. The method according to claim 1, wherein the pre-obtaining of the probability distribution information of the fine-tuning shift values of the flash memory chip specifically comprises:
pre-acquiring a preset number of flash memory chips, and setting a second interval range consistent with the first interval range;
based on the second interval range, testing the fine adjustment gear values of the preset number of flash memory chips by a linear scanning method to obtain a second target fine adjustment gear value consistent with the preset number of values;
and analyzing the statistical rule of the second target fine adjustment gear value consistent with the preset number of numerical values to obtain the probability distribution information of the actual fine adjustment gear values of the preset number of flash memory chips.
3. The method of claim 2, wherein the probability distribution information of the actual fine shift level value is a normal distribution probability information of the actual fine shift level value.
4. The method of claim 2, wherein the predetermined number of flash memory chips is in a range of 1000 to 20000.
5. A trimming apparatus for a flash memory chip reference circuit, comprising:
the fine-adjustment gear value probability distribution acquisition module is used for acquiring probability distribution information of the fine-adjustment gear historical data of the flash memory chip;
the fine shift value discretization module is used for setting a first interval range of fine shift values, and discretizing the fine shift values in the first interval range according to preset step length to obtain a first number of fine shift values;
the fine shift value sequencing module is used for sequencing all fine shift values in the first number of fine shift values based on the magnitude sequence of the probability values in the probability distribution information to obtain a second number of fine shift values consistent with the first number of values;
and the fine shift value testing module is used for selecting a fine shift value to be set from the second number of fine shift values in sequence for the flash memory chips to be tested, testing the flash memory chips to be tested based on the fine shift value to be set, and setting the fine shift value to be set as a first target fine shift value when the absolute value of the difference between the measured value obtained by testing and a preset target value is smaller than a preset threshold value.
6. A trimming device for a flash memory chip reference circuit, comprising:
at least one processor; and the number of the first and second groups,
a memory communicatively coupled to the at least one processor; wherein,
the memory stores instructions executable by the at least one processor to enable the at least one processor to:
acquiring probability distribution information of history data of the fine-adjustment gears of the flash memory chip;
setting a first interval range of fine adjustment gear values, and discretizing the fine adjustment gear values in the first interval range according to a preset step length to obtain a first number of fine adjustment gear values;
sorting all fine-adjustment gear values in the first number of fine-adjustment gear values based on the magnitude sequence of the probability values in the probability distribution information to obtain a second number of fine-adjustment gear values consistent with the first number of values;
and selecting to-be-set fine shift values from the second number of fine shift values for the flash memory chips to be tested in sequence, testing the flash memory chips to be tested based on the to-be-set fine shift values, and setting the to-be-set fine shift values as first target fine shift values when the absolute value of the difference between a measured value obtained by testing and a preset target value is smaller than a preset threshold value.
7. A computer readable medium having computer readable instructions stored thereon which are executable by a processor to implement the method of trimming the flash chip reference circuit of any one of claims 1 to 4.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN115910190A (en) * | 2022-12-05 | 2023-04-04 | 海光集成电路设计(北京)有限公司 | Chip yield prediction method and device and computer readable storage medium |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN115910190A (en) * | 2022-12-05 | 2023-04-04 | 海光集成电路设计(北京)有限公司 | Chip yield prediction method and device and computer readable storage medium |
| CN115910190B (en) * | 2022-12-05 | 2023-08-18 | 海光集成电路设计(北京)有限公司 | Chip yield prediction method and device and computer readable storage medium |
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