CN116487440A - SiC MOSFET device - Google Patents

Abstract

The application discloses SiC MOSFET device sets up the slot through the surface that deviates from the substrate at the epitaxial layer, and sets up grid and the shielded gate that is located grid and is close to drain electrode one side in the slot to introduce the shielded gate between grid and drain electrode, reduce the overlap area between grid and the drain electrode, and then reduce gate-drain capacitance. And, set up the shielding bars and include along the at least two-layer doped layer of perpendicular to direction of slot bottom range upon range of, and the doping type of adjacent two-layer doped layer is opposite, and the one deck doped layer that is closest to slot bottom or the one deck doped layer that is furthest from slot bottom in the shielding bars is connected with the source electricity for adjacent two-layer doped layer forms PN junction in the shielding bars, and the introduction of the junction capacitance of PN junction, make the electric capacity between shielding bars and the drain have the space that reduces, consequently, the SiC MOSFET device that this application provided can solve the too big problem of source leakage electric capacity when reducing gate leakage electric capacity, and then can reduce the switching loss.

Description

SiC MOSFET device

Technical Field

The application relates to the technical field of semiconductors, in particular to a SiC MOSFET device.

Background

Silicon Carbide (SiC) material is one of the representatives of the third generation wide bandgap semiconductor materials, has the characteristics of large bandgap, high critical breakdown electric field, high thermal conductivity, high electron saturation drift velocity and the like, and has wide application prospect in the fields of high power, high temperature, high frequency power electronics and the like. The application range of the SiC power device is wider than that of a SiC MOSFET device, and the SiC MOSFET device has two typical gate structures: the planar gate and the trench gate have no JFET region, so that on-resistance is reduced, the cell area is reduced, and the integration level of a chip is improved, and therefore, the development potential is huge.

When a SiC MOSFET device is in operation, there are typically two loss: conduction loss and switching loss. The shielding gate structure is introduced into the trench gate SiC MOSFET device, so that the doping concentration of the drift region can be allowed to be greatly improved compared with that of the conventional trench gate SiC MOSFET device, the on-resistance is greatly reduced, the on-loss is further reduced, and the introduced shielding gate structure reduces the overlapping area of the gate and the drain electrode, so that the gate-drain capacitance C is further reduced _GD The switching loss of the device is improved. However, since the shield gate structure is connected to the source, the capacitance C is inevitably generated between the source and the drain _DS Introducing capacitance caused by overlap of shield gate structure and drain electrode, i.e. increasing source-drain capacitance C _DS And capacitor C _DS Is a capacitor C _GD About 1000 times, thereby limiting the reduction of switching losses.

Therefore, how to reduce the gate-drain capacitance C _GD Is to solve the source-drain capacitance C at the same time _DS The excessive problem, and thus the reduced switching loss, is a technical problem to be solved by the skilled person.

Disclosure of Invention

The embodiment of the application provides a SiC MOSFET device for reducing the grid-drain capacitance C _GD Is to solve the source-drain capacitance C at the same time _DS And the excessive problem is solved, so that the switching loss is reduced.

In order to achieve the above purpose, the embodiment of the present application provides the following technical solutions:

a SiC MOSFET device, comprising:

a substrate;

an epitaxial layer located on one side of the substrate;

the source electrode is positioned on one side of the epitaxial layer, which is away from the substrate, and the drain electrode is positioned on one side of the substrate, which is away from the epitaxial layer;

a groove is formed in the surface, deviating from the substrate, of the epitaxial layer, a grid electrode and a shielding grid positioned on one side, close to the drain electrode, of the grid electrode are arranged in the groove, and insulating oxide layers are arranged on the side wall and the bottom of the groove, between the grid electrode and the shielding grid and between the grid electrode and the source electrode;

the shielding grid comprises at least two doped layers which are stacked along the direction perpendicular to the bottom of the groove, the doping types of the adjacent two doped layers are opposite, and one doped layer closest to the bottom of the groove or one doped layer farthest from the bottom of the groove in the shielding grid is electrically connected with the source electrode.

Optionally, the doping concentration of one doping layer electrically connected with the source electrode in the shielding gate is larger than the doping concentration of other doping layers.

Optionally, in the shielding gate, the doping concentration of each doping layer gradually decreases along a direction away from one doping layer electrically connected with the source electrode.

Optionally, the doping concentration of a doped layer electrically connected with the source electrode in the shielding gate ranges from 1×10 ²⁰ cm ^-3 -1×10 ²¹ cm ^-3 Including endpoint values.

Optionally, each doped layer in the shielding gate is a polysilicon doped layer.

Optionally, the epitaxial layer includes a drift region, a base region and a first source region sequentially arranged along a direction away from the substrate, and the trench extends into the drift region;

the base region and the first source region are arranged corresponding to the grid electrode, and a first channel region is arranged at one side of the base region, which is close to the grid electrode;

the base region and the first source region are both electrically connected with the source electrode.

Optionally, the drift region includes a first drift region and a second drift region sequentially arranged along a direction away from the substrate, and a doping concentration of the second drift region is greater than that of the first drift region;

the trench extends into the second drift region.

Optionally, the base region and the first source region are located at one side of the trench, and the second drift region surrounds part of the bottom of the trench;

the epitaxial layer further comprises a second source region and a second channel region;

the second source region is positioned at one side of the groove away from the first source region and the base region, the second source region is electrically connected with the source electrode, and the second source region extends to one side of the groove close to the substrate in an L shape;

the second channel region is located at one side of the groove close to the substrate, and the second channel region is communicated with the second source region and the second drift region.

Optionally, the epitaxial layer further includes a well region, and the well region includes a first well region and a second well region;

the first well region is positioned at one side of the first source region, the base region and the first drift region, which is away from the groove;

the second well region is located at one side of the second source region and the second channel region away from the groove.

Optionally, the doping concentration of the first source region is in a range of 1×10 ¹⁸ cm ^-3 -3×10 ¹⁸ cm ^-3 Including endpoint values.

Compared with the prior art, the technical scheme has the following advantages:

the SiC MOSFET device comprises a substrate, an epitaxial layer positioned on one side of the substrate, a source electrode positioned on one side of the epitaxial layer, which is far away from the substrate, and a drain electrode positioned on one side of the substrate, which is far away from the epitaxial layer, wherein a groove is formed in the surface of the epitaxial layer, which is far away from the substrate, and a grid electrode and a shielding grid positioned on one side of the grid electrode, which is close to the drain electrode, are arranged in the groove, so that the shielding grid is introduced between the grid electrode and the drain electrode, the overlapping area between the grid electrode and the drain electrode is reduced, and the grid-drain capacitance C is further reduced _GD . But since the shield gate is electrically connected to the source, this will be at the source-drain capacitance C _DS Introducing capacitance caused by overlap of shield gate and drain, at this time, source-drain capacitance C _DS Not only includes the capacitance C between the source and the drain _DS1 Also comprises a capacitor C between the shielding gate and the drain electrode _DS2 。

Based on the above, the shielding grid is further provided with at least two doped layers stacked along the direction perpendicular to the bottom of the trench, the doping types of the two adjacent doped layers are opposite, one doped layer closest to the bottom of the trench or one doped layer farthest from the bottom of the trench in the shielding grid is electrically connected with the source electrode, so that the two adjacent doped layers in the shielding grid form a PN junction, and specifically, taking the example that one doped layer farthest from the bottom of the trench in the shielding grid is electrically connected with the source electrode, then the capacitor C between the shielding grid and the drain electrode _DS2 Comprising capacitance C between a doped layer of the shield gate furthest from the bottom of the trench and the drain _SP1 Capacitance C between a doped layer closest to the bottom of the trench and the drain in the shield gate _SP2 Junction capacitance C of PN junctions in shield gate _J And the capacitance C between the doped layer closest to the bottom of the trench and the drain electrode in the shield gate _SP2 Junction capacitance C with each PN junction in the shield gate _J The capacitor C is connected in series with the doped layer of the shielding grid furthest from the bottom of the trench and the drain electrode _SP1 In parallel, thereby forming a capacitance C between the shield gate and the drain _DS2 Because the capacitance value of the whole series capacitor is smaller than that of each part of the series capacitor, the capacitance C between the shielding grid and the drain electrode can be reduced _DS2 Enter intoWhile reducing the overall source-drain capacitance C _DS 。

Therefore, the SiC MOSFET device provided by the embodiment of the application can reduce the gate-drain capacitance C _GD Is to solve the source-drain capacitance C at the same time _DS The excessive problem, in turn, can reduce switching losses.

Drawings

In order to more clearly illustrate the embodiments of the invention or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described, it being obvious that the drawings in the following description are only some embodiments of the invention, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

Fig. 1 is a schematic cross-sectional structure of a prior art shielded gate SiC MOSFET device;

fig. 2 is an equivalent circuit schematic diagram of parasitic capacitance of the shielded gate SiC MOSFET device shown in fig. 1;

fig. 3 is a schematic cross-sectional structure of a SiC MOSFET device according to an embodiment of the present application;

fig. 4 is an enlarged schematic diagram of a shielding gate including two doped layers in a SiC MOSFET device according to an embodiment of the present application;

fig. 5 is an equivalent circuit schematic diagram of parasitic capacitance of a SiC MOSFET device provided in the embodiment of the present application when a shield gate includes two doped layers;

fig. 6 is an enlarged schematic diagram of a SiC MOSFET device according to an embodiment of the present application, where the shield gate includes three doped layers;

fig. 7 is an equivalent circuit schematic diagram of parasitic capacitance of a SiC MOSFET device provided in an embodiment of the present application when a shield gate includes three doped layers;

fig. 8 is a schematic cross-sectional structure of another SiC MOSFET device according to an embodiment of the present application.

Detailed Description

The following description of the embodiments of the present application will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are only some, but not all, of the embodiments of the present application. All other embodiments, which can be made by one of ordinary skill in the art without undue burden from the present disclosure, are within the scope of the present disclosure.

In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present application, but the present application may be practiced in other ways other than those described herein, and persons skilled in the art will readily appreciate that the present application is not limited to the specific embodiments disclosed below.

Next, the present application will be described in detail with reference to the schematic drawings, wherein the cross-sectional views of the device structure are not drawn to scale for the convenience of illustration, and the schematic drawings are merely examples, which should not limit the scope of protection of the present application. In addition, the three-dimensional dimensions of length, width and depth should be included in actual fabrication.

As described in the background section, siC MOSFET devices generally operate with two loss components: conduction loss and switching loss. In the on state, a loss occurs when current flows through the device due to the on-resistance of the device itself, and this loss is referred to as an on-loss. During switching of the device, the voltage and current cannot jump to zero, and the overlapping parts of the voltage and current waveforms generate power dissipation, which results in energy loss, which is called switching loss.

To reduce the conduction loss and the switching loss, a shielding gate structure can be introduced into the trench gate SiC MOSFET device to form a shielding gate SiC MOSFET device, specifically, fig. 1 shows a schematic cross-sectional structure of a prior art shielding gate SiC MOSFET device, as shown in fig. 1, which includes N ⁺ Substrate 01 and located at N ⁺ An epitaxial layer 02 on one side of the substrate 01, the epitaxial layer 02 including an N drift region 021, a P well region 022, a P base region 023, and N ⁺ Source region 024, epitaxial layer 02 facing away from N ⁺ The surface of the substrate 01 is provided with grooves 025 andthe trench 025 extends into the N drift region 021, an insulating oxide layer 026 is grown on the bottom and side walls of the trench 025, and the insulating oxide layer 026 surrounds the gate G and is positioned near N ⁺ A shielding grid SG on one side of the substrate 01 and isolated from the grid G by an insulating oxide layer 026, and an epitaxial layer 02 facing away from N ⁺ Source S and source N on one side of substrate 01 ⁺ The substrate 01 is separated from the drain electrode D on the side of the epitaxial layer 02 by an insulating oxide layer 026, and the gate electrode G and the source electrode S are also isolated, wherein the shielding gate SG is a single N-type doped polysilicon structure, and the shielding gate SG is electrically connected with the source electrode, so that the shielding gate SG is also called a source polysilicon structure.

For the shielded gate SiC MOSFET device shown in FIG. 1, based on the charge compensation effect, the doping concentration of the N drift region 021 can be allowed to be greatly increased compared with that of the traditional trench gate SiC MOSFET device through the auxiliary depletion effect of the shielded gate SG penetrating into the N drift region 021, so that the on-resistance of the device is greatly reduced, and the on-loss is improved from the device structure per se.

And, compared with the conventional trench gate SiC MOSFET device, in the shielded gate SiC MOSFET device shown in FIG. 1, the shielded gate SG is positioned between the gate G and the drain D, so that the overlapping area of the gate G and the drain D of the device is reduced, thereby reducing the gate-drain capacitance C _GD The switching loss of the device is also improved. But because the shielding gate SG is electrically connected with the source S, the overlapping area of the source S and the drain D is increased, namely, the grid-drain power supply C is reduced _GD At the same time, inevitably increases the source-drain capacitance C _DS And capacitor C _DS Is a capacitor C _GD About 1000 times, so that the total output charge is increased, the turn-off time of the device is prolonged, and the reduction of the switching loss is further limited.

For ease of understanding, FIG. 2 shows an equivalent circuit schematic diagram of the parasitic capacitance of the shielded gate SiC MOSFET device shown in FIG. 1, including the gate-drain capacitance C, as shown in connection with FIGS. 1 and 2 _GD Source drain capacitance C _DS Sum gate source capacitance C _GS Wherein, due to the introduction of the shielding gate SG, the gate-drain capacitance C of the overlapped part of the original gate G and the drain D _GD The source-drain capacitance C of the device is reduced because the shielding gate SG is electrically connected with the source S, i.e. the shielding gate SG is equipotential with the source S _DS Capacitor C including not only the original overlapping portion of source S and drain D _DS1 Also comprises a capacitor C at the overlapping part of the bottom of the shielding grid SG and the drain electrode D _DS2 I.e. in reducing the gate leakage power C _GD At the same time, inevitably increases the source-drain capacitance C _DS 。

In addition, the gate-source capacitance C of the device _GS Capacitance of overlapping part of grid G and P base region 023 of groove side wall originally, grid G and N of groove side wall ⁺ Capacitance of the overlapped portion of the source region 024, and sum C of capacitance of the overlapped portion of the gate G and the source S via the insulating oxide 026 _GS1 Due to the existence of the shielding gate SG below the gate G and the electrical connection of the shielding gate SG and the source S, the gate-source capacitance C of the device _GS The capacitance C of the overlapping part of the grid G and the shielding grid SG is also increased _GS2 Here, the thickness of the insulating oxide layer 026 between the gate electrode G and the shielding gate electrode SG is equal to the capacitance C of the overlapping portion of the gate electrode G and the shielding gate electrode SG _GS2 With greater impact, a thicker insulating oxide layer 026 can be used to reduce the gate-source capacitance C _GS2 。

Therefore, how to reduce the gate-drain capacitance C _GD Is to solve the source-drain capacitance C at the same time _DS The excessive problem, and thus the reduction of switching losses, is a technical problem to be solved by the person skilled in the art.

Based on the above study, the embodiment of the present application provides a SiC MOSFET device, and fig. 3 shows a schematic cross-sectional structure of the SiC MOSFET device provided in the embodiment of the present application, as shown in fig. 3, where the SiC MOSFET device includes:

a substrate 10;

an epitaxial layer 20 on one side of the substrate 10;

a source electrode S located on the side of the epitaxial layer 20 facing away from the substrate 10 and a drain electrode D located on the side of the substrate 10 facing away from the epitaxial layer 20;

a groove 21 is formed in the surface, facing away from the substrate 10, of the epitaxial layer 20, a grid G and a shielding grid SG positioned on one side, close to the drain D, of the grid G are arranged in the groove 21, and an insulating oxide layer 22 is arranged on the side wall and the bottom of the groove 21, between the grid G and the shielding grid SG and between the grid G and the source S;

the shielding gate SG includes at least two doped layers stacked in a direction perpendicular to the bottom of the trench 21, the doping types of adjacent two doped layers are opposite, and one doped layer closest to the bottom of the trench 21 or one doped layer farthest from the bottom of the trench in the shielding gate SG is electrically connected to the source S.

Alternatively, the substrate 10 may be a SiC substrate, which may be N ⁺ Doping.

Alternatively, as shown in fig. 3, the epitaxial layer 20 may include a drift region 23, a base region 24 and a first source region 25 sequentially arranged in a direction away from the substrate 10, and the trench 21 extends into the drift region 23, where the drift region 23 may be N-doped, the base region 24 may be P-doped, and the first source region 25 may be N ⁺ Doping. The base region 24 and the first source region 25 are disposed corresponding to the gate G, and a side of the base region 24 close to the gate G is a first channel region. In addition, the base region 24 and the first source region 25 are electrically connected to the source S, wherein the surface of the first source region 25 facing away from the substrate 10 is in contact with the source S, such that the first source region 25 is electrically connected to the source S, and the first source region 25 may be N ⁺ Doping to form good ohmic contact with the source S; base region 24 may be electrically connected to source S through well region 26.

When the device is turned on in the forward direction, the base region 24 forms an inversion channel region (i.e., the first channel region) on the side near the gate G, so that electron flow flows from the source S, through the first source region 25, the inversion channel region in the base region 24, the drift region 23, and the substrate 10, and finally to the drain D.

As shown in fig. 3, in the SiC MOSFET device provided in the embodiment of the present application, a trench 21 is provided on a surface of an epitaxial layer 20 facing away from a substrate 10, and a gate G and a shielding gate SG located on a side of the gate G near a drain D are provided in the trench 21, so that the shielding gate SG is introduced between the gate G and the drain D, an overlapping area between the gate G and the drain D is reduced, and a gate-drain capacitance C is further reduced _GD 。

However, since the shielding gate SG needs to be electrically connected to the source S, this will be at the source-drain capacitance C _DS Introducing capacitance caused by overlapping part of shielding gate SG and drain D, at this time, source-drain capacitance C _DS Not only includes the capacitance C between the source S and the drain D _DS1 Also comprises a capacitor C between the shielding gate SG and the drain D _DS2 。

Based on this, unlike the conventional shielding gate having a single doping structure, in the SiC MOSFET device provided in the embodiment of the present application, as shown in fig. 3, the shielding gate SG further includes at least two doped layers stacked along a direction perpendicular to the bottom of the trench, and doping types of adjacent two doped layers are opposite, and one doped layer closest to the bottom of the trench or one doped layer farthest from the bottom of the trench in the shielding gate SG is electrically connected to the source S, so that the adjacent two doped layers in the shielding gate form a PN junction.

It should be noted that, for any two adjacent doped layers in the shielding gate SG, one doped layer is P-type doped, and the other doped layer is N-type doped, so that after one doped layer closest to the bottom of the trench or one doped layer farthest from the bottom of the trench in the shielding gate SG is electrically connected with the source S, any two adjacent doped layers form a PN junction.

It should be further noted that if the doped layer closest to the bottom of the trench in the shielding gate SG is electrically connected to the source S, the doped layer closest to the bottom of the trench 21 in the shielding gate SG is equipotential with the source S. Similarly, if the doped layer of the shielding gate SG furthest from the bottom of the trench 21 is electrically connected to the source S, the doped layer of the shielding gate SG furthest from the bottom of the trench 21 is equipotential with the source S.

It should be noted that the doped layer closest to the bottom of trench 21 or the doped layer furthest from the bottom of trench 21 in shield gate SG is electrically connected to source S at the device termination position.

Specifically, taking an example that the shielding gate SG includes two doped layers, and a doped layer farthest from the bottom of the trench 21 in the shielding gate SG is electrically connected to the source S, fig. 4 shows an enlarged schematic diagram of the two doped layers in the SiC MOSFET device provided in the embodiment of the present application, and fig. 5 further shows an equivalent circuit schematic diagram of parasitic capacitance of the SiC MOSFET device, where, in a direction away from the bottom of the trench 21, the 1 st doped layer may be an N-type doped layer, and the 2 nd doped layer may be a P-type doped layer; alternatively, the 1 st doped layer may be a P-type doped layer, and the 2 nd doped layer may be an N-type doped layer, and in summary, the doping types of the 1 st doped layer and the 2 nd doped layer are opposite.

As shown in fig. 4 and 5, the 2 nd doped layer is electrically connected with the source electrode S, i.e. the 2 nd doped layer and the source electrode S are equipotential, then the capacitance C between the shielding gate SG and the drain electrode D _DS2 Comprising capacitance C between the doped layer 2 and the drain D _SP1 Capacitance C between layer 1 doped layer and drain D _SP2 And PN junction capacitance C between the 1 st doped layer and the 2 nd doped layer _J1 And, a capacitance C between the 1 st doped layer and the drain D _SP2 PN junction capacitance C between doped layer 1 and doped layer 2 _J1 After being connected in series, the capacitor C between the 2 nd doped layer and the drain electrode D _SP1 In parallel, thereby forming a capacitance C between the shielding gate SG and the drain D _DS2 Because the capacitance value of the whole series capacitor is smaller than that of each part of the series capacitor, the capacitance C between the shielding gate SG and the drain D can be reduced _DS2 Thereby reducing the overall source-drain capacitance C _DS 。

Taking the case that the shielding gate SG comprises three doped layers, and a doped layer farthest from the bottom of the trench 21 in the shielding gate SG is electrically connected with the source S as an example, fig. 6 shows an enlarged schematic diagram of the three doped layers in the SiC MOSFET device provided in the embodiment of the present application, and fig. 7 further shows an equivalent circuit schematic diagram of the parasitic capacitance of the SiC MOSFET device, where, in a direction away from the bottom of the trench 21, the 1 st doped layer may be an N-type doped layer, the 2 nd doped layer may be a P-type doped layer, and the 3 rd doped layer may be an N-type doped layer; alternatively, the 1 st doped layer may be a P-type doped layer, the 2 nd doped layer may be an N-type doped layer, the 3 rd doped layer may be a P-type doped layer, and in summary, the doping types of the 1 st doped layer and the 2 nd doped layer are opposite, and the doping types of the 2 nd doped layer and the 3 rd doped layer are opposite.

As shown in combination with fig. 6 and 7, layer 3 doped layer and sourceThe electrode S is electrically connected, i.e. the 3 rd doped layer is equipotential with the source S, then the capacitance C between the gate SG and the drain D is shielded _DS2 Comprising capacitance C between the 3 rd doped layer and drain D _SP1 Capacitance C between layer 1 doped layer and drain D _SP2 PN junction capacitance C between doped layer 1 and doped layer 2 _J1 And PN junction capacitance C between the 2 nd doped layer and the 3 rd doped layer _J2 And, a capacitance C between the 1 st doped layer and the drain D _SP2 PN junction capacitance C between doped layer 1 and doped layer 2 _J And PN junction capacitance C between the 2 nd doped layer and the 3 rd doped layer _J2 After being connected in series, the capacitor C between the 3 rd doped layer and the drain electrode D _SP1 In parallel, thereby forming a capacitance C between the shielding gate SG and the drain D _DS2 Because the capacitance value of the whole series capacitor is smaller than that of each part of the series capacitor, the capacitance C between the shielding gate SG and the drain D can be reduced _DS2 Thereby reducing the overall source-drain capacitance C _DS 。

It will be appreciated that the more layers of doped layers are included in the shielding gate SG, the more PN junction capacitance is in series, so that the capacitance C between the shielding gate SG and the drain D _DS2 The smaller the overall source-drain capacitance C _DS The smaller.

However, the number of doped layers included in the shielding gate SG needs to be determined according to parameters such as breakdown voltage of the device and thickness of the epitaxial layer.

For example, if a breakdown voltage of about 70V is required for a SiC MOSFET device, the thickness of the epitaxial layer 20 is about 10 μm to 12 μm, if the thickness of the gate G is about 1 μm, the bottom of the shielding gate SG is about 3 μm from the bottom of the drift region 23, and assuming that the thickness of each doped layer in the shielding gate SG is 1 μm, 6 to 8 doped layers may be provided in the shielding gate SG.

From this, it can be seen that the larger the breakdown voltage requirement of the SiC MOSFET device, the thicker the epitaxial layer, the more doping layers can be provided in the shielding gate SG, and the capacitance C between the shielding gate SG and the drain D _DS2 The more the reduction is, the overall source-drain capacitance C is further made _DS The smaller.

It should be noted that, although the foregoing description is only given by taking the case that the doped layer of the shielding gate SG farthest from the bottom of the trench 21 is electrically connected to the source S as an example, it is understood that the doped layer of the shielding gate SG closest to the bottom of the trench 21 is completely similar to the case that the doped layer of the shielding gate SG is electrically connected to the source S, and the description thereof is omitted herein.

It should be further noted that, as shown in fig. 3, the source electrode S generally covers the gate electrode G, so that a large area of source electrode metal can be used in the manufacturing process, so that the source electrode is avoided from being made of a narrow metal strip, and the source electrode bonding wire resistance of the device is reduced. However, this inevitably increases the overlap area of the gate G and the source S, resulting in a gate-source capacitance C _GS Is generated.

As shown in connection with fig. 3-7, the gate-source capacitance C of the device _GS The sum C of the capacitance of the overlapping part of the grid G and the base region 24 of the side wall of the groove, the capacitance of the overlapping part of the grid G and the first source region 25 of the side wall of the groove and the capacitance of the overlapping part of the grid G and the source S through the insulating oxide layer 22 _GS1 Due to the existence of the shielding gate SG below the gate G and the electrical connection of the shielding gate SG and the source S, the gate-source capacitance C of the device _GS The capacitance C of the overlapping part of the grid G and the shielding grid SG is also increased _GS2 Here, the thickness of the insulating oxide layer 22 between the gate G and the shielding gate SG is equal to the capacitance C of the overlapping portion of the gate G and the shielding gate SG _GS2 With greater impact, a thicker insulating oxide layer 22 can be generally used to reduce the gate-source capacitance C _GS2 。

In summary, in the SiC MOSFET device provided in the embodiment of the present application, the surface of the epitaxial layer 20 facing away from the substrate 10 is provided with the trench 21, and the trench 21 is provided therein with the gate G and the shielding gate SG located on the side of the gate G near the drain D, so that the shielding gate SG is introduced between the gate G and the drain D, the overlapping area between the gate G and the drain D is reduced, and the gate-drain capacitance C is further reduced _GD . And, the shielding gate SG comprises at least two doped layers stacked along the direction perpendicular to the bottom of the trench 21, and the doping types of the adjacent two doped layers are opposite, and one doped layer closest to the bottom of the trench 21 or the doped layer farthest from the bottom of the trench 21 in the shielding gate SG is electrically connected with the source SIs connected to form PN junction between two adjacent doped layers in the shielding gate SG, and junction capacitance C of the PN junction _J Is introduced such that the capacitance C between the shielding gate SG and the drain D _DS2 With reduced space, the SiC MOSFET device provided by the embodiment of the application can reduce the gate-drain capacitance C _GD Is to solve the source-drain capacitance C at the same time _DS The excessive problem, in turn, can reduce switching losses.

Optionally, in an embodiment of the present application, a doping concentration of one doping layer electrically connected to the source S in the shielding gate SG is greater than a doping concentration of the other doping layer. This is because a doped layer electrically connected to the source S in the shield gate SG needs to form a good ohmic contact with the source S, and thus a doped layer electrically connected to the source S in the shield gate SG needs to be heavily doped.

The inventor researches that, for each doped layer in the shielding gate SG, the lower the doping concentration is, the wider the depletion layer of PN junction formed by two adjacent doped layers is, the smaller the junction capacitance of PN junction formed by two adjacent doped layers is, which is more beneficial to reducing the capacitance C between the shielding gate SG and the drain D _DS2 Thereby making the whole source-drain capacitance C _DS The smaller. However, as can be seen from the foregoing, the doped layer of the shielding gate SG electrically connected to the source electrode S needs to be heavily doped, so that a good ohmic contact is formed with the source electrode S. Therefore, in this embodiment, the doping concentration of one doped layer electrically connected to the source electrode S in the shielding gate SG is set to be larger than the doping concentration of the other doped layers, that is, the doping concentration of the other doped layers may be smaller, so that the junction capacitance of the PN junction formed by the other doped layers is smaller on the basis of ensuring good ohmic contact with the source electrode S.

On the basis of the above-described embodiments, optionally, in an embodiment of the present application, in the shielding gate SG, the doping concentration of each doping layer gradually decreases in a direction away from one doping layer electrically connected to the source S. That is, when one of the doped layers closest to the bottom of the trench 21 in the shield gate SG is electrically connected to the source S, i.e., in a direction away from the bottom of the trench 21, the doping concentration of each doped layer gradually decreases. Similarly, when a doped layer of the shielding gate SG farthest from the bottom of the trench 21 is electrically connected to the source S, i.e., in a direction approaching the bottom of the trench 21, the doping concentration of each doped layer gradually decreases.

Since the doping concentration of the doped layers in the shielding gate SG is smaller, the junction capacitance of the PN junction formed by two adjacent doped layers is smaller, in this embodiment, the shielding gate SG is arranged such that the doping concentration of each doped layer is gradually reduced along the direction away from the one doped layer electrically connected with the source electrode S, so that the junction capacitance of the PN junction formed by two adjacent doped layers is smaller along the direction away from the one doped layer electrically connected with the source electrode S, and the minimum junction capacitance of the PN junction determines the capacitance C between the shielding gate SG and the drain electrode D _DS2 Thereby determining the overall source-drain capacitance C _DS Thereby facilitating the source-drain capacitance C for the whole device _DS And controlling.

In one embodiment of the present application, the doping concentration of the doped layer electrically connected to the source electrode S in the shielding gate SG is optionally 1×10 ²⁰ cm ^-3 -1×10 ²¹ cm ^-3 The endpoint value is included, so that a doped layer electrically connected with the source electrode S in the shielding gate SG is heavily doped and forms good ohmic contact with the source electrode S.

Optionally, in an embodiment of the present application, each doped layer in the shielding gate SG is a polysilicon doped layer, that is, a material of each doped layer in the shielding gate SG is polysilicon. Since the shielding gate SG is electrically connected to the source electrode, the shielding gate SG may be also referred to as a source polysilicon structure at this time.

Alternatively, the gate G may be a polysilicon gate, that is, the material of the gate G may be polysilicon, where the gate G is a polysilicon gate.

Fig. 8 is a schematic cross-sectional structure of another SiC MOSFET device provided in an embodiment of the present application, and referring to fig. 3 and 8, in the SiC MOSFET device provided in an embodiment of the present application, the epitaxial layer 20 includes a drift region 23, a base region 24, and a first source region 25 sequentially arranged in a direction away from the substrate 10, and the trench 21 extends into the drift region 23;

the base region 24 and the first source region 25 are both disposed corresponding to the gate G, and a side of the base region 24 close to the gate G is a first channel region;

base region 24 and first source region 25 are both electrically connected to the source.

Alternatively, in one embodiment of the present application, as shown in fig. 8, the drift region 23 includes a first drift region 231 and a second drift region 232 sequentially arranged in a direction away from the substrate 10, where the doping concentration of the second drift region 232 is greater than that of the first drift region 231, and the trench 21 extends into the second drift region 232.

In this embodiment, the drift region 23 includes the first drift region 231 and the second drift region 232 sequentially arranged along the direction away from the substrate 10, and the doping concentration of the second drift region 232 is larger, which is beneficial to reducing the on-resistance of the device, and further reducing the on-loss of the device; the first drift region 231 has a smaller doping concentration, which is beneficial to maintaining the device with a higher breakdown voltage.

Alternatively, the doping concentration of the first drift region 231 may be in the range of 3×10 ¹⁵ cm ^-3 -8×10 ¹⁵ cm ^-3 Including endpoint values.

The doping concentration of the second drift region 232 may be in the range of 1×10 ¹⁶ cm ^-3 -5×10 ¹⁶ cm ^-3 Including endpoint values.

Optionally, in one embodiment of the present application, as shown in fig. 8, the base region 24 and the first source region 25 are located on one side of the trench 21, and the second drift region 232 surrounds a portion of the bottom of the trench 21;

epitaxial layer 20 further includes a second source region 27 and a second channel region 28;

the second source region 27 is located at one side of the trench 21 away from the first source region 25 and the base region 24, the second source region 27 is electrically connected with the source S, and the second source region 27 extends to one side of the trench 21 close to the substrate 10 in an L shape;

the second channel region 28 is located on a side of the trench 21 close to the substrate 10, and the second channel region 28 communicates with the second source region 27 and the second drift region 232.

In this embodiment, as shown in fig. 8, since the trench 21 extends into the second drift region 232, the base region 24 and the first source region 25 are located at one side of the trench 21, i.e. the base region 24 and the first source region 25 are located at one side of the sidewall of the trench 21, and at this time, the second drift region 232 surrounds part of the bottom of the trench 21, i.e. the SiC MOSFET device provided in this embodiment is an asymmetric structure, where the base region 24, the first source region 25 and the second drift region 232 are located at one side of the trench 21, but not at two opposite sides of the trench 21.

In this embodiment, as shown in fig. 8, the epitaxial layer 20 further includes a second source region 27 and a second channel region 28, where the second source region 27 extends from a side of the trench 21 facing away from the base region 24 and the first source region 25 to a side of the trench 21 facing away from the substrate 10, the surface of the second source region 27 facing away from the substrate 10 is electrically connected to the source S, and the second source region 27 communicates with the second drift region 232 through the second trench region 28 at a side of the trench 21 facing away from the substrate 10.

Optionally, the second source region 27 is N ⁺ Doped to form a good ohmic contact with the source S. The doping concentration of the second source region 27 may be in the range of 5×10 ¹⁶ cm ^-3 -9×10 ¹⁶ cm ^-3 Including endpoint values.

Optionally, the second channel region 28 is N-doped.

When the SiC MOSFET device provided in this embodiment is turned on in the forward direction, the second channel region 28 at the bottom of the trench 21 serves as an accumulation channel and is connected in parallel with the first channel region (inversion channel) in the base region 24, so that the on-resistance of the device is reduced and the forward conduction capability of the device is improved.

Optionally, in an embodiment of the present application, the epitaxial layer 20 further includes a well region 26, where the well region 26 includes a first well region 261 and a second well region 262;

the first well region 261 is positioned at one side of the first source region 25, the base region 24 and the second drift region 232, which is away from the trench 21;

the second well region 262 is located on the side of the second source region 27 and the second channel region 28 away from the trench 23.

In an actual manufacturing process, the trench 21 needs to be etched in the epitaxial layer 20, and then the epitaxial layer 20 is subjected to ion implantation to form the first well region 261 and the second well region 262, where the first well region 261 and the second well region 262 may be P-type doped, so as to further form the second drift region 232, the base region 24, the first source region 25, and the second channel region 28 and the second source region 27.

In this embodiment, the second source region 27 of the L-shape is introduced into the second well region 262 at one side of the trench 21, and the second well region 262 deeper at the bottom of the trench 21 is introduced into the second channel region 28, so as to reduce the barrier height of the body diode, make the device have lower turn-on voltage and conduction loss, significantly improve the third quadrant performance of the device, inhibit the bipolar degradation problem caused by turning on the body diode, and meanwhile, since the device is internally integrated with the diode with low conduction voltage drop, the external antiparallel schottky diode required by the SiC MOSFET device in the system application is removed, the chip area is saved, and the cost is reduced.

Alternatively, in one embodiment of the present application, the doping concentration of the first source region 25 may be in a range of 1×10 ¹⁸ cm ^-3 -3×10 ¹⁸ cm ^-3 The endpoint value is included so as to reduce the contact resistance between the first source region 25 and the source electrode S, so that the first source region 25 and the source electrode S form good ohmic contact, and the circulation of electron flow when the device is turned on is facilitated.

Optionally, in an embodiment of the present application, the front projection of the gate G on the plane of the substrate 10 is located within the front projection range of the shielding gate SG on the plane of the substrate 10, that is, the front projection of the gate G on the plane of the substrate 10 overlaps with the front projection of the shielding gate SG on the plane of the substrate 10, or the front projection of the gate G on the plane of the substrate 10 is surrounded by the front projection of the shielding gate SG on the plane of the substrate 10.

It will be appreciated that the orthographic projection of the gate electrode G on the plane of the substrate 10 is within the orthographic projection range of the shielding gate electrode SG on the plane of the substrate 10, which is beneficial to further reducing the overlapping area of the gate electrode G and the drain electrode D, so that the gate-drain capacitance C _GD Further reducing the switching losses of the device.

In the description, each part is described in a parallel and progressive mode, and each part is mainly described as a difference with other parts, and all parts are identical and similar to each other.

The features described in the various embodiments of the present disclosure may be interchanged or combined with one another in the description to enable those skilled in the art to make or use the disclosure. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the application. Thus, the present application is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims (10)

1. A SiC MOSFET device, comprising:

a substrate;

an epitaxial layer located on one side of the substrate;

the source electrode is positioned on one side of the epitaxial layer, which is away from the substrate, and the drain electrode is positioned on one side of the substrate, which is away from the epitaxial layer;

a groove is formed in the surface, deviating from the substrate, of the epitaxial layer, a grid electrode and a shielding grid positioned on one side, close to the drain electrode, of the grid electrode are arranged in the groove, and insulating oxide layers are arranged on the side wall and the bottom of the groove, between the grid electrode and the shielding grid and between the grid electrode and the source electrode;

the shielding grid comprises at least two doped layers which are stacked along the direction perpendicular to the bottom of the groove, the doping types of the adjacent two doped layers are opposite, and one doped layer closest to the bottom of the groove or one doped layer farthest from the bottom of the groove in the shielding grid is electrically connected with the source electrode.

2. The SiC MOSFET device of claim 1, wherein a doping concentration of one of the doped layers in the shield gate electrically connected to the source is greater than a doping concentration of the other doped layers.

3. The SiC MOSFET device of claim 2, wherein in the shield gate, the doping concentration of each of the doped layers decreases gradually in a direction away from the one of the doped layers electrically connected to the source.

4. A SiC MOSFET device according to claim 2 or 3, characterized in that the doping concentration of the one of the doping layers of the shield gate electrically connected to the source electrode is in the range of 1 x 10 ²⁰ cm ^-3 -1×10 ²¹ cm ^-3 Including endpoint values.

5. The SiC MOSFET device of claim 1, wherein each of said doped layers in said shield gate is a polysilicon doped layer.

6. The SiC MOSFET device of claim 1, wherein the epitaxial layer comprises a drift region, a base region, and a first source region arranged in sequence in a direction away from the substrate, the trench extending into the drift region;

the base region and the first source region are arranged corresponding to the grid electrode, and a first channel region is arranged at one side of the base region, which is close to the grid electrode;

the base region and the first source region are both electrically connected with the source electrode.

7. The SiC MOSFET device of claim 6, wherein the drift region comprises a first drift region and a second drift region arranged in sequence in a direction away from the substrate, the second drift region having a doping concentration greater than a doping concentration of the first drift region;

the trench extends into the second drift region.

8. The SiC MOSFET device of claim 7, wherein said base region and said first source region are located on one side of said trench, and said second drift region surrounds a portion of a bottom of said trench;

the epitaxial layer further comprises a second source region and a second channel region;

the second source region is positioned at one side of the groove away from the first source region and the base region, the second source region is electrically connected with the source electrode, and the second source region extends to one side of the groove close to the substrate in an L shape;

the second channel region is located at one side of the groove close to the substrate, and the second channel region is communicated with the second source region and the second drift region.

9. The SiC MOSFET device of claim 8, wherein the epitaxial layer further comprises a well region comprising a first well region and a second well region;

the first well region is positioned at one side of the first source region, the base region and the first drift region, which is away from the groove;

the second well region is located at one side of the second source region and the second channel region away from the groove.

10. A SiC MOSFET device according to any of claims 6-9 characterized in that the doping concentration of the first source region is in the range of 1 x 10 ¹⁸ cm ^-3 -3×10 ¹⁸ cm ^-3 Including endpoint values.