CN116487386A - High-voltage BCD semiconductor device based on deep groove partition oxidation and manufacturing method - Google Patents
High-voltage BCD semiconductor device based on deep groove partition oxidation and manufacturing method Download PDFInfo
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- 238000005530 etching Methods 0.000 claims description 20
- 238000002513 implantation Methods 0.000 claims description 12
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- 239000000758 substrate Substances 0.000 claims description 11
- 238000000151 deposition Methods 0.000 claims description 10
- 239000012535 impurity Substances 0.000 claims description 9
- 238000005468 ion implantation Methods 0.000 claims description 9
- 239000010953 base metal Substances 0.000 claims description 7
- 229910004298 SiO 2 Inorganic materials 0.000 claims description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 3
- 230000004913 activation Effects 0.000 claims description 3
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 3
- 238000000407 epitaxy Methods 0.000 claims description 3
- 229910052760 oxygen Inorganic materials 0.000 claims description 3
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- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
- H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
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Abstract
The invention provides a high-voltage BCD semiconductor device based on deep groove partition oxidation and a manufacturing method thereof, which can integrate semiconductor devices such as a high-voltage LDMOS, a low-voltage CMOS, a low-voltage NPN and the like on one chip at the same time, integrate various devices such as a Bipolar device applied to an analog circuit, a power device in a switch circuit, a CMOS device in a logic circuit and the like together, save cost and greatly improve the integration level of the chip. Different from the traditional BCD integration technology, the invention uses a deep-trench partition oxidation high-voltage BCD technology, introduces a longitudinal floating field plate array into the device, and improves the device withstand voltage of the high-voltage LDMOS by introducing a global MIS depletion mechanism in the off state of the device. When the device is in an on state, an accumulation layer can be formed on the surface of the floating field plate, the specific on resistance is reduced, the saturation current is increased, and isolation among semiconductor device structures such as a high-voltage LDMOS, a low-voltage CMOS, a low-voltage NPN and the like is realized.
Description
Technical Field
The invention belongs to the field of power semiconductors, and mainly provides a high-voltage BCD semiconductor device based on deep groove partition oxidation and a manufacturing method thereof.
Background
Power integrated ICs are widely used in power management, motor driving, automotive electronics, industrial control, and other fields. BCD (binary coded decimal)
The technology integrates Bipolar, CMOS, DMOS and other high-voltage power devices, various resistors, capacitors and diodes into one chip, has the characteristics of low cost, easy packaging, easy design, simpler peripheral chips and the like, and is rapidly developed into a mainstream technology in the field of power ICs. Bipolar transistors in BCD technology have high analog precision mainly used in analog circuits, CMOS has high integration mainly used in logic circuits, and DMOS has high power (high voltage) characteristics commonly used as switching. The DMOS used as a switch is a core device of a BCD process, the function of the DMOS requires the device to have high voltage resistance and small specific on-resistance as much as possible, and the driving capability and the area of a chip are directly determined by the performance of the DMOS, so that the design of the DMOS is one of the keys; in addition, the BCD technology integrates devices with different functions on one chip, and the required working environments are different due to the different functions of the devices, so how to isolate the different devices is another key in BCD design. Unlike traditional BCD integration techniques, the present invention uses a deep trench, zoned oxidized high voltage BCD process to introduce a vertical floating field plate array into the device. According to the invention, the device withstand voltage of the high-voltage LDMOS is improved by introducing a global MIS depletion mechanism in the off state of the device. Meanwhile, when the device is in an on state, an accumulation layer can be formed on the surface of the floating field plate, the specific on resistance is reduced, the saturation current is improved, and isolation among semiconductor device structures such as a high-voltage LDMOS, a low-voltage CMOS, a low-voltage NPN and the like is realized.
Disclosure of Invention
Aiming at the problems in the background technology, the invention introduces a vertical floating field plate array into the device, provides a high-voltage BCD semiconductor device based on deep trench partition oxidation, improves the performance of the DMOS device and realizes isolation among different devices.
In order to achieve the above purpose, the technical scheme of the invention is as follows:
a high-voltage BCD semiconductor device based on deep groove partition oxidation comprises a high-voltage LDMOS device 1, a low-voltage NPN device 2 and a low-voltage CMOS device 3 which are integrated on the same chip;
the high-voltage LDMOS device 1 comprises a plurality of cells which have the same structure and are sequentially connected, wherein the cells are directly formed in the second conductivity type drift region 21, the second conductivity type drift region 21 is positioned above the first conductivity type semiconductor substrate 11, the first conductivity type well region a112 is positioned at the left side of the second conductivity type drift region 21 of the high-voltage LDMOS device 1, the first conductivity type source-side heavily doped region 113 and the second conductivity type source-side heavily doped region 122 are adjacently contacted and are positioned in the first conductivity type well region a112, and the source metal a152 of the high-voltage LDMOS device 1 is positioned at the upper surfaces of the first conductivity type source-side heavily doped region 113 and the second conductivity type source-side heavily doped region 122; the second conductive type well region a124 is located on the right side of the second conductive type drift region 21 of the high-voltage LDMOS device 1, the second conductive type drain-side heavily doped region 123 is located in the second conductive type well region a124, and the drain metal a153 of the high-voltage LDMOS device 1 is located on the upper surface of the second conductive type drain-side heavily doped region 123; the second dielectric oxide layer a132 is located above the first conductivity type well region a112, and has a left end in contact with the second conductivity type source end heavily doped region 122 and a right end in contact with the second conductivity type drift region 21; the third dielectric oxide layer a133 is located on the upper surface of the second conductivity type drift region 21 between the second dielectric oxide layer a132 and the second conductivity type drain heavily doped region 123, and the fourth dielectric oxide layer 34 is located on the device surface; the control gate polysilicon electrode A142 covers the upper surface of the second dielectric oxide layer A132 and extends to the upper surface of the third dielectric oxide layer A133 partially; the metal ring 151 is located on the upper surface of the fourth dielectric oxide layer 34 and connected to the polysilicon electrode 41 through a through hole, the first dielectric oxide layer 31 and the polysilicon electrode 41 form a longitudinal floating field plate, and the first dielectric oxide layer 31 surrounds the polysilicon electrode 41, and the longitudinal floating field plate is distributed in the second conductivity type drift region 21 of the whole high-voltage LDMOS device 1 to form a longitudinal floating field plate array;
the low-voltage NPN device 2 comprises a plurality of cells which have the same structure and are sequentially connected, and the cells are directly arranged in a second conduction type drift region 21 surrounded by a longitudinal floating field plate formed by a first dielectric oxide layer 31 and a polysilicon electrode 41; the first conductive type base region 212 is located in the second conductive type drift region 21, the second conductive type emitter heavy doping region 222 is located in the first conductive type base region 212, and the emitter metal 251 of the low-voltage NPN device 2 is located on the upper surface of the second conductive type emitter heavy doping region 222; the first conductive type base heavily doped region 213 is located in the first conductive type base region 212, and the base metal 252 of the low-voltage NPN device 2 is located on the upper surface of the first conductive type base heavily doped region 213; the second conductivity type collector heavy doping region 223 is located in the second conductivity type drift region 21, and the collector metal 253 of the low-voltage NPN device 2 is located on the upper surface of the second conductivity type collector heavy doping region 223;
the low-voltage CMOS device 3 includes a plurality of cells having the same structure and sequentially connected, and the cells are directly formed in the second conductivity type well region B324 in the second conductivity type drift region 21 surrounded by the longitudinal floating field plate formed by the first dielectric oxide layer 31 and the polysilicon electrode 41; wherein, the third dielectric oxide layer B333 is located between PMOS and NMOS of the low-voltage CMOS device 3; the first conductivity type well region B312 is located on the right side of the second conductivity type drift region 21 of the CMOS device 3, and the NMOS portion of the low voltage CMOS device 3 is located in the first conductivity type well region B312; a second dielectric oxide layer B332 is arranged between the second conductive type source end heavy doping region 322 and the second conductive type drain end heavy doping region 323 of the NMOS, and a second dielectric oxide layer B332 is arranged between the first conductive type source end heavy doping region 313 and the first conductive type drain end heavy doping region 314 of the PMOS; the control gate polysilicon electrode B342 covers the upper surface of the second dielectric oxide layer B332; the source metal B351 is located above the first conductivity type source side heavily doped region 313 of PMOS and the second conductivity type source side heavily doped region 322 of NMOS, the gate metal B352 is located above the control gate polysilicon electrodes B342 of PMOS and NMOS, and the drain metal B353 is located above the first conductivity type drain side heavily doped region 314 of PMOS and the second conductivity type drain side heavily doped region 323 of NMOS;
the x direction is from the source electrode to the drain electrode, the downward depth direction of the vertical floating field plate is the y direction, and the z direction is perpendicular to the x direction and the y direction.
Preferably, the transverse-longitudinal spacing of the vertical floating field plate formed by the first dielectric oxide layer 31 and the polysilicon electrode 41 of the high-voltage LDMOS device 1 is reduced, so that the bottom of the vertical floating field plate formed by the first dielectric oxide layer 31 and the polysilicon electrode 41 forms continuous buried oxide, and isolation among the high-voltage LDMOS device, the low-voltage CMOS device and the low-voltage NPN device structures is realized in an on state.
Preferably, the buried layer 114 of the first conductivity type is introduced in the drift region 21 of the high-voltage LDMOS device 1 of the second conductivity type.
Preferably, a first conductivity type top layer 115 is introduced on the surface of the second conductivity type drift region 21 of the high voltage LDMOS device 1.
Preferably, a superjunction structure is introduced in the second conductivity type drift region 21 of the high-voltage LDMOS device 1, and N and P stripes are alternately arranged in the z direction, and the widths of the N and P stripes are larger than the width of the first dielectric oxide layer 31 or smaller than the width of the first dielectric oxide layer 31.
Preferably, the second conductivity type drift region 21 is formed by implantation and junction pushing, and the vertical floating field plate formed by the first dielectric oxide layer 31 and the polysilicon electrode 41 is entirely located in the second conductivity type drift region 21 without being inserted into the first conductivity type semiconductor substrate 11.
The invention also provides a manufacturing method of the high-voltage BCD semiconductor device based on deep groove partition oxidation, which comprises the following steps:
step 1: selecting a first-type conductivity semiconductor substrate 11;
step 2: epitaxial of the second conductivity type impurity, forming a second conductivity type drift region 21;
step 3: siO (SiO) 2 /Si 3 N 4 /SiO 2 Forming a triple hard mask and etching a first deep groove;
step 4: pad oxygen layer and Si 3 N 4 Forming a layer;
step 5: si (Si) 3 N 4 Anisotropic etching and second deep trench etching;
step 6: forming a continuous buried oxide by thermal oxidation;
step 7: removing the hard mask and oxidizing the groove wall, and forming a first dielectric oxide layer 31 in the deep groove;
step 8: depositing polycrystalline and etching to a silicon plane to form a polycrystalline silicon electrode 41;
step 9: implanting second conductivity type impurities and pushing a junction, forming a second conductivity type well region A124 and a second conductivity type well region B324 at the same time, implanting first conductivity type impurities and pushing a junction at the same time, and forming a first conductivity type well region A112, a first conductivity type base region 212 and a first conductivity type well region B312 at the same time;
step 10: simultaneously forming a second dielectric oxide layer A132 and a second dielectric oxide layer B332, and then simultaneously forming a third dielectric oxide layer A133 and a third dielectric oxide layer B333;
step 11: depositing and etching polysilicon, and simultaneously forming a control gate polysilicon electrode A142 and a control gate polysilicon electrode B342;
step 12: ion implantation is performed to form a first conductive type source-side heavily doped region 113, a second conductive type source-side heavily doped region 122 and a second conductive type drain-side heavily doped region 123 of the high-voltage LDMOS device 1; ion implantation forms a second conductivity type source end heavily doped region 122, a first conductivity type base heavily doped region 213 and a second conductivity type collector heavily doped region 223 of the low voltage NPN device 2; ion implantation forms a first conductivity type source side heavily doped region 313, a first conductivity type drain side heavily doped region 314, a second conductivity type source side heavily doped region 322, a second conductivity type drain side heavily doped region 323 of the PMOS device, and the nmos device of the low voltage CMOS device 3;
step 13: a fourth dielectric oxide layer 34 is deposited, contact holes of the high-voltage LDMOS device 1, the NPN device 2 and the low-voltage CMOS device 3 are simultaneously formed by etching the third dielectric oxide layer a133 and the fourth dielectric oxide layer 34, and then a metal ring 151, a source metal a152, a drain metal a153, a gate metal a154, an emitter metal 251, a base metal 252, a collector metal 253, a source metal B351, a gate metal B352 and a drain metal B353 are deposited and etched.
Preferably, the second conductivity type drift region 21 formed by epitaxy in step 2 is obtained by a method of implantation and junction pushing; and/or the first conductivity-type well region a112, the first conductivity-type base region 212, and the first conductivity-type well region B312 obtained by implantation and junction pushing in step 9 are formed by implantation and activation of a plurality of different energies.
The beneficial effects of the invention are as follows: a deep trench zoned oxidation high voltage BCD process is used to introduce a vertical floating field plate array into the device. According to the invention, the device withstand voltage of the high-voltage LDMOS is improved by introducing a global MIS depletion mechanism in the off state of the device. Meanwhile, when the device is in an on state, an accumulation layer can be formed on the surface of the floating field plate, the specific on resistance is reduced, the saturation current is improved, and isolation among semiconductor device structures such as a high-voltage LDMOS, a low-voltage CMOS, a low-voltage NPN and the like is realized.
Drawings
Fig. 1 is a plan view structural diagram of a high voltage BCD semiconductor device based on deep trench partition oxidation of embodiment 1;
fig. 2 (a) and (b) are plan view block diagrams of a low-voltage NPN device 2 and a low-voltage CMOS device 3 of embodiment 1, respectively;
fig. 3 is a top view of an AB cross-section of a high voltage BCD semiconductor device based on deep trench partition oxidation of embodiment 1;
fig. 4 is a plan view structural diagram of a high voltage BCD semiconductor device based on deep trench partition oxidation of embodiment 2;
fig. 5 is an AB cross-sectional top view of a high voltage BCD semiconductor device based on deep trench partition oxidation of example 2;
fig. 6 is a plan view structural diagram of a high voltage BCD semiconductor device based on deep trench partition oxidation of embodiment 3;
fig. 7 is a plan view structural diagram of a high voltage BCD semiconductor device based on deep trench partition oxidation of embodiment 4;
fig. 8 is a perspective view of a high voltage BCD semiconductor device based on deep trench partition oxidation of embodiment 5;
fig. 9 is a plan view structural diagram of a high voltage BCD semiconductor device based on deep trench partition oxidation of embodiment 6;
FIGS. 10 (a) -10 (m) are schematic process flow diagrams of the device of example 1;
1 is a high-voltage LDMOS device, 2 is a low-voltage NPN device, 3 is a low-voltage CMOS device, 11 is a first conductive type semiconductor substrate, 112 is a first conductive type well region A,113 is a first conductive type source-end heavily doped region, 122 is a second conductive type source-end heavily doped region, 123 is a second conductive type drain-end heavily doped region, 124 is a second conductive type well region A,132 is a second dielectric oxide layer A,133 is a third dielectric oxide layer A,142 is a control gate polysilicon electrode A,151 is a metal ring, 152 is a source metal A,153 is a drain metal A,154 is a gate metal A,21 is a second conductive type drift region, 212 is a first conductive type base region, 222 is a second conductive type emitter heavily doped region, 223 is a second conductivity type collector heavily doped region, 251 is an emitter metal, 252 is a base metal, 253 is a collector metal, 31 is a first dielectric oxide layer, 312 is a first conductivity type well region B,313 is a first conductivity type source heavily doped region, 314 is a first conductivity type drain heavily doped region, 322 is a second conductivity type source heavily doped region, 323 is a second conductivity type drain heavily doped region, 324 is a second conductivity type well region B,332 is a second dielectric oxide layer B,333 is a third dielectric oxide layer B,34 is a fourth dielectric oxide layer, 342 is a control gate polysilicon electrode B,41 is a polysilicon electrode, 213 is a first conductivity type base heavily doped region, 114 is a first conductivity type buried layer, 115 is a first conductivity type top layer; 351 is a source metal B,352 is a gate metal B,353 is a drain metal B.
Detailed Description
Other advantages and effects of the present invention will become apparent to those skilled in the art from the following disclosure, which describes the embodiments of the present invention with reference to specific examples. The invention may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present invention.
Example 1
A deep trench partition oxidation-based high voltage BCD semiconductor device as described in embodiment 1, as shown in fig. 1-3:
the high-voltage LDMOS device 1 comprises a plurality of cells which have the same structure and are sequentially connected, wherein the cells are directly formed in the second conductivity type drift region 21, the second conductivity type drift region 21 is positioned above the first conductivity type semiconductor substrate 11, the first conductivity type well region a112 is positioned at the left side of the second conductivity type drift region 21 of the high-voltage LDMOS device 1, the first conductivity type source-side heavily doped region 113 and the second conductivity type source-side heavily doped region 122 are adjacently contacted and are positioned in the first conductivity type well region a112, and the source metal a152 of the high-voltage LDMOS device 1 is positioned at the upper surfaces of the first conductivity type source-side heavily doped region 113 and the second conductivity type source-side heavily doped region 122; the second conductive type well region a124 is located on the right side of the second conductive type drift region 21 of the high-voltage LDMOS device 1, the second conductive type drain-side heavily doped region 123 is located in the second conductive type well region a124, and the drain metal a153 of the high-voltage LDMOS device 1 is located on the upper surface of the second conductive type drain-side heavily doped region 123; the second dielectric oxide layer a132 is located above the first conductivity type well region a112, and has a left end in contact with the second conductivity type source end heavily doped region 122 and a right end in contact with the second conductivity type drift region 21; the third dielectric oxide layer a133 is located on the upper surface of the second conductivity type drift region 21 between the second dielectric oxide layer a132 and the second conductivity type drain heavily doped region 123, and the fourth dielectric oxide layer 34 is located on the device surface; the control gate polysilicon electrode A142 covers the upper surface of the second dielectric oxide layer A132 and extends to the upper surface of the third dielectric oxide layer A133 partially; the metal ring 151 is located on the upper surface of the fourth dielectric oxide layer 34 and connected to the polysilicon electrode 41 through a through hole, the first dielectric oxide layer 31 and the polysilicon electrode 41 form a longitudinal floating field plate, and the first dielectric oxide layer 31 surrounds the polysilicon electrode 41, and the longitudinal floating field plate is distributed in the second conductivity type drift region 21 of the whole high-voltage LDMOS device 1 to form a longitudinal floating field plate array;
the low-voltage NPN device 2 comprises a plurality of cells which have the same structure and are sequentially connected, and the cells are directly arranged in a second conduction type drift region 21 surrounded by a longitudinal floating field plate formed by a first dielectric oxide layer 31 and a polysilicon electrode 41; the first conductive type base region 212 is located in the second conductive type drift region 21, the second conductive type emitter heavy doping region 222 is located in the first conductive type base region 212, and the emitter metal 251 of the low-voltage NPN device 2 is located on the upper surface of the second conductive type emitter heavy doping region 222; the first conductive type base heavily doped region 213 is located in the first conductive type base region 212, and the base metal 252 of the low-voltage NPN device 2 is located on the upper surface of the first conductive type base heavily doped region 213; the second conductivity type collector heavy doping region 223 is located in the second conductivity type drift region 21, and the collector metal 253 of the low-voltage NPN device 2 is located on the upper surface of the second conductivity type collector heavy doping region 223;
the low-voltage CMOS device 3 includes a plurality of cells having the same structure and sequentially connected, and the cells are directly formed in the second conductivity type well region B324 in the second conductivity type drift region 21 surrounded by the longitudinal floating field plate formed by the first dielectric oxide layer 31 and the polysilicon electrode 41; wherein, the third dielectric oxide layer B333 is located between PMOS and NMOS of the low-voltage CMOS device 3; the first conductivity type well region B312 is located on the right side of the second conductivity type drift region 21 of the CMOS device 3, and the NMOS portion of the low voltage CMOS device 3 is located in the first conductivity type well region B312; a second dielectric oxide layer B332 is arranged between the second conductive type source end heavy doping region 322 and the second conductive type drain end heavy doping region 323 of the NMOS, and a second dielectric oxide layer B332 is arranged between the first conductive type source end heavy doping region 313 and the first conductive type drain end heavy doping region 314 of the PMOS; the control gate polysilicon electrode B342 covers the upper surface of the second dielectric oxide layer B332; the source metal B351 is located above the first conductivity type source side heavily doped region 313 of PMOS and the second conductivity type source side heavily doped region 322 of NMOS, the gate metal B352 is located above the control gate polysilicon electrodes B342 of PMOS and NMOS, and the drain metal B353 is located above the first conductivity type drain side heavily doped region 314 of PMOS and the second conductivity type drain side heavily doped region 323 of NMOS;
the x direction is from the source electrode to the drain electrode, the downward depth direction of the vertical floating field plate is the y direction, and the z direction is perpendicular to the x direction and the y direction. The basic working principle is as follows:
taking the first conductive type semiconductor material as a P-type as an example, when the integrated device is in an off state, the longitudinal floating field plate introduces a global MIS depletion mechanism, and because of self-charge balance of the MIS structure, the second conductive type drift region 21 can be depleted independently of a substrate, so that the withstand voltage of the device part of the high-voltage LDMOS is improved, the concentration of the second conductive type drift region 21 can be increased, and the specific on-resistance is reduced. When the integrated device is in an on state, the surface of the floating field plate can form an accumulation layer, the specific on resistance is reduced, the saturation current is increased, and the isolation among the high-voltage LDMOS, the low-voltage CMOS and the low-voltage NPN semiconductor device structures in the on state is realized because the low-voltage NPN device part and the low-voltage CMOS device are both manufactured in the area, surrounded by the second conductive type drift region 21, formed by the longitudinal floating field plate formed by the first dielectric oxide layer 31 and the polysilicon electrode 41.
As shown in fig. 10, a schematic process flow chart of embodiment 1 of the present invention specifically includes the following steps:
step 1: selecting a first-type conductivity semiconductor substrate 11 as shown in fig. 10 (a);
step 2: a second conductivity type impurity is epitaxially grown to form a second conductivity type drift region 21 as shown in fig. 10 (b);
step 3: siO (SiO) 2 /Si 3 N 4 /SiO 2 Forming a triple hard mask and etching a first deep trench as shown in fig. 10 (c);
step 4: pad oxygen layer and Si 3 N 4 Layer formation, as shown in fig. 10 (d);
step 5: si (Si) 3 N 4 Anisotropic etching and second deep trench etching, as shown in fig. 10 (e);
step 6: forming a continuous buried oxide by thermal oxidation, as shown in fig. 10 (f);
step 7: hard mask removal and trench wall oxidation, forming a first dielectric oxide layer 31 in the deep trench, as shown in fig. 10 (g);
step 8: depositing polycrystalline and etching to a silicon plane to form a polycrystalline silicon electrode 41, as shown in fig. 10 (h);
step 9: ion-implanting second conductivity-type impurities and pushing a junction while forming a second conductivity-type well region a124, a second conductivity-type well region B324, and then ion-implanting first conductivity-type impurities and pushing a junction while forming a first conductivity-type well region a112, a first conductivity-type base region 212, and a first conductivity-type well region B312, as shown in fig. 10 (i);
step 10: simultaneously forming a second dielectric oxide layer A132 and a second dielectric oxide layer B332, and then simultaneously forming a third dielectric oxide layer A133 and a third dielectric oxide layer B333; as shown in fig. 10 (j);
step 11: depositing and etching polysilicon, and simultaneously forming a control gate polysilicon electrode A142 and a control gate polysilicon electrode B342; as shown in fig. 10 (k);
step 12: ion implantation is performed to form a first conductive type source-side heavily doped region 113, a second conductive type source-side heavily doped region 122 and a second conductive type drain-side heavily doped region 123 of the high-voltage LDMOS device 1; ion implantation forms a second conductivity type source end heavily doped region 122, a first conductivity type base heavily doped region 213 and a second conductivity type collector heavily doped region 223 of the low voltage NPN device 2; ion implantation forms a first conductivity type source side heavily doped region 313, a first conductivity type drain side heavily doped region 314, a second conductivity type source side heavily doped region 322, a second conductivity type drain side heavily doped region 323 of the PMOS device, and the nmos device of the low voltage CMOS device 3; as shown in fig. 10 (l);
step 13: depositing a fourth dielectric oxide layer 34, etching the third dielectric oxide layer A133 and the fourth dielectric oxide layer 34 to form contact holes of the high-voltage LDMOS device 1, the NPN device 2 and the low-voltage CMOS device 3 at the same time, and then depositing and etching a metal ring 151, a source metal A152, a drain metal A153, a gate metal A154, an emitter metal 251, a base metal 252, a collector metal 253, a source metal B351, a gate metal B352 and a drain metal B353; as shown in fig. 10 (m);
it should be noted that:
in the above-described manufacturing method, the second conductivity type drift region 21 formed by epitaxy in step 2 may also be obtained by a high-energy implantation and junction pushing method;
in the manufacturing method, the first conductivity type well region a112, the first conductivity type base region 212 and the first conductivity type well region B312 obtained by high-energy implantation and junction pushing in step 9 may be formed by multiple implantation and activation with different energies.
Example 2
As shown in fig. 4 and 5, a schematic structural diagram of a high-voltage BCD semiconductor device based on deep trench partition oxidation in embodiment 2 is shown, and the difference between the structure of this example and that of embodiment 1 is that the vertical-floating field plate horizontal-vertical spacing formed by the first dielectric oxide layer 31 and the polysilicon electrode 41 of the high-voltage LDMOS device 1 is reduced, so that the bottom of the vertical-floating field plate formed by the first dielectric oxide layer 31 and the polysilicon electrode 41 forms a continuous buried oxide, and in the on state, isolation among the structures of the high-voltage LDMOS device, the low-voltage CMOS device and the low-voltage NPN device is realized.
Example 3
As shown in fig. 6, a schematic structural diagram of a high-voltage BCD semiconductor device based on deep trench partition oxidation in embodiment 3 is shown, and the difference between the structure of this embodiment and that of embodiment 1 is that a first conductivity type buried layer 114 is introduced into a second conductivity type drift region 21 of the high-voltage LDMOS device 1. The principle of operation is substantially the same as in example 1.
Example 4
As shown in fig. 7, a schematic structural diagram of a high-voltage BCD semiconductor device based on deep trench partition oxidation in embodiment 4 is shown, and the difference between the structure of this embodiment and that of embodiment 1 is that a first conductivity type top layer 115 is introduced on the surface of the second conductivity type drift region 21 of the high-voltage LDMOS device 1. New self-charge balance was developed in the buried layer region of the first conductivity type, which fixes the surface electric field and results in an almost constant breakdown voltage over a wide doping range, the operation principle of which is substantially the same as that of example 1.
Example 5
As shown in fig. 8, a schematic structural diagram of a high-voltage BCD semiconductor device based on deep trench partition oxidation in embodiment 5 is shown, and the difference between the structure of this embodiment and that of embodiment 1 is that a super junction structure is introduced in the second conductivity type drift region 21 of the high-voltage LDMOS device 1, N and P strips are alternately arranged in the z direction, and the widths of the N and P strips are greater than the width of the first dielectric oxide layer 31 or less than the width of the first dielectric oxide layer 31. The on-resistance can be further reduced by further increasing the doping concentration of the superjunction strip while maintaining high withstand voltage. The x direction is from the source electrode to the drain electrode, the downward depth direction of the vertical floating field plate is the y direction, and the z direction is perpendicular to the x direction and the y direction.
Example 6
As shown in fig. 9, a schematic structural diagram of a high-voltage BCD semiconductor device based on deep trench partition oxidation in embodiment 6 is shown, and the difference between the structure of this embodiment and that of embodiment 1 is that the second conductivity type drift region 21 is formed by implantation and junction pushing, and the vertical floating field plate formed by the first dielectric oxide layer 31 and the polysilicon electrode 41 is entirely located in the second conductivity type drift region 21, and is not inserted into the first conductivity type semiconductor substrate 11. The concentration of the drift region formed by injection and junction pushing presents residual error distribution, and a longitudinal floating field plate is introduced into a global MIS depletion mechanism to be mainly used at the peak concentration of the residual error distribution, so that the withstand voltage of a device part of the high-voltage LDMOS is improved.
The above embodiments are merely illustrative of the principles of the present invention and its effectiveness, and are not intended to limit the invention. Modifications and variations may be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the invention. Accordingly, it is intended that all equivalent modifications and variations of the invention be covered by the claims of this invention, which are within the skill of those skilled in the art, can be made without departing from the spirit and scope of the invention disclosed herein.
Claims (8)
1. A high-voltage BCD semiconductor device based on deep groove partition oxidation is characterized in that:
the high-voltage LDMOS device (1), the low-voltage NPN device (2) and the low-voltage CMOS device (3) are integrated on the same chip;
the high-voltage LDMOS device (1) comprises a plurality of cells which are identical in structure and are sequentially connected, the cells are directly arranged in a second conduction type drift region (21), the second conduction type drift region (21) is positioned above a first conduction type semiconductor substrate (11), a first conduction type well region A (112) is positioned on the left side of the second conduction type drift region (21) of the high-voltage LDMOS device (1), a first conduction type source-end heavy doping region (113) and a second conduction type source-end heavy doping region (122) are adjacently contacted and are positioned in the first conduction type well region A (112), and a source metal A (152) of the high-voltage LDMOS device (1) is positioned on the upper surfaces of the first conduction type source-end heavy doping region (113) and the second conduction type source-end heavy doping region (122); the second conductive type well region A (124) is positioned on the right side of the second conductive type drift region (21) of the high-voltage LDMOS device (1), the second conductive type drain terminal heavy doping region (123) is positioned in the second conductive type well region A (124), and the drain metal A (153) of the high-voltage LDMOS device (1) is positioned on the upper surface of the second conductive type drain terminal heavy doping region (123); the second dielectric oxide layer A (132) is positioned above the first conductive type well region A (112), and the left end is contacted with the second conductive type source end heavy doping region (122), and the right end is contacted with the second conductive type drift region (21); the third dielectric oxide layer A (133) is positioned on the upper surface of the second conductive type drift region (21) between the second dielectric oxide layer A (132) and the second conductive type drain end heavily doped region (123), and the fourth dielectric oxide layer (34) is positioned on the surface of the device; the control gate polysilicon electrode A (142) covers the upper surface of the second dielectric oxide layer A (132) and extends to the upper surface of the third dielectric oxide layer A (133) partially; the metal ring (151) is positioned on the upper surface of the fourth dielectric oxide layer (34) and is connected with the polysilicon electrode (41) through a through hole, the first dielectric oxide layer (31) and the polysilicon electrode (41) form a longitudinal floating field plate, the first dielectric oxide layer (31) surrounds the polysilicon electrode (41), and the longitudinal floating field plate is distributed in the second conductivity type drift region (21) of the whole high-voltage LDMOS device (1) to form a longitudinal floating field plate array;
the low-voltage NPN device (2) comprises a plurality of cells which have the same structure and are connected in sequence, and the cells are directly arranged in a second conduction type drift region (21) surrounded by a longitudinal floating field plate formed by a first dielectric oxide layer (31) and a polysilicon electrode (41); the first conductive type base region (212) is positioned in the second conductive type drift region (21), the second conductive type emitter heavy doping region (222) is positioned in the first conductive type base region (212), and the emitter metal (251) of the low-voltage NPN device (2) is positioned on the upper surface of the second conductive type emitter heavy doping region (222); the first conductive type base heavy doping region (213) is positioned in the first conductive type base region (212), and the base metal (252) of the low-voltage NPN device (2) is positioned on the upper surface of the first conductive type base heavy doping region (213); the second conductive type collector heavy doping region (223) is positioned in the second conductive type drift region (21), and the collector metal (253) of the low-voltage NPN device (2) is positioned on the upper surface of the second conductive type collector heavy doping region (223);
the low-voltage CMOS device (3) comprises a plurality of cells which are identical in structure and are sequentially connected, and the cells are directly arranged in a second conductive type well region B (324) in a second conductive type drift region (21) surrounded by a longitudinal floating field plate formed by a first dielectric oxide layer (31) and a polycrystalline silicon electrode (41); wherein the third dielectric oxide layer B (333) is located between PMOS and NMOS of the low-voltage CMOS device (3); the first conductive type well region B (312) is positioned on the right side of the second conductive type drift region (21) of the CMOS device (3), and the NMOS part of the low-voltage CMOS device (3) is positioned in the first conductive type well region B (312); a second dielectric oxide layer B (332) is arranged between the second conductive type source end heavy doping region (322) and the second conductive type drain end heavy doping region (323) of the NMOS, and a second dielectric oxide layer B (332) is arranged between the first conductive type source end heavy doping region (313) and the first conductive type drain end heavy doping region (314) of the PMOS; the control gate polysilicon electrode B (342) covers the upper surface of the second dielectric oxide layer B (332); the source metal B (351) is positioned above the source end heavy doping region (313) of the first conductivity type of the PMOS and the source end heavy doping region (322) of the second conductivity type of the NMOS, the gate metal B (352) is positioned above the control gate polysilicon electrode B (342) of the PMOS and the NMOS, and the drain metal B (353) is positioned above the drain end heavy doping region (314) of the first conductivity type of the PMOS and the drain end heavy doping region (323) of the second conductivity type of the NMOS;
the x direction is from the source electrode to the drain electrode, the downward depth direction of the vertical floating field plate is the y direction, and the z direction is perpendicular to the x direction and the y direction.
2. The deep trench partition oxidation based high voltage BCD semiconductor device of claim 1, wherein: and the transverse-longitudinal distance between the first dielectric oxide layer (31) of the high-voltage LDMOS device (1) and the longitudinal floating field plate formed by the polysilicon electrode (41) is reduced, so that the bottom of the longitudinal floating field plate formed by the first dielectric oxide layer (31) and the polysilicon electrode (41) forms continuous buried oxide, and isolation among the high-voltage LDMOS device, the low-voltage CMOS device and the low-voltage NPN device structures is realized in an on state.
3. The deep trench partition oxidation based high voltage BCD semiconductor device of claim 1, wherein: a buried layer (114) of the first conductivity type is introduced in a drift region (21) of the second conductivity type of the high-voltage LDMOS device (1).
4. The deep trench partition oxidation based high voltage BCD semiconductor device of claim 1, wherein: a first conductivity type top layer (115) is introduced at the surface of a second conductivity type drift region (21) of the high voltage LDMOS device (1).
5. The deep trench partition oxidation based high voltage BCD semiconductor device of claim 1, wherein: a super junction structure is introduced into a second conductive type drift region (21) of the high-voltage LDMOS device (1), N strips and P strips are alternately arranged in the z direction, and the width of the N strips and the P strips is larger than the width of a first dielectric oxide layer (31) or smaller than the width of the first dielectric oxide layer (31).
6. The deep trench partition oxidation based high voltage BCD semiconductor device of claim 1, wherein: a second conductivity type drift region (21) is formed by implantation and junction pushing, and a vertical floating field plate formed by a first dielectric oxide layer (31) and a polysilicon electrode (41) is entirely located in the second conductivity type drift region (21) without being inserted into a first conductivity type semiconductor substrate (11).
7. A method for manufacturing a deep trench partition oxidation-based high voltage BCD semiconductor device according to any of claims 1 to 6, characterized by comprising the steps of:
step 1: selecting a first type conductivity semiconductor substrate (11);
step 2: epitaxial second conductivity type impurities forming a second conductivity type drift region (21);
step 3: siO (SiO) 2 /Si 3 N 4 /SiO 2 Forming a triple hard mask and etching a first deep groove;
step 4: pad oxygen layer and Si 3 N 4 Forming a layer;
step 5: si (Si) 3 N 4 Anisotropic etching and second deep trench etching;
step 6: forming a continuous buried oxide by thermal oxidation;
step 7: removing the hard mask and oxidizing the groove wall, and forming a first dielectric oxide layer (31) in the deep groove;
step 8: depositing polycrystalline and etching to a silicon plane to form a polycrystalline silicon electrode (41);
step 9: ion-implanting second conductivity type impurities and pushing a junction, forming a second conductivity type well region A (124) and a second conductivity type well region B (324), and then ion-implanting first conductivity type impurities and pushing a junction, and forming a first conductivity type well region A (112), a first conductivity type base region (212) and a first conductivity type well region B (312);
step 10: simultaneously forming a second dielectric oxide layer A (132) and a second dielectric oxide layer B (332), and then simultaneously forming a third dielectric oxide layer A (133) and a third dielectric oxide layer B (333);
step 11: depositing and etching polysilicon, and simultaneously forming a control gate polysilicon electrode A (142) and a control gate polysilicon electrode B (342);
step 12: ion implantation is carried out to form a first conductive type source end heavy doping region (113), a second conductive type source end heavy doping region (122) and a second conductive type drain end heavy doping region (123) of the high-voltage LDMOS device (1); ion implantation is carried out to form a second conduction type source end heavy doping region (122) of the low-voltage NPN device (2), and a first conduction type base heavy doping region (213) and a second conduction type collector heavy doping region (223); ion implantation is carried out to form a first conductive type source end heavy doping region (313) and a first conductive type drain end heavy doping region (314) of a PMOS device of the low-voltage CMOS device (3), a second conductive type source end heavy doping region (322) and a second conductive type drain end heavy doping region (323) of an NMOS device;
step 13: depositing a fourth dielectric oxide layer (34), etching the third dielectric oxide layer A (133) and the fourth dielectric oxide layer (34) to form contact holes of the high-voltage LDMOS device (1), the NPN device (2) and the low-voltage CMOS device (3) simultaneously, and then depositing and etching a metal ring (151), a source metal A (152), a drain metal A (153), a gate metal A (154), an emitter metal (251), a base metal (252), a collector metal (253), a source metal B (351), a gate metal B (352) and a drain metal B (353).
8. The method for manufacturing the high-voltage BCD semiconductor device based on deep trench partition oxidation according to claim 7, wherein: the second conductive type drift region (21) formed by epitaxy in the step 2 is obtained by a method of implantation and junction pushing; and/or the first conductivity type well region A (112), the first conductivity type base region (212) and the first conductivity type well region B (312) obtained by implantation and junction pushing in the step 9 are formed by implantation and activation of different energies for a plurality of times.
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