CN116487322B - Method for forming conductive interconnection structure - Google Patents
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- CN116487322B CN116487322B CN202310458065.XA CN202310458065A CN116487322B CN 116487322 B CN116487322 B CN 116487322B CN 202310458065 A CN202310458065 A CN 202310458065A CN 116487322 B CN116487322 B CN 116487322B
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- 238000000034 method Methods 0.000 title claims abstract description 89
- 238000005530 etching Methods 0.000 claims abstract description 85
- 239000010410 layer Substances 0.000 claims description 197
- 238000005192 partition Methods 0.000 claims description 34
- 239000012792 core layer Substances 0.000 claims description 29
- 125000006850 spacer group Chemical group 0.000 claims description 24
- 238000005468 ion implantation Methods 0.000 claims description 16
- 230000004888 barrier function Effects 0.000 claims description 12
- 239000000463 material Substances 0.000 claims description 8
- 238000000059 patterning Methods 0.000 claims description 7
- 229910052707 ruthenium Inorganic materials 0.000 claims description 4
- 229910052721 tungsten Inorganic materials 0.000 claims description 3
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims 1
- 230000008569 process Effects 0.000 description 34
- 229910052751 metal Inorganic materials 0.000 description 27
- 239000002184 metal Substances 0.000 description 27
- 239000004065 semiconductor Substances 0.000 description 15
- 239000000758 substrate Substances 0.000 description 14
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 6
- 229910052710 silicon Inorganic materials 0.000 description 6
- 239000010703 silicon Substances 0.000 description 6
- 229910052581 Si3N4 Inorganic materials 0.000 description 5
- 238000005229 chemical vapour deposition Methods 0.000 description 5
- 239000003989 dielectric material Substances 0.000 description 5
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 5
- 238000004519 manufacturing process Methods 0.000 description 4
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 3
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- 238000005240 physical vapour deposition Methods 0.000 description 3
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 3
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- KJTLSVCANCCWHF-UHFFFAOYSA-N Ruthenium Chemical compound [Ru] KJTLSVCANCCWHF-UHFFFAOYSA-N 0.000 description 2
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 2
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
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- 229910052799 carbon Inorganic materials 0.000 description 2
- 239000010941 cobalt Substances 0.000 description 2
- 229910017052 cobalt Inorganic materials 0.000 description 2
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 238000005137 deposition process Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
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- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 2
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- 238000012986 modification Methods 0.000 description 2
- 150000004767 nitrides Chemical class 0.000 description 2
- 239000010948 rhodium Substances 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
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- 239000013078 crystal Substances 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 229910052755 nonmetal Inorganic materials 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 230000007425 progressive decline Effects 0.000 description 1
- 229910052703 rhodium Inorganic materials 0.000 description 1
- MHOVAHRLVXNVSD-UHFFFAOYSA-N rhodium atom Chemical compound [Rh] MHOVAHRLVXNVSD-UHFFFAOYSA-N 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 1
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76886—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances
- H01L21/76892—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances modifying the pattern
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The embodiment of the invention discloses a method for forming a conductive interconnection structure, which comprises the following steps: forming a predetermined mask pattern on the conductive layer; doping a first mask pattern to form a doped region with a predetermined depth in the first mask pattern, wherein the first mask pattern is the doped predetermined mask pattern, and the second mask pattern is the undoped predetermined mask pattern; wherein the etching rate of the doped region is greater than that of the undoped region; etching the conductive layer by using the first mask pattern and the second mask pattern to form a conductive interconnection structure; wherein the conductive line corresponding to the region of the second mask pattern has a high height and is formed as a conductive path.
Description
Technical Field
The invention belongs to the technical field of semiconductor manufacturing, and particularly relates to a method for forming a conductive interconnection structure.
Background
In the semiconductor manufacturing process, metal interconnect structures are fabricated by Back End Of Line (BEOL) to route integrated circuits. Typically, a metal interconnect structure includes several metal interconnect layers, with electrical connection between the metal interconnect layers of different layers being made by conductive vias (via).
With the progressive decrease in wire pitch and line width in integrated circuits, there is a need to provide a method of providing conductive paths that can form good conductive contacts between metal interconnect layers.
Disclosure of Invention
The embodiment of the invention discloses a method for forming a conductive interconnection structure, which is used for solving the problem that a conductive path with good conductive contact is difficult to form in the related technology.
In order to solve the above technical problems, an embodiment of the present invention discloses a method for forming a conductive interconnection structure, including:
forming a predetermined mask pattern on the conductive layer;
doping a first mask pattern to form a doped region with a predetermined depth in the first mask pattern, wherein the first mask pattern is the doped predetermined mask pattern, and the second mask pattern is the undoped predetermined mask pattern; wherein the etching rate of the doped region is greater than that of the undoped region;
etching the conductive layer by using the first mask pattern and the second mask pattern to form a conductive interconnection structure; wherein the conductive line corresponding to the region of the second mask pattern has a high height and is formed as a conductive path.
As some optional embodiments, the etching the conductive layer using the first mask pattern and the second mask pattern includes:
etching the first mask pattern and the second mask pattern while etching the conductive layer using the first mask pattern and the second mask pattern;
wherein an etching selectivity ratio between the conductive layer and an undoped region in the predetermined mask pattern is less than a predetermined value.
As some optional embodiments, the step of etching the first mask pattern and the second mask pattern while etching the conductive layer using the first mask pattern and the second mask pattern includes the following stages:
when the doped region in the first mask pattern is etched away, the second mask pattern is etched by a small amount, and the conductive layer not covered by the predetermined mask pattern is also partially etched at the same time;
when the first mask pattern is completely removed, the second mask pattern is correspondingly etched, and the conductive layer which is not covered by the preset mask pattern is continuously etched at the same time;
when the second mask pattern is completely removed, the conductive layer not covered by the predetermined mask pattern is completely removed to form a plurality of conductive lines, the conductive layer corresponding to the region of the first mask pattern is partially etched, and the conductive layer corresponding to the region of the second mask pattern has a higher height as the conductive path.
As some optional embodiments, the etching the conductive layer using the first mask pattern and the second mask pattern includes:
removing the doped region in the first mask pattern;
etching the remaining first mask pattern and second mask pattern to completely remove the first mask pattern;
and removing part of the conductive layer in the area where the first mask pattern is located while removing the remaining second mask pattern, so as to form a conductive path in the conductive wire corresponding to the area of the second mask pattern.
As some alternative embodiments, the conductive layer not covered by the predetermined mask pattern is etched while the first mask pattern and the second mask pattern are etched and removed.
As some optional embodiments, before removing the doped region in the first mask pattern, the method further comprises:
etching the conductive layer by using the first mask pattern and the second mask pattern to form the conductive line; or alternatively
After removing the doped regions in the first mask pattern, the method further includes:
and etching the conductive layer by using the remaining first mask pattern and the second mask pattern to form the conductive line.
As some alternative embodiments, the forming a predetermined mask pattern on the conductive layer includes:
forming a core layer on the conductive layer;
forming a spacer on a sidewall of the core layer, the spacer serving as the predetermined mask pattern.
As some optional embodiments, the doping the first mask pattern includes:
the first partition wall is doped to form a doped region with a preset depth in the first partition wall, wherein the first partition wall is the doped partition wall, and the second partition wall is the undoped partition wall.
As some optional embodiments, the doping the first spacer includes:
forming a planarization layer on the conductive layer to fill the region between the spacers;
planarizing the planarizing layer to expose the core layer and the partition walls;
forming a mask layer on the surface of the planarization layer to shield the second partition wall;
and carrying out ion implantation on the first partition walls which are not shielded.
As some alternative embodiments, the planarization layer is an SOC material; or alternatively
The element implanted by the ion implantation is Ge.
As some optional embodiments, the method further comprises:
and removing the core layer and the planarization layer.
As some alternative embodiments, the doped region of the first spacer wall is removed at the same time as the core layer and/or the planarization layer is removed.
As some optional embodiments, a hard mask layer is further included between the conductive layer and the core layer and the planarization layer, and the removing the core layer and the planarization layer includes:
and taking the hard mask layer as an etching stop layer, and removing the core layer and the planarization layer.
As some optional embodiments, the etching the conductive layer using the first mask pattern and the second mask pattern includes:
and removing the hard mask layer and the conductive layer which are not covered by the first partition wall and the second partition wall by taking the first partition wall and the second partition wall as masks.
As some optional embodiments, the spacer layer further includes a liner layer under the conductive layer, the hard mask layer and the conductive layer, which are not covered by the first spacer and the second spacer, are removed by using the first spacer and the second spacer as masks, and the method further includes:
the liner layer not covered by the first and second barrier ribs is removed.
As some alternative embodiments, the backing layer includes at least one of TiN, taN, al, cu, ni, co, ru, ti, ta.
As some alternative embodiments, the conductive layer is a metallic conductive layer; or alternatively
The conductive layer includes at least one of Ru, co, mo, W, al, rh.
As some alternative embodiments, the forming a predetermined mask pattern on the conductive layer includes:
the predetermined mask pattern is formed by self-aligned multiple patterning.
In the method for forming the conductive interconnection structure, the doping is performed on the predetermined mask pattern, so that the etching rate of the doped region in the predetermined mask pattern is larger than that of the undoped region, conductive lines with different heights can be formed through a subsequent etching process, and the heights of the conductive lines corresponding to the region of the second mask pattern are higher, so that a conductive path is formed. The conductive path is formed by adopting a self-alignment process, the problem of alignment deviation between the conductive path and the conductive wire, which is possibly generated by adopting a mosaic process in the related art, is avoided, and meanwhile, compared with a subtractive etching process in the related art, the method has fewer process steps and does not need a precise mask pattern.
Drawings
FIG. 1 illustrates a schematic diagram of one method of forming a metal interconnect structure in the related art;
FIG. 2 illustrates a schematic diagram of another method of forming a metal interconnect structure in the related art;
fig. 3 to 11 are schematic views respectively showing semiconductor structures corresponding to respective steps in a method for forming a metal interconnection structure according to an embodiment of the present invention;
fig. 12 to 20 are schematic views respectively showing a semiconductor structure corresponding to each step in a method for forming a metal interconnection structure according to another embodiment of the present invention.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the present invention more apparent, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are some embodiments of the present invention, but not all embodiments of the present invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
It is to be understood by one skilled in the art that the present embodiments are merely illustrative of the claimed structures and methods that may be embodied in various forms. Furthermore, each of the examples given in connection with the various embodiments is intended to be illustrative, and not limiting. Moreover, the figures are not necessarily to scale, some features may be exaggerated to show details of particular components. Therefore, specific structural and functional details of the embodiments of the present invention are not to be interpreted as limiting, but merely as a representative basis for teaching one skilled in the art to variously employ the present methods and structures. It should also be noted that like and corresponding elements are denoted by like reference numerals.
In the following description, numerous specific details are set forth, such as specific structures, components, materials, dimensions, processing steps and techniques, in order to provide an understanding of various embodiments of the invention. However, it will be understood by those skilled in the art that the various embodiments of the invention may be practiced without these specific details. In other instances, well-known structures or processing steps have not been described in detail in order to avoid obscuring the present invention.
For purposes of the following description, the terms "upper," "right," "left," "vertical," "horizontal," "top," "bottom," and derivatives thereof shall relate to the structure and method as disclosed in the drawing figures of the specification. It will be understood that when an element as a layer, region or substrate is referred to as being "on" another element, it can be directly on the other element or intervening elements may also be present. In contrast, when an element is referred to as being directly on another element, there are no intervening elements between the two. It will also be understood that when an element is referred to as being "under" another element, it can be directly under the other element or intervening elements may be present. On the contrary. When an element is referred to as being directly under another element, there are no intervening elements present therebetween.
A related art method for forming a metal interconnection structure is provided, as shown in fig. 1, in which an insulating layer is formed on a metal interconnection line 11 using a damascene (damascene) process, a via (via) is formed in the insulating layer, and then a metal is filled in the via to form a conductive via 12, and the conductive via 12 is used to electrically connect a current metal interconnection line 11 with an upper metal interconnection line. However, this method is difficult to align with the underlying metal interconnect line 11 when forming the via hole, especially in the case where the line width of the wire is narrow; on the other hand, the metal interconnection line may have a line swing (line swing) phenomenon, so that deviation exists between the alignment of the conductive path 12 and the metal interconnection line 11, and the impedance of the metal interconnection structure is increased.
There is also provided a method of forming a metal interconnection structure, as shown in fig. 2, which uses a subtractive etching (substractive etch) process to form a mask pattern 13 at a position where a conductive via is to be formed, and then etches the metal interconnection line, with the unetched position being higher than the etched position, and the unetched position being used as a conductive via. However, this method requires the formation of a precise mask pattern 13 when the wire pitch (pitch) is very tight, and if there is a deviation in the mask pattern 13, it may result in the formation of undesired conductive paths at locations where the formation of conductive paths is not desired.
The technical scheme disclosed by the embodiment of the invention is described in detail below with reference to the accompanying drawings.
Embodiments of the present invention provide a method of forming a conductive interconnect structure, which may include the following steps.
S11, forming a preset mask pattern on the conductive layer.
The semiconductor structure shown in fig. 3 includes a substrate 100, a spacer layer (liner) 110 formed on the substrate 100, a conductive layer 120 formed on the spacer layer 110, and a predetermined mask pattern 140 formed on a hard mask layer 130.
The substrate 100 may be comprised of a silicon-containing material. The silicon-containing material includes, but is not limited to, silicon, single crystal silicon, polysilicon, siGe, single crystal SiGe, polycrystalline SiGe or carbon doped silicon (Si: C), amorphous silicon, and the like, or combinations thereof, and the substrate 100 may be a single layer or a plurality of layers. The substrate 100 may also be composed of other semiconductor materials such as germanium (Ge) and compound semiconductor substrates, which may be, for example, III-V type semiconductor substrates such as gallium arsenide (GaAs) and the like.
The liner layer 110 may be formed by sputtering, chemical Vapor Deposition (CVD), atomic Layer Deposition (ALD), or the like, and the liner layer 110 may include a conductive material such as titanium nitride (TiN) or tantalum nitride (TaN). In some embodiments, the liner layer 110 may also be composed of other conductive materials, such as aluminum (Al), copper (Cu), nickel (Ni), cobalt (Co), ruthenium (Ru), titanium (Ti), tantalum (Ta), or combinations thereof.
The conductive layer 120 may be a metal conductive layer or a nonmetal conductive layer. In some alternative implementations of embodiments of the present invention, the conductive layer 120 is a metallic conductive layer, and may include ruthenium (Ru), cobalt (Co), molybdenum (Mo), tungsten (W), aluminum (Al), or rhodium (Rh), or alloys thereof. Conductive layer 120 may be formed using, for example, CVD, PECVD, PVD or other deposition processes.
The hard mask layer 130 is a material used as an etch mask in a semiconductor process. The hard mask layer 130 may be composed of a metal or a dielectric material, such as silicon nitride, silicon oxide, or a combination of silicon nitride and silicon oxide, etc., which may be formed using a process such as Low Pressure Chemical Vapor Deposition (LPCVD).
The predetermined mask pattern 140 may be composed of any dielectric material, such as dielectric oxide, dielectric nitride, and/or dielectric oxynitride. In some embodiments, the mask pattern 140 may be composed of a non-conductive low capacitance dielectric material, such as silicon dioxide. To obtain a finer mask pattern 140, it may be formed by self-aligned multiple patterning, such as self-aligned double patterning or self-aligned quadruple patterning.
Those skilled in the art will appreciate that the substrate 100, liner layer 110, and hard mask layer 130 are not optional in the above description, and that one or more of the substrate 100, liner layer 110, and hard mask layer 130 may not be formed in some alternative implementations of embodiments of the invention.
In the example of fig. 3, other layers may be further disposed between the substrate 100 and the conductive layer 120, and the present invention is not limited to the metal interconnection layer where the conductive layer 120 is disposed being the lowest metal interconnection layer, and may be any interconnection layer. That is, other metal interconnect layers may be in direct contact with conductive layer 120.
S12, doping the first mask pattern to form a doped region with a preset depth in the first mask pattern, wherein the first mask pattern is a doped preset mask pattern, and the second mask pattern is an undoped preset mask pattern.
As shown in fig. 4, the first mask pattern 141 may be doped by ion implantation or the like, for example, ge may be implanted into the first mask pattern 141, and the implantation depth of ion implantation may be precisely controlled by controlling the implantation energy and the implantation dose of ion implantation. As will be seen hereinafter, the ion implantation depth is related to the height of the conductive path (via) to be subsequently formed. In the subsequent etching process, the etching rate of the region subjected to ion implantation is higher than that of the region not subjected to ion implantation.
When the doping process is performed, the regions not to be doped may be masked with photoresist (not shown), so that the first and second mask patterns 141 and 142 can be obtained.
S13, etching the conductive layer by using the first mask pattern and the second mask pattern to form a conductive interconnection structure; wherein the conductive line corresponding to the region of the second mask pattern has a high height and is formed as a conductive path.
The step S13 may be performed by one-step etching or step etching. For clarity, the manner of step etching is described in detail herein.
In some optional implementations of the embodiment of the present invention, the step S13 may include:
s131, removing the doped region in the first mask pattern.
As shown in fig. 5, the doped region in the first mask pattern 141 may be removed using an etching process. Since a partial region of the first mask pattern 141 is doped, an etching rate of the doped region is greater than that of the undoped region when the etching process is performed, so that the doped region can be removed. In some alternative embodiments, the conductive layer not covered by the predetermined mask pattern 140 is etched while the doped region of the first mask pattern 141 is etched away to save process steps.
And S132, etching the conductive layer by using the residual first mask pattern and the second mask pattern to form a conductive wire.
After this etching, a number of conductive lines 121 are formed in the semiconductor structure, as shown in fig. 6. Note that the present invention is not limited thereto, and the conductive layer 120 may be etched with the first mask pattern 141 and the second mask pattern 142 without removing the doped region to form the conductive line 121 before step S131.
It will be appreciated by those skilled in the art that step S132 is optional, and in some alternative embodiments, the conductive layer 120 not covered by the predetermined mask pattern may be etched at the same time as the first mask pattern 141 and the second mask pattern 142 are etched, so that a separate step of etching to form the conductive lines 121 is not required, to save process steps.
S133, etching the remaining first mask pattern and the second mask pattern to completely remove the first mask pattern.
As shown in fig. 7, since the second mask pattern 142 has a height greater than that of the remaining first mask pattern 141, after the first mask pattern 141 is completely removed, a portion of the second mask pattern 142 remains.
S134, removing part of the conductive layer of the area where the first mask pattern is located while removing the remaining second mask pattern, so as to form a conductive path in the conductive wire of the area corresponding to the second mask pattern.
After step S133, etching of the semiconductor structure continues. In this etching process, an etching gas with a relatively low etching selectivity between the conductive line 121 and the second mask pattern 142 is selected, so that the conductive line 121 exposed after the first mask pattern 141 is completely removed is etched while the remaining second mask pattern 142 is etched, so that after the remaining second mask pattern 142 is completely removed, a portion of the conductive line in the region where the first mask pattern 141 is located is also removed, thereby forming the conductive line 121 with different heights. The height of the conductive line corresponding to the region of the first mask pattern 141 is low and the height of the conductive line corresponding to the region of the second mask pattern 142 is high, thereby forming the conductive via 123, as shown in fig. 8 and 9.
As can be seen from the above description, the main concept of the embodiment of the present invention is that by doping a predetermined mask pattern such that the etching rate of a doped region in the predetermined mask pattern is greater than that of an undoped region, conductive lines of different heights can be formed through a subsequent etching process, the height of the conductive lines corresponding to the region of the first mask pattern 141 is lower, and the height of the conductive lines corresponding to the region of the second mask pattern 142 is higher, thereby forming the conductive via 123. Based on this concept, in order to further reduce the manufacturing process of the conductive interconnection structure, the above step S13 may be further implemented by one-step etching, thereby reducing the manufacturing cost of the conductive interconnection structure. In some optional implementations of the embodiment of the present invention, the step S13 may include:
etching the first and second mask patterns 141 and 142 while etching the conductive layer 120 using the first and second mask patterns 141 and 142; wherein an etch selectivity ratio between the conductive layer 120 and the undoped region in the predetermined mask pattern 140 is less than a predetermined value. That is, the etching selectivity between the conductive layer 120 and the undoped region in the predetermined mask pattern 140 is relatively small, the predetermined mask pattern 140 is etched at the same time when the conductive layer 120 is removed, and by selecting an appropriate etching gas, the removal of the conductive layer 120 not covered by the predetermined mask pattern 14 is completely removed when the etching of the second mask pattern 142 is completed, thereby forming the plurality of conductive lines 121.
The one-step etching step will be described in detail in stages.
In the step 1, when the semiconductor structure shown in fig. 4 is etched, the doped region in the first mask pattern 141 is etched and removed, and since the etching rate of the doped region in the predetermined mask pattern 140 is greater than that of the undoped region, the second mask pattern 142 is etched only slightly, and there is also a certain etching effect on the conductive layer 120 not covered by the predetermined mask pattern 140, and the exposed portion of the conductive layer 120 is also etched partially at the same time, so that a plurality of grooves 122 are formed, as shown in fig. 10.
Stage 2. Continuing to etch the semiconductor structure shown in fig. 10, when the first mask pattern 141 is completely removed, the remaining undoped first mask pattern 141 has the same etching rate as the second mask pattern 142, so that the second mask pattern 142 is correspondingly etched, and the height becomes low. Meanwhile, since the etching selectivity between the conductive layer 120 and the undoped region in the predetermined mask pattern 140 is smaller than a predetermined value, the conductive layer 120 not covered by the predetermined mask pattern 140 is also correspondingly etched, and the depth of the groove 122 becomes large, as shown in fig. 11.
Continuing with the etching of the semiconductor structure shown in fig. 11, when the second mask pattern 142 is completely removed, the conductive layer 120 not covered by the predetermined mask pattern 140 is completely removed, thereby forming a plurality of conductive lines 121 having different heights. Meanwhile, the conductive layer 120 corresponding to the region of the first mask pattern 141 is partially etched, the height of the conductive line corresponding to the region of the first mask pattern 141 is lower, and the height of the conductive line corresponding to the region of the second mask pattern 142 is higher as the conductive via 123, as shown in fig. 8 and 9.
In the method for forming a conductive interconnection structure according to the embodiment of the present invention, by doping a predetermined mask pattern, the etching rate of a doped region in the predetermined mask pattern is greater than the etching rate of an undoped region, so that conductive lines with different heights can be formed through a subsequent etching process, and the heights of the conductive lines corresponding to the region of the second mask pattern 142 are higher, thereby forming the conductive via 123. The conductive via 123 is formed by a self-aligned process, which does not have the problem of misalignment between the conductive via and the conductive line that may occur by a damascene process in the related art, and has fewer process steps and does not require a precise mask pattern compared to a subtractive etching process in the related art.
Hereinafter, a method of forming a conductive interconnection structure provided by an embodiment of the present invention will be described in more detail, and may include the following steps.
S101. a core layer (mandril) is formed on the conductive layer.
As shown in fig. 12, the specific descriptions of the substrate 100, the pad layer 110, the conductive layer 120, and the hard mask layer 130 may be referred to in the corresponding descriptions above, and will not be repeated here.
The core layer 150 may be composed of, for example, silicon nitride (SiN), silicon carbonitride (SiCN), siOCN, siBCN, or other insulating materials known in the art. Specifically, it may be formed by depositing an insulating layer on the conductive layer 120 and then performing an etching process on the insulating layer. The etching process may be dry etching or laser ablation (laser ablation) or any process known in the art that can achieve selective removal, without limitation.
S102, forming a spacer on the side wall of the core layer, wherein the spacer is used as a preset mask pattern.
As shown in fig. 13, the spacers 140 may be composed of any dielectric material, such as dielectric oxide, dielectric nitride, and/or dielectric oxynitride. In some embodiments, the spacer 140 may be comprised of a non-conductive low capacitance dielectric material, such as silicon dioxide. The process of forming the barrier ribs 140 may include depositing an insulating material, such as silicon nitride, on the exposed surfaces of the core layer 150, the hard mask layer 130, which may be deposited using, for example, CVD, plasma Enhanced Chemical Vapor Deposition (PECVD), physical Vapor Deposition (PVD), or other deposition process. An anisotropic etch process may then be used, wherein the forward etch rate is greater than the lateral etch rate, thereby etching away horizontal portions of the deposited insulating material, thereby forming the spacer walls 140 at the sidewalls of the core layer 150.
While the process of forming the barrier ribs 140 as the predetermined mask pattern by self-aligned double patterning has been described above, it will be understood by those skilled in the art that it is also possible to form a finer predetermined mask pattern by self-aligned quad patterning or more.
S103, forming a planarization layer on the conductive layer to fill the area between the partition walls.
S104, carrying out planarization treatment on the planarization layer to expose the core layer and the partition wall.
As shown in fig. 14, the planarization layer 160 may be made of SOC (silicon on carbon) material, for example, and may be formed on the conductive layer 120 by deposition, such as chemical vapor deposition, or the like. After the planarization layer 160 is deposited, the surface of the core layer 150 is also covered by the planarization layer 160, and thus, a planarization process is performed to expose the surface of the core layer 150, thereby realizing filling the area between the barrier ribs 140 and obtaining a planar surface for subsequent process steps.
S105, forming a mask layer on the surface of the planarization layer to shield the second partition wall.
As shown in fig. 15, a mask layer 170 is formed on the surface of the planarization layer 160 to block the second barrier ribs 142. The region corresponding to the mask layer 170 is the region where the conductive path is to be formed.
S106, ion implantation is carried out on the first partition walls 141 which are not shielded.
As shown in fig. 16, after ion implantation, a doped region of a predetermined depth is formed in the first barrier rib 141. Unlike the related art shown in fig. 2, the mask pattern 13 is a mask for etching, which needs to be precisely formed at a corresponding position, and when the wire pitch is as low as the nano-scale, it is difficult for the mask pattern for etching to achieve a corresponding precision process. In the present embodiment, the mask layer 170 is a mask for ion implantation, and the requirement for the mask position accuracy is relatively low, and even if there is a slight shift in the position of the mask layer 170, the ion implantation of the first barrier rib 141 is not affected, for example, the shift in the position of the mask layer 170 can be overcome by slightly adjusting the ion implantation angle or the like.
The mask layer 170 may be, for example, photoresist, and after the ion implantation process is completed, the mask layer 170 may be removed through a photoresist removal process.
And S107, removing the planarization layer and the core layer.
The semiconductor structure after removal of the core layer 150 and the planarizing layer 160 is shown in fig. 17. In step S107, the core layer 150 and the planarization layer 160 may be removed using the hard mask layer 130 as an etch stop layer.
In some alternative implementations of embodiments of the present invention, the core layer 150 and the planarizing layer 160 may be removed simultaneously or in steps.
In alternative implementations of embodiments of the present invention, the doped regions of the first barrier ribs 141 may be removed at the same time as the core layer 150 and/or the planarization layer 160 are removed.
S108, using the first partition wall 141 and the second partition wall 142 as masks, removing the hard mask layer 130 and the conductive layer 120 which are not covered by the first partition wall 141 and the second partition wall 142.
In this step, the etching of the hard mask layer 130 and the conductive layer 120 may be completed in a one-step etching process. Of course, the etching of the hard mask layer 130 and the conductive layer 120 may be performed in separate steps, so as to form a plurality of conductive lines 121.
In some alternative implementations of the present embodiment, the liner layer 110 not covered by the first and second barrier ribs 141 and 142 is removed at the same time as the hard mask layer 130 and the conductive layer 120 not covered by the first and second barrier ribs 141 and 142 are removed, as shown in fig. 18.
In the example of fig. 18, other layers may be further disposed between the substrate 100 and the pad layer 110 and the conductive line 121, and the metal interconnect layer where the conductive line 121 is disposed is not limited to the lowest metal interconnect layer in the present invention, and may be any interconnect layer.
S109, etching the remaining first mask pattern and the second mask pattern, and completely removing the second mask pattern to form a conductive path in the conductive line corresponding to the region of the second mask pattern.
In this step, since the height of the second mask pattern 142 is greater than the remaining first mask pattern 141, a portion of the second mask pattern 142 remains after the first mask pattern 141 is completely removed. In the subsequent etching process, since the etching selectivity between the conductive line 121 and the second mask pattern 142 is relatively low, the conductive line 121 exposed after the first mask pattern 141 is completely removed is etched while the remaining second mask pattern 142 is etched, so that after the remaining second mask pattern 142 is completely removed, a portion of the conductive line in the region where the first mask pattern 141 is located is also removed, thereby forming the conductive line 121 with different heights. The height of the conductive line corresponding to the region of the first mask pattern 141 is low and the height of the conductive line corresponding to the region of the second mask pattern 142 is high, thereby forming the conductive via 123, as shown in fig. 19.
In this step, the hard mask layer 130 remaining on the conductive lines 121 is also removed.
S110, forming an interlayer insulating layer coating the conductive interconnection structure, and performing planarization treatment to expose the conductive paths.
As shown in fig. 20, an interlayer insulating layer 180 is formed on the substrate 100 to cover the entire conductive interconnect structure and is planarized, so that an upper conductive interconnect structure can be formed on the interlayer insulating layer 180, and the upper conductive interconnect structure can be electrically connected to the current layer conductive interconnect structure through a conductive via 123.
In the method for forming a conductive interconnection structure according to the embodiment of the present invention, by doping a predetermined mask pattern, the etching rate of a doped region in the predetermined mask pattern is greater than the etching rate of an undoped region, so that conductive lines with different heights can be formed through a subsequent etching process, and the heights of the conductive lines corresponding to the regions of the second barrier ribs 142 are higher, thereby forming the conductive vias 123. The conductive via 123 is formed by a self-aligned process, which does not have the problem of misalignment between the conductive via and the conductive line that may occur by a damascene process in the related art, and has fewer process steps and does not require a precise mask pattern compared to a subtractive etching process in the related art.
The foregoing embodiments of the present invention mainly describe differences between the embodiments, and as long as there is no contradiction between different optimization features of the embodiments, the embodiments may be combined to form a better embodiment, and in view of brevity of line text, no further description is provided herein.
The foregoing is merely exemplary of the present invention and is not intended to limit the present invention. Various modifications and variations of the present invention will be apparent to those skilled in the art. Any modification, equivalent replacement, improvement, etc. which come within the spirit and principles of the invention are to be included in the scope of the claims of the present invention.
Claims (18)
1. A method of forming a conductive interconnect structure, comprising:
forming a predetermined mask pattern on the conductive layer;
doping a first mask pattern to form a doped region with a predetermined depth in the first mask pattern, wherein the first mask pattern is the doped predetermined mask pattern, and the second mask pattern is the undoped predetermined mask pattern; wherein the etching rate of the doped region is greater than that of the undoped region;
etching the conductive layer by using the first mask pattern and the second mask pattern to form a conductive interconnection structure; wherein the conductive line corresponding to the region of the second mask pattern has a high height and is formed as a conductive path.
2. The method of claim 1, wherein etching the conductive layer using the first mask pattern and the second mask pattern comprises:
etching the first mask pattern and the second mask pattern while etching the conductive layer using the first mask pattern and the second mask pattern;
wherein an etching selectivity ratio between the conductive layer and an undoped region in the predetermined mask pattern is less than a predetermined value.
3. The method of claim 2, wherein the step of etching the first mask pattern and the second mask pattern while etching the conductive layer with the first mask pattern and the second mask pattern comprises the steps of:
when the doped region in the first mask pattern is etched away, the second mask pattern is etched by a small amount, and the conductive layer not covered by the predetermined mask pattern is also partially etched at the same time;
when the first mask pattern is completely removed, the second mask pattern is correspondingly etched, and the conductive layer which is not covered by the preset mask pattern is continuously etched at the same time;
when the second mask pattern is completely removed, the conductive layer not covered by the predetermined mask pattern is completely removed to form a plurality of conductive lines, the conductive layer corresponding to the region of the first mask pattern is partially etched, and the conductive layer corresponding to the region of the second mask pattern has a higher height as the conductive path.
4. The method of claim 1, wherein etching the conductive layer using the first mask pattern and the second mask pattern comprises:
removing the doped region in the first mask pattern;
etching the remaining first mask pattern and second mask pattern to completely remove the first mask pattern;
and removing part of the conductive layer in the area where the first mask pattern is located while removing the remaining second mask pattern, so as to form a conductive path in the conductive wire corresponding to the area of the second mask pattern.
5. The method according to claim 4, wherein the conductive layer not covered by the predetermined mask pattern is etched while etching the first mask pattern and the second mask pattern.
6. The method of claim 4, wherein prior to removing the doped region in the first mask pattern, the method further comprises:
etching the conductive layer by using the first mask pattern and the second mask pattern to form the conductive line; or alternatively
After removing the doped regions in the first mask pattern, the method further includes:
and etching the conductive layer by using the remaining first mask pattern and the second mask pattern to form the conductive line.
7. The method of claim 1, wherein forming a predetermined mask pattern on the conductive layer comprises:
forming a core layer on the conductive layer;
forming a spacer on a sidewall of the core layer, the spacer serving as the predetermined mask pattern.
8. The method of claim 7, wherein doping the first mask pattern comprises:
the first partition wall is doped to form a doped region with a preset depth in the first partition wall, wherein the first partition wall is the doped partition wall, and the second partition wall is the undoped partition wall.
9. The method of claim 8, wherein doping the first spacer comprises:
forming a planarization layer on the conductive layer to fill the region between the spacers;
planarizing the planarizing layer to expose the core layer and the partition walls;
forming a mask layer on the surface of the planarization layer to shield the second partition wall;
and carrying out ion implantation on the first partition walls which are not shielded.
10. The method of claim 9, wherein the planarization layer is an SOC material; or alternatively
The element implanted by the ion implantation is Ge.
11. The method as recited in claim 9, further comprising:
and removing the core layer and the planarization layer.
12. The method of claim 11, wherein the doped region of the first spacer wall is removed at the same time as the core layer and/or the planarization layer is removed.
13. The method of claim 11, further comprising a hard mask layer between the conductive layer and the core layer and the planarization layer, the removing the core layer and the planarization layer comprising:
and taking the hard mask layer as an etching stop layer, and removing the core layer and the planarization layer.
14. The method of claim 13, wherein etching the conductive layer using the first mask pattern and the second mask pattern comprises:
and removing the hard mask layer and the conductive layer which are not covered by the first partition wall and the second partition wall by taking the first partition wall and the second partition wall as masks.
15. The method of claim 14, wherein the underlying conductive layer further comprises a liner layer, wherein the removing the hard mask layer and the conductive layer not covered by the first and second spacers using the first and second spacers as a mask, further comprises:
the liner layer not covered by the first and second barrier ribs is removed.
16. The method of claim 15, wherein the liner layer comprises at least one of TiN, taN, al, cu, ni, co, ru, ti, ta.
17. The method of claim 1, wherein the conductive layer is a metallic conductive layer; or alternatively
The conductive layer includes at least one of Ru, co, mo, W, al, rh.
18. The method of claim 1, wherein forming a predetermined mask pattern on the conductive layer comprises:
the predetermined mask pattern is formed by self-aligned multiple patterning.
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| JP2007335660A (en) * | 2006-06-15 | 2007-12-27 | Toshiba Corp | Method of forming pattern of semiconductor device |
| JP2012054307A (en) * | 2010-08-31 | 2012-03-15 | Tokyo Electron Ltd | Manufacturing method of semiconductor device |
| CN114068453A (en) * | 2020-07-30 | 2022-02-18 | 中芯国际集成电路制造(上海)有限公司 | Interconnect structure and method of forming the same |
| CN115312385A (en) * | 2022-08-04 | 2022-11-08 | 长鑫存储技术有限公司 | Method for manufacturing semiconductor structure |
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| JP2007335660A (en) * | 2006-06-15 | 2007-12-27 | Toshiba Corp | Method of forming pattern of semiconductor device |
| JP2012054307A (en) * | 2010-08-31 | 2012-03-15 | Tokyo Electron Ltd | Manufacturing method of semiconductor device |
| CN114068453A (en) * | 2020-07-30 | 2022-02-18 | 中芯国际集成电路制造(上海)有限公司 | Interconnect structure and method of forming the same |
| CN115312385A (en) * | 2022-08-04 | 2022-11-08 | 长鑫存储技术有限公司 | Method for manufacturing semiconductor structure |
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