JP2007335660A - Method of forming pattern of semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of forming a wiggle-shaped pattern of a semiconductor device not by lithography. <P>SOLUTION: The method of forming a pattern of a semiconductor device comprises steps of depositing a processing film on a semiconductor substrate, depositing a mask film having a varying etching characteristic on the processing film by doping an impurity in the processing film, forming a line pattern on the mask film, selectively doping an impurity in a desired region of the mask film having the line pattern formed thereon to provide a varying etching rate, forming a mask pattern having partially different line widths and including a wiggle shape by selectively etching the line pattern of the mask film, and forming a wiggle shaped pattern by etching the processing film with the mask pattern used as a mask. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a pattern formation method for a semiconductor device, and more particularly to a pattern formation method including a wiggle shape.

  In addition to miniaturization of semiconductor devices and the layout of various patterns and / or considering the function of each pattern, a wiggle shape in which a thick portion and a thin portion are mixed rather than a linear shape of each pattern. It may be preferable to use this pattern. For example, a word line composed of a gate electrode is an example. In the prior art, a wiggle-shaped, for example, gate electrode pattern is formed by patterning by lithography.

One improved technique for forming a wiggle shaped pattern by lithography is disclosed in US Pat. In this technique, in order to pattern a wiggle shape having a triangular bent shape, a mask in which an oblique component and a vertical and horizontal component are combined to form a triangular bent portion as a whole is used. However, in this process, a complicated pattern must be formed by lithography, and a lithography margin (exposure margin, focus margin) cannot be secured sufficiently.
Japanese Patent Laid-Open No. 10-65027

  The present invention provides a pattern forming method for a semiconductor device that forms a wiggle-shaped pattern without using lithography.

  According to one aspect of the present invention, there is provided a pattern forming method for a semiconductor device, the step of depositing a film to be processed above a semiconductor substrate, and the step of depositing a mask film whose etching characteristics are changed by adding an impurity onto the film to be processed. A step of forming a line pattern on the mask film, a step of selectively adding an impurity that changes an etching rate to a desired region of the mask film on which the line pattern is formed, and the line of the mask film A step of selectively etching the pattern to form a mask pattern including a wiggle shape partially different in line width; and a step of etching the film to be processed using the mask pattern as a mask to form a wiggle shape pattern. It has.

  According to another aspect of the present invention, there is provided a pattern forming method for a semiconductor device, comprising: depositing a film to be processed on a semiconductor substrate; and a mask film whose etching characteristics are changed by adding an impurity to the film to be processed. A step of depositing, a step of adding an impurity that changes an etching rate to the mask film in a line pattern, and a step of selectively adding the impurity to a desired region of the mask film adjacent to the line pattern to which the impurity is added. A step of adding, a step of selectively etching the mask film to form a mask pattern including a wiggle shape having partially different line widths, and a wiggle shape by etching the film to be processed using the mask pattern as a mask Forming a pattern.

  According to the present invention, there is provided a pattern forming method of a semiconductor device that forms a wiggle shape pattern without using lithography.

  Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the figure, corresponding parts are indicated by corresponding reference numerals. The following embodiment is shown as an example, and various modifications can be made without departing from the spirit of the present invention.

  The present invention discloses a method of manufacturing a semiconductor device in which a wiggle-shaped pattern in which a portion having a large line width and a portion having a thin line width are mixed is formed without using lithography.

  Here, the method for forming a pattern of a semiconductor device according to various embodiments will be described by taking as an example the case where the gate electrode is formed in a wiggle shape pattern, but is not limited thereto.

  According to an embodiment of the present invention, after patterning a straight pattern on a mask film by lithography, or after forming a latent image of a straight pattern, a wiggle protrusion or recess is formed by a method other than lithography, such as ion implantation. A hard mask pattern having a wiggle shape is formed by adding by a method using. As a result, a wiggle-shaped pattern having portions with different line widths can be formed without depending on lithography.

(First embodiment)
The first embodiment of the present invention uses a straight pattern formed by lithography on a mask film formed on a film to be processed, and additionally processes a wiggle protrusion by impurity implantation and etching to form a wiggle shape pattern. It is an example of the pattern formation method of the semiconductor device to form.

  In this embodiment, a desired wiggle shape pattern is formed by selectively adding impurities to a desired region of a mask film used as a hard mask when patterning a film to be processed to change the etching characteristics of the mask film. . An example of a method of forming a pattern of a gate electrode having a wiggle shape of the semiconductor device according to the present embodiment will be described with reference to FIGS. Each drawing (a) is a plan view, and each drawing (b) is a process cross-sectional view along the cutting line XX shown in (a).

Referring to FIG. 1, first and second gate electrode materials 14, 16, a cap insulating film 18 and a mask film 20 are deposited on a semiconductor substrate 10 via a gate insulating film 12. As the semiconductor substrate 10, for example, a silicon substrate can be used. As the gate insulating film 12, for example, a silicon oxide film (SiO ₂ film) can be used. As the first gate electrode material 14, a dopant, for example, polysilicon doped with phosphorus (P) at a high concentration, and as the second gate electrode material 16, for example, tungsten silicide (WSi) can be used. For example, a silicon nitride film (Si ₃ N ₄ film) can be used as the cap insulating film 18.

  The mask film 20 is a hard mask for patterning the gate electrode, can secure a sufficient etching selection ratio when processing the underlying film, and has processing characteristics between a portion where impurities are introduced and a portion where impurities are not introduced. For example, the film can change the etching rate. As the mask film 20, for example, amorphous silicon not doped with impurities (non-doped a-Si) can be used.

  A straight pattern A is patterned on the mask film 20 by lithography and etching. The straight pattern A is processed to have a width wider than the finished width of the gate pattern. In this way, the straight pattern A shown in FIG. 1 is formed on the non-doped a-Si mask film 20.

Next, referring to FIG. 2, a second resist film 32 is formed so as to cover the patterned mask film 20. In the second resist film 32, an ion implantation mask pattern 32W for forming a wiggle protrusion B is opened. The opening 32W has a wider opening area than the protrusion B of the wiggle, that is, the area B to be ion-implanted. As shown in FIG. 2, the impurity 40 is ion-implanted from one oblique direction (in the upper right direction in FIG. 2) using the second resist film 32 as a mask, and shadowing by the second resist film 32 is used. Then, the impurity 40 is introduced only into the region B on one side (a part on the right side of the straight pattern A) of the mask film 20 exposed in the opening. Thereby, the ion-implanted region B becomes a mask film (a-Si) 21 doped with the impurity 40. For example, boron difluoride (BF ₂ ) can be used as the impurity 40 to be implanted. By doping with boron, the etching rate of the alkaline solution of a-Si can be reduced. In this manner, only the region where the wiggle protrusion B of the mask film 20 is to be formed can be selectively used as the mask film 21 doped with impurities.

  When the second resist film 32 is peeled off, as shown in FIG. 3, the mask film 20 includes a straight pattern A composed of a non-doped a-Si mask film 20 and a mask film 21 doped with impurities in a part thereof. A region B is formed.

  Next, referring to FIG. 4, the non-doped a-Si region A of the mask film 20 is selectively etched. This selective etching can be performed using, for example, an alkaline solution such as potassium hydroxide (KOH) or choline. By this selective etching, the non-doped mask film 20 is etched and receded as a whole, but the region B composed of the a-Si mask film 21 doped with impurities has a slow etching rate, so that the wiggle-shaped protrusion B Is left behind. In this way, as shown in FIG. 4, a hard mask HM (20 + 21) having a desired wiggle shape can be formed.

Referring to FIG. 5, anisotropic etching is performed by, for example, RIE (reactive ion etching) using hard mask HM as a mask, and cap Si ₃ N ₄ film 18, WSi film 16, and polysilicon film 14 are sequentially formed. The gate electrode GE having a wiggle shape can be formed by patterning. Although the hard mask HM may be removed during this etching, the cap Si ₃ N ₄ film 18 is first processed so as to have the same planar pattern as the hard mask HM. Therefore, even if the hard mask HM is removed, the cap Si ₃ N ₄ film 18 can be used as an etching mask, so that the finished shape of the gate electrode GE is not affected.

  In the above embodiment, non-doped a-Si is used as the mask film 20, and boron (B) is used as the impurity 40 for changing the etching rate. However, the etching rate can also be changed by, for example, a combination using boron-doped a-Si as a mask film and phosphorus (P) as an impurity that changes the etching rate. In this case, phosphorus is doped to the same level or higher than the boron concentration. As a result, contrary to the above embodiment, the etching rate of the region doped with phosphorus is faster than the etching rate of the undoped region.

  Further, the semiconductor device using the pattern forming method according to the present embodiment is completed by performing processes such as doping and wiring necessary for the semiconductor device.

  In the present embodiment, since the pattern formed by lithography is the simple straight pattern A and the mask pattern 32W having a large opening, various margins in lithography can be sufficiently secured.

  As described above, according to the present embodiment, it is possible to provide a pattern forming method for a semiconductor device that forms a wiggle-shaped pattern without using lithography.

(Second Embodiment)
In the first embodiment described above, the hard mask gate pattern made of non-doped a-Si is partially doped with an impurity that slows the etching rate, and then etched entirely, thereby having a wiggle-shaped protrusion. The pattern was processed. The second embodiment of the present invention is an example of a pattern formation method for a semiconductor device in which impurities that slow down the etching rate are formed on the entire line-shaped portion and projection portion where a wiggle-shaped gate pattern of a hard mask is to be formed. . According to the present embodiment, it is possible to provide a pattern forming method that suppresses variation in dimensions.

  An example of the pattern forming method of the semiconductor device according to the present embodiment will be described with reference to FIGS. Each drawing (a) is a plan view, and each drawing (b) is a process cross-sectional view along the cutting line XX shown in (a).

  Similar to the first embodiment, the first and second gate electrode materials 14 and 16, the cap insulating film 18, and the mask film 20 are deposited on the semiconductor substrate 10 via the gate insulating film 12.

Referring to FIG. 6, an inverted pattern (negative pattern) of straight gate pattern C to be formed is formed on first resist film 30 by lithography. Impurities 40, for example, BF ₂ are ion-implanted into the mask film 20 exposed in the opening of the first resist film 30, that is, the region where the gate pattern C is to be formed. Thereby, the region C becomes the mask film 21 made of a-Si doped with impurities.

Next, referring to FIG. 7, as in the first embodiment, the first resist film 30 is removed, and a second resist film 32 is formed on the entire surface. Then, an ion implantation mask pattern 32W is opened in the second resist film 32 in order to form a wiggle protrusion D. The opening 32W has a wider opening area than the protrusion D of the wiggle, that is, the area D to be ion-implanted. In order to introduce the impurity 40 into the region D (right side in FIG. 7) adjacent to the gate pattern C of the mask film 20 exposed in the opening 32W, as shown in FIG. From above, for example, BF ₂ is ion-implanted. In this way, only the region C + D that becomes the wiggle-shaped gate pattern can be selectively used as the mask film 21 doped with the impurity 40.

  Referring to FIG. 8, the second resist film 32 is peeled off, and the region of the mask film 20 where impurities are not introduced is selectively removed with, for example, an alkaline etching solution. In this way, a hard mask HM (C + D) having a wiggle shape made of the mask film 21 doped with the impurity 40 can be formed.

Thereafter, using the hard mask HM formed in this manner as a mask, anisotropic etching is performed, for example, by RIE, and the cap Si ₃ N ₄ film 18, WSi film 16, and polysilicon film 14 are sequentially patterned to form a wiggle. A gate electrode having a shape can be formed. Since the structure of the formed gate electrode is the same as that of FIG. 5, the drawing is omitted.

  Further, the semiconductor device using the pattern forming method according to the present embodiment is completed by performing processes such as doping and wiring necessary for the semiconductor device.

  In the present embodiment, since the pattern formed by lithography is the simple straight pattern C and the mask pattern 32W having a large opening, various margins in lithography can be sufficiently secured. Compared with the first embodiment, the dimensional variation caused by the selective etching of the hard mask pattern can be reduced.

  Therefore, according to the present embodiment, it is possible to provide a pattern forming method for a semiconductor device that forms a wiggle-shaped pattern without using lithography.

(Third embodiment)
The third embodiment of the present invention is an example of a pattern forming method for a semiconductor device in which a wiggle-shaped gate pattern is formed using a two-layer hard mask.

  An example of the pattern forming method of the semiconductor device according to the present embodiment will be explained with reference to FIGS. Each drawing (a) is a plan view, and each drawing (b) is a process cross-sectional view along the cutting line XX shown in (a).

  Similar to the first and second embodiments, the first and second gate electrode materials 14 and 16 and the cap insulating film 18 are deposited on the semiconductor substrate 10 via the gate insulating film 12.

Referring to FIG. 9, a two-layer hard mask film 20 including a first mask film 22 and a second mask film 24 is deposited on the cap insulating film 18. The first mask film 22 is a film that can control the etching selectivity between a doped region and an undoped region by doping impurities, and for example, non-doped a-Si can be used. The second mask film 24 is a film whose etching selectivity does not substantially change even when the impurity is doped. For example, a Si ₃ N ₄ film can be used.

Next, a reverse pattern (negative pattern) of the straight gate pattern E to be formed is formed on the first resist film 30 by lithography. The second mask film 24 exposed in the opening of the first resist film 30 is further removed by anisotropic etching, for example, RIE. An impurity 40, for example, BF ₂ is ion-implanted into the exposed first mask film 22, that is, the region where the gate pattern E is to be formed. Thereby, the region where the gate pattern E of the first mask film 22 is to be formed becomes the first mask film 23 doped with the impurity 40.

  Next, referring to FIG. 10, as in the second embodiment, the first resist film 30 is removed to form a second resist film 32 on the entire surface. Then, a mask pattern 32 W for forming the wiggle protrusion F is opened in the second resist film 32. The opening 32W has a wider opening area than the protrusion F of the wiggle, that is, the area F to be ion-implanted. The second mask film 24 exposed in the opening 32W is removed to expose the first mask film 22 in the region where the wiggle protrusion F is to be formed.

Next, referring to FIG. 11, for example, BF ₂ is ion-implanted from one diagonal direction (upwardly to the right) using the second resist film 32 and the second hard mask 24 as a mask to form the gate pattern E. Impurities 40 are introduced into the region F on one side (right side) adjacent to. In this manner, the impurity 40 can be selectively introduced only into the region E + F where the wiggle-shaped gate pattern is to be formed. As a result, the first mask film 22 corresponding to the wiggle-shaped gate pattern E + F becomes the first mask film 23 doped with the impurity 40. This impurity introduction may be performed by removing the second resist film 32 and performing ion implantation using the second hard mask 24 as a mask.

  Referring to FIG. 12, the second mask film 24 is peeled off, and the portion of the first mask film 22 where impurities are not introduced is selectively removed with, for example, an alkaline etching solution. In this way, a hard mask HM (E + F) having a wiggle shape composed of the first mask film 23 doped with the impurity 40 can be formed.

Thereafter, using the hard mask HM formed in this manner as a mask, anisotropic etching, for example, RIE is performed, and the cap Si ₃ N ₄ film 18, WSi film 16 and polysilicon film 14 are sequentially patterned to form a wiggle shape. Can be formed. Since the structure of the formed gate electrode is the same as that of FIG. 5, the drawing is omitted.

  Further, the semiconductor device using the pattern forming method according to the present embodiment is completed by performing processes such as doping and wiring necessary for the semiconductor device.

  In the present embodiment, the pattern formed by lithography is the simple straight pattern E and the mask pattern 32W having a large opening, so that various margins in lithography can be sufficiently secured.

  Further, according to the present embodiment, ion implantation from an oblique direction is performed using the second mask film 24 instead of the resist film in order to form the projections F of the wiggle pattern. Therefore, as compared with the first and second embodiments, it is possible to suppress the dimensional variation of the wiggle pattern protrusion F caused by the pattern misalignment.

  Therefore, according to the present embodiment, it is possible to provide a pattern forming method for a semiconductor device that forms a wiggle-shaped pattern without using lithography.

(Fourth embodiment)
In the embodiments so far, ion implantation is performed from one oblique direction in order to form the wiggle pattern protrusion. Therefore, there is a concern that the protrusions of the wiggle pattern of the hard mask are not formed with a uniform film thickness because the end face is inclined.

  The fourth embodiment of the present invention is an example of a pattern forming method for a semiconductor device in which a hard mask having a wiggle shape including a protrusion is formed by ion implantation from the vertical direction.

  An example of the pattern forming method of the semiconductor device according to the present embodiment will be explained with reference to FIGS. Each drawing (a) is a plan view, and each drawing (b) is a process cross-sectional view along the cutting line XX shown in (a).

Similar to the second embodiment, the first and second gate electrode materials 14 and 16, the cap insulating film 18, and the mask film 20 are deposited on the semiconductor substrate 10 via the gate insulating film 12. Then, as in the second and third embodiments, an inverted pattern (negative pattern) of the straight gate pattern G is formed on the resist film by lithography. Impurities 40, for example, BF ₂ are ion-implanted into the mask film 20 in the region where the straight gate pattern G opened in the resist film is to be formed. Thereby, the region G of the mask film 20 corresponding to the gate pattern G becomes the mask film 21 made of a-Si doped with the impurity 40.

Next, referring to FIG. 13, the first resist film 30 is removed, and a second resist film 32 is formed on the entire surface. Then, the mask pattern 32H of the protrusion H of the wiggle pattern is opened in the second resist film 32. As in the example shown in FIG. 13, the mask pattern 32 </ b> H is formed such that the right end of the mask pattern 32 </ b> H opens only the protrusion H of the wiggle pattern on the right side of the gate pattern G and the left end remains within the line width of the gate pattern G. To open. Therefore, the mask pattern 32H has an opening larger than the minimum processing dimension of lithography and an opening area wider than the protrusion H of the wiggle. Impurities 40, for example, BF ₂ are ion-implanted from the vertical direction using the second resist film 32 as a mask. In this manner, the impurity 40 can be selectively introduced only into the region G + H where the wiggle-shaped gate pattern is formed. In this way, only the region of the mask film 20 corresponding to the wiggle-shaped gate pattern G + H can be selectively made into the mask film 21 doped with the impurity 40.

  Referring to FIG. 14, the second resist film 32 is peeled off, and the portion of the mask film 20 where the impurities 40 are not introduced is selectively removed with, for example, an alkaline etching solution. In this way, a hard mask HM (G + H) having a wiggle shape can be formed. The hard mask HM has a shape in which the end face is vertical in any part.

Thereafter, using the hard mask HM formed in this manner as a mask, anisotropic etching, for example, RIE is performed, and the cap Si ₃ N ₄ film 18, WSi film 16 and polysilicon film 14 are sequentially patterned to form a wiggle shape. Can be formed. Since the structure of the formed gate electrode is the same as that of FIG. 5, the drawing is omitted.

  Further, the semiconductor device using the pattern forming method according to the present embodiment is completed by performing processes such as doping and wiring necessary for the semiconductor device.

  In the present embodiment, since the pattern formed by lithography is the simple straight pattern G and the mask pattern 32H having a large opening, various margins in lithography can be sufficiently secured. Compared with the first to third embodiments, since the ion implantation for forming the hard mask pattern is performed only from the vertical direction, the end face can be processed vertically. As a result, it is possible to reduce the dimensional variation due to the hard mask retreat during the gate electrode etching.

  Therefore, according to the present embodiment, it is possible to provide a pattern forming method for a semiconductor device that forms a wiggle-shaped pattern without using lithography.

(Fifth embodiment)
The fifth embodiment of the present invention is an example of a pattern formation method for a semiconductor device in which doping for forming a hard mask pattern is performed by a method other than ion implantation, for example, thermal diffusion.

  An example of the pattern forming method of the semiconductor device according to the present embodiment will be explained with reference to FIGS. Each drawing (a) is a plan view, and each drawing (b) is a process cross-sectional view along the cutting line XX shown in (a).

Similar to the third embodiment, the first and second gate electrode materials 14 and 16 and the cap insulating film 18 are deposited on the semiconductor substrate 10 via the gate insulating film 12. Further, a two-layer hard mask film 20 including a first mask film 22 and a second mask film 24 is deposited on the cap insulating film 18. The first mask film 22 is a film that can control the etching selectivity between a doped region and an undoped region by doping impurities, and for example, non-doped a-Si can be used. The second mask film 24 is, for example, a film that serves as a mask when the impurities are doped by thermal diffusion. For example, a SiO ₂ film can be used.

  Referring to FIG. 15, similarly to the third embodiment, a reverse pattern (negative pattern) of the straight gate pattern J is formed on the second mask film 24 using the first resist film 30.

  Next, referring to FIG. 16, the first resist film 30 is peeled off, and a second resist film 32 is formed on the entire surface. Then, similarly to the fourth embodiment, the mask pattern 32K of the protrusion K of the wiggle pattern is opened in the second resist film 32. The opening 32K can be formed in the same manner as in the fourth embodiment, and has an opening area wider than the projection K of the wiggle. Using the second resist film 32 as a mask, anisotropic etching, for example, RIE is performed, and the second mask film 24 is opened by adding the pattern of the protrusion K of the wiggle pattern. In this way, a wiggle-shaped gate pattern J + K is opened in the second mask film 24.

  Next, the second resist film 32 is peeled off. Then, using the second mask film 24 whose opening corresponds to the wiggle-shaped gate pattern J + K as a mask, for example, the first mask film exposed to the opening of the second mask film 24 by performing thermal diffusion, for example. 22 is doped with an impurity 42 such as boron (B). As a thermal diffusion method, for example, a facing method using boron nitride (BN), a coating method in which boron-added glass (BSG: boron silicate glass) is applied to the surface, or the like can be used. In this manner, the first mask film 23 doped with the impurity 40 can be selectively doped by doping impurities only in the region of the first mask film 22 corresponding to the wiggle-shaped gate pattern J + K.

  Thereafter, as in the third embodiment, the second mask film 24 is peeled off, and the portion of the first mask film 22 where impurities are not introduced is selectively removed with, for example, an alkaline etching solution. . In this manner, a hard mask (J + K) made of the first mask film 23 having a wiggle shape can be formed.

Thereafter, anisotropic etching, for example, RIE is performed using the hard mask thus formed as a mask, and the cap Si ₃ N ₄ film 18, WSi film 16, and polysilicon film 14 are sequentially patterned to form a wiggle shape. A gate electrode having the same can be formed. Since the structure of the formed gate electrode is the same as that of FIG. 5, the drawing is omitted.

  Further, the semiconductor device using the pattern forming method according to the present embodiment is completed by performing processes such as doping and wiring necessary for the semiconductor device.

  In the present embodiment, since the pattern formed by lithography is the simple straight pattern J and the mask pattern 32K having a large opening, various margins in lithography can be sufficiently secured.

  In the above embodiment, a negative pattern of a wiggle-shaped gate pattern is formed on the second mask film 24 and used as a mask for impurity diffusion. However, for the second mask film 24, for example, a film serving as a source of impurity diffusion such as the above-described BSG can be used. In this case, a positive pattern of a wiggle-shaped gate pattern can be formed on the second mask film 24 and used directly as a source of impurity diffusion.

  Therefore, according to the present embodiment, it is possible to provide a pattern forming method for a semiconductor device that forms a wiggle-shaped pattern without using lithography.

  In the above embodiment, non-doped a-Si is used as the mask films 20 and 22, and boron (B) is used as the impurity 40 for changing the etching rate. For example, boron-doped a-Si and phosphorus (P) The etching rate can also be changed by a combination. In this case, phosphorus is doped to the same level or higher than the boron concentration. As a result, contrary to the above embodiment, the etching rate of the region doped with phosphorus is faster than the etching rate of the undoped region.

  The present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the spirit and scope of the present invention. Therefore, the present invention is not intended to be limited to the embodiments disclosed herein, and can be applied to other embodiments without departing from the spirit of the present invention and can be applied to a wide range. It is.

1A and 1B are views for explaining an example of a pattern forming method for a semiconductor device according to a first embodiment of the present invention, in which FIG. 1A is a plan view and FIG. 1B is a section line shown in FIG. It is process sectional drawing along XX. 2A and 2B are views for explaining the pattern forming method of the semiconductor device according to the first embodiment following FIG. 1, wherein FIG. 2A is a plan view, and FIG. 2B is a section line X shown in FIG. It is process sectional drawing along -X. 3A and 3B are views for explaining the pattern formation method of the semiconductor device according to the first embodiment following FIG. 2, in which FIG. 3A is a plan view, and FIG. 3B is a section line X shown in FIG. It is process sectional drawing along -X. 4A and 4B are views for explaining the pattern forming method of the semiconductor device according to the first embodiment following FIG. 3, in which FIG. 4A is a plan view, and FIG. 4B is a cutting line X shown in FIG. It is process sectional drawing along -X. FIGS. 5A and 5B are views for explaining the pattern forming method of the semiconductor device according to the first embodiment following FIG. 4, wherein FIG. 5A is a plan view, and FIG. 5B is a cutting line X shown in FIG. It is process sectional drawing along -X. 6A and 6B are views for explaining an example of a pattern forming method for a semiconductor device according to the second embodiment of the present invention, in which FIG. 6A is a plan view, and FIG. 6B is a cutting line shown in FIG. It is process sectional drawing along XX. 7A and 7B are views for explaining the pattern forming method of the semiconductor device according to the second embodiment following FIG. 6, in which FIG. 7A is a plan view, and FIG. 7B is a cutting line X shown in FIG. It is process sectional drawing along -X. FIGS. 8A and 8B are views for explaining the pattern forming method of the semiconductor device according to the second embodiment following FIG. 7, in which FIG. 8A is a plan view, and FIG. 8B is a cutting line X shown in FIG. It is process sectional drawing along -X. FIGS. 9A and 9B are views for explaining an example of a pattern forming method for a semiconductor device according to the third embodiment of the present invention. FIG. 9A is a plan view, and FIG. 9B is a cutting line shown in FIG. It is process sectional drawing along XX. 10A and 10B are views for explaining the pattern formation method of the semiconductor device according to the third embodiment following FIG. 9, where FIG. 10A is a plan view, and FIG. 10B is a cutting line X shown in FIG. It is process sectional drawing along -X. 11A and 11B are views for explaining the pattern forming method of the semiconductor device according to the third embodiment following FIG. 10, in which FIG. 11A is a plan view, and FIG. 11B is a cutting line X shown in FIG. It is process sectional drawing along -X. FIGS. 12A and 12B are views for explaining the pattern forming method of the semiconductor device according to the third embodiment following FIG. 11, wherein FIG. 12A is a plan view, and FIG. 12B is a cutting line X shown in FIG. It is process sectional drawing along -X. 13A and 13B are views for explaining an example of a pattern forming method for a semiconductor device according to the fourth embodiment of the present invention. FIG. 13A is a plan view, and FIG. 13B is a section line shown in FIG. It is process sectional drawing along XX. 14A and 14B are views for explaining the pattern forming method of the semiconductor device according to the fourth embodiment following FIG. 13, wherein FIG. 14A is a plan view, and FIG. 14B is a cutting line X shown in FIG. It is process sectional drawing along -X. FIGS. 15A and 15B are views for explaining an example of a pattern forming method for a semiconductor device according to the fifth embodiment of the present invention. FIG. 15A is a plan view, and FIG. 15B is a section line shown in FIG. It is process sectional drawing along XX. FIGS. 16A and 16B are views for explaining the pattern forming method of the semiconductor device according to the fifth embodiment following FIG. 15, wherein FIG. 16A is a plan view, and FIG. 16B is a section line X shown in FIG. It is process sectional drawing along -X.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 10 ... Semiconductor substrate, 12 ... Gate insulating film, 14 ... 1st and 2nd gate electrode material 14, 16 ... 2nd gate electrode material, 18 ... Cap insulating film, 20 ... Mask film, 21 ... Impurity doped Mask film, 22 ... first mask film, 23 ... first mask film doped with impurities, 24 ... second mask film, 30, 32 ... resist film, 40, 42 ... impurities.

Claims (5)

Depositing a film to be processed above the semiconductor substrate;
Depositing a mask film whose etching characteristics are changed by adding impurities on the film to be processed;
Forming a line pattern on the mask film;
Selectively adding an impurity that changes the etching rate to a desired region of the mask film in which the line pattern is formed;
Selectively etching the line pattern made of the mask film to form a mask pattern including a wiggle shape partially different in line width;
And a step of etching the film to be processed by using the mask pattern as a mask to form a wiggle-shaped pattern. Depositing a film to be processed above the semiconductor substrate;
Depositing a mask film whose etching characteristics are changed by adding impurities on the film to be processed;
Adding an impurity that changes an etching rate to the mask film in a line pattern;
Selectively adding the impurity to a desired region adjacent to the line pattern to which the impurity is added in the mask film;
Selectively etching the mask film to form a mask pattern including a wiggle shape with partially different line widths;
And a step of etching the film to be processed by using the mask pattern as a mask to form a wiggle-shaped pattern.   The step of selectively adding the impurity uses a second mask pattern having an opening larger than the desired region to which the impurity is added, and uses a shadowing of the second mask pattern in one oblique direction. 3. The pattern forming method for a semiconductor device according to claim 1, wherein the impurity is added to the desired region by ion implantation. A second mask film formed on the mask film;
4. The pattern formation method for a semiconductor device according to claim 3, wherein the second mask pattern is formed on the second mask film.   5. The pattern forming method for a semiconductor device according to claim 1, wherein the mask film is a non-doped amorphous silicon film, and the impurity that changes the etching rate is boron. .

Images