CN116487269A - Preparation method of chip heat dissipation structure - Google Patents
Preparation method of chip heat dissipation structure Download PDFInfo
- Publication number
- CN116487269A CN116487269A CN202310549460.9A CN202310549460A CN116487269A CN 116487269 A CN116487269 A CN 116487269A CN 202310549460 A CN202310549460 A CN 202310549460A CN 116487269 A CN116487269 A CN 116487269A
- Authority
- CN
- China
- Prior art keywords
- chip
- boiling
- microstructure
- layer
- cover plate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000002360 preparation method Methods 0.000 title claims abstract description 11
- 230000017525 heat dissipation Effects 0.000 title claims description 48
- 238000009835 boiling Methods 0.000 claims abstract description 112
- 239000007788 liquid Substances 0.000 claims abstract description 37
- 238000000034 method Methods 0.000 claims abstract description 32
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 30
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 30
- 239000010703 silicon Substances 0.000 claims abstract description 30
- 239000003507 refrigerant Substances 0.000 claims abstract description 29
- 239000000758 substrate Substances 0.000 claims abstract description 22
- 235000012431 wafers Nutrition 0.000 claims description 75
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 53
- 229910052751 metal Inorganic materials 0.000 claims description 42
- 239000002184 metal Substances 0.000 claims description 42
- 229910052802 copper Inorganic materials 0.000 claims description 34
- 239000010949 copper Substances 0.000 claims description 34
- 238000007747 plating Methods 0.000 claims description 33
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 32
- 238000003466 welding Methods 0.000 claims description 32
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 29
- 229910052737 gold Inorganic materials 0.000 claims description 29
- 239000010931 gold Substances 0.000 claims description 29
- 238000005520 cutting process Methods 0.000 claims description 26
- 238000005530 etching Methods 0.000 claims description 23
- 239000011248 coating agent Substances 0.000 claims description 22
- 238000000576 coating method Methods 0.000 claims description 22
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 21
- 239000010936 titanium Substances 0.000 claims description 21
- 229910052719 titanium Inorganic materials 0.000 claims description 21
- 238000009713 electroplating Methods 0.000 claims description 17
- 238000001704 evaporation Methods 0.000 claims description 16
- 229910052759 nickel Inorganic materials 0.000 claims description 16
- 238000005245 sintering Methods 0.000 claims description 16
- 238000004519 manufacturing process Methods 0.000 claims description 12
- 230000008020 evaporation Effects 0.000 claims description 11
- 229910052738 indium Inorganic materials 0.000 claims description 8
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 claims description 8
- 238000004140 cleaning Methods 0.000 claims description 7
- 230000001681 protective effect Effects 0.000 claims description 6
- 238000007738 vacuum evaporation Methods 0.000 claims description 5
- 238000011161 development Methods 0.000 claims description 4
- 229920002120 photoresistant polymer Polymers 0.000 claims description 4
- 238000001312 dry etching Methods 0.000 claims description 3
- 229910000679 solder Inorganic materials 0.000 claims description 3
- 238000007740 vapor deposition Methods 0.000 claims description 3
- 238000001816 cooling Methods 0.000 abstract description 31
- 230000000694 effects Effects 0.000 abstract description 18
- 238000009834 vaporization Methods 0.000 abstract description 17
- 230000008016 vaporization Effects 0.000 abstract description 17
- 230000005855 radiation Effects 0.000 abstract description 10
- 238000007654 immersion Methods 0.000 abstract description 2
- 229910000756 V alloy Inorganic materials 0.000 description 12
- 230000004907 flux Effects 0.000 description 12
- HBVFXTAPOLSOPB-UHFFFAOYSA-N nickel vanadium Chemical compound [V].[Ni] HBVFXTAPOLSOPB-UHFFFAOYSA-N 0.000 description 12
- 230000008569 process Effects 0.000 description 12
- 238000004021 metal welding Methods 0.000 description 9
- 239000007789 gas Substances 0.000 description 8
- 239000000565 sealant Substances 0.000 description 7
- 238000005476 soldering Methods 0.000 description 6
- 239000000463 material Substances 0.000 description 5
- 238000012360 testing method Methods 0.000 description 5
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 4
- 239000004593 Epoxy Substances 0.000 description 3
- 239000012298 atmosphere Substances 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 239000012530 fluid Substances 0.000 description 3
- 238000012545 processing Methods 0.000 description 3
- 238000005728 strengthening Methods 0.000 description 3
- 239000000853 adhesive Substances 0.000 description 2
- 230000001070 adhesive effect Effects 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 229910003460 diamond Inorganic materials 0.000 description 2
- 239000010432 diamond Substances 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000001755 magnetron sputter deposition Methods 0.000 description 2
- 229910052757 nitrogen Inorganic materials 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 238000012546 transfer Methods 0.000 description 2
- 230000007704 transition Effects 0.000 description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- 239000000654 additive Substances 0.000 description 1
- 230000000996 additive effect Effects 0.000 description 1
- 230000004075 alteration Effects 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000004364 calculation method Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 229910002804 graphite Inorganic materials 0.000 description 1
- 239000010439 graphite Substances 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 239000011261 inert gas Substances 0.000 description 1
- 238000010329 laser etching Methods 0.000 description 1
- 238000003754 machining Methods 0.000 description 1
- 238000001883 metal evaporation Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000002086 nanomaterial Substances 0.000 description 1
- 239000012299 nitrogen atmosphere Substances 0.000 description 1
- 230000032696 parturition Effects 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4803—Insulating or insulated parts, e.g. mountings, containers, diamond heatsinks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/44—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements the complete device being wholly immersed in a fluid other than air
- H01L23/445—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements the complete device being wholly immersed in a fluid other than air the fluid being a liquefied gas, e.g. in a cryogenic vessel
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
The application discloses preparation method of chip heat radiation structure, heat radiation structure are applicable to the chip in the immersion liquid cooling server, and heat radiation structure sets up in the chip upper surface, and heat radiation structure includes boiling microstructure, and wherein, boiling microstructure is protruding in order to increase the vaporization core quantity of chip upper surface. Through the technical scheme in this application, set up boiling microstructure on the smooth surface of chip silicon substrate to increase the vaporization core quantity of liquid refrigerant boiling in-process, make the liquid refrigerant boiling in-process can produce more bubbles, improve evaporative cooling's radiating effect.
Description
RELATED APPLICATIONS
The application is a divisional application of the invention with the application number of 202010872202.0, namely a surface enhanced boiling heat dissipation structure.
Technical Field
The application relates to the technical field of chips, in particular to a preparation method of a chip heat dissipation structure.
Background
With the increasing requirements on data and graphics processing efficiency, the heat dissipation problems faced by data processing chips such as CPU, GPU and the like are more and more severe, and the heat flux density of the GPU of the super computer at present reaches 80W/cm 2 The conventional air cooling heat dissipation method cannot solve the heat dissipation problem caused by such high heat flux density.
Therefore, liquid cooling heat dissipation is gradually introduced. In liquid cooling heat dissipation, a heat dissipation mode utilizing the liquid boiling vaporization latent heat of a refrigerant is called as evaporative cooling, and the principle is that the vaporization latent heat of fluid in boiling takes away heat, and the vaporization latent heat of the fluid is much larger than the specific heat of the fluid, so that the cooling effect of the evaporative cooling is more remarkable.
In the prior art, the surface of the silicon wafer exposed outside is usually a smooth surface due to the production process of the chip, and at the moment, when the evaporative cooling is adopted, bubbles are not easy to generate due to the smooth surface of the silicon wafer, so that the number of vaporization cores is less when the refrigerant boils, the evaporative cooling heat dissipation effect is poor, and the potential advantages of the evaporative cooling heat dissipation effect cannot be exerted.
Disclosure of Invention
The purpose of the present application is: a preparation method of a chip heat dissipation structure is provided to improve the liquid cooling heat dissipation effect of the chip.
The technical scheme of the first aspect of the application is that: the preparation method of the chip heat dissipation structure is used for preparing the boiling microstructure on the surface of a chip, and comprises the following steps:
step 1, protecting a chip wafer circuit side;
step 2, setting a boiling microstructure on the surface of the chip;
and 3, cutting and mounting the chip wafer.
Further, in step 1, pure silicon wafers of the same size as the chip wafers are bonded on the circuit side, and the bonding sites are edge non-circuit sites of the wafers.
Further, in step 2, the chip is contacted with the liquid refrigerant through the cover plate, and the boiling microstructure is arranged on the cover plate;
the boiling microstructure comprises a copper mesh bonding layer, a copper powder sintering layer or a cutting column;
the copper mesh bonding layer comprises at least one layer of copper mesh bonded on the upper surface of the cover plate, and copper wires in the copper mesh are used as boiling microstructure bulges;
the copper powder sintering layer is formed by sintering copper powder on the upper surface of the cover plate in an environment filled with protective gas.
The cutting posts are engraved on the upper surface of the cover plate.
Further, in step 3, the preparation method further includes:
step 101, evaporating the non-circuit side of the chip wafer, and recording the coating as a first coating;
step 102, cutting the evaporated chip wafer into a plurality of chips according to a preset size, and welding the cut chips on a PCB substrate;
step 104, electroplating a layer of nickel metal on the lower surface of the cover plate in an electroplating mode, and plating gold on the nickel layer generated by electroplating, wherein the nickel layer is recorded as a second plating layer;
and 105, adopting metal indium as solder, and welding the second coating on the lower surface of the cover plate on the first coating on the upper surface of the chip.
Further, in step 3, the first plating layer is disposed on the upper surface of the chip, and the first plating layer includes metallic titanium, where the metallic titanium is attached to the upper surface of the chip by evaporation;
the first coating is formed by adhering one of a blue film or a silicon wafer to the edge of the circuit side of a chip wafer, placing the adhered chip wafer in a vacuum evaporation furnace to perform evaporation on the non-circuit side of the chip wafer, and marking the coating as the first coating;
and the second plating layer is formed by electroplating a layer of nickel metal on the lower surface of the cover plate in an electroplating mode, and the nickel layer formed by electroplating is plated with gold and is recorded as the second plating layer.
Further, in step 2, the boiling microstructure is disposed on the upper surface of the chip, and the preparation method further includes:
step 202, cleaning a bonded chip wafer, coating photoresist, and covering a mask plate on the upper surface of the chip wafer;
step 203, performing exposure and development treatment on the chip wafer covered with the mask plate, and etching the exposed chip wafer to form the boiling microstructure, wherein the boiling microstructure is a silicon bump;
step 204, cleaning the etched chip wafer and exposing the etched chip wafer to ultraviolet light so as to form pits on the boiling microstructure to increase the number of vaporized cores on the surface of the boiling microstructure.
Further, in step 203, the boiling microstructure is a drawn rectangular column.
Further, in step 203, the boiling microstructure is formed for the chip wafer using a dry etching technique.
Further, in step 203, the boiling microstructure has a length ranging from 100um to 5000um, a width ranging from 50um to 2000um, a height ranging from 50um to 2000um, and a pitch of 0 to 1000um; the etching time is 80 to 200min.
Further, in step 204, the pit uses CF 4 The etching temperature is 40 ℃ under the condition of gas and vacuum, and the etching time is 90min, 110min, 130min, 150min, 170min and 190min in sequence.
The beneficial effects of this application are:
according to the technical scheme, the boiling microstructure is arranged on the smooth surface of the chip silicon substrate, so that the number of vaporization cores in the boiling process of the liquid refrigerant is increased, more bubbles can be generated in the boiling process of the liquid refrigerant, the heat dissipation effect of evaporative cooling is improved, and the nucleate boiling heat exchange performance and the critical heat flow density are remarkably improved. Meanwhile, the boiling microstructure is arranged, so that the heat exchange area of the chip can be increased, and the liquid cooling heat dissipation effect of the chip is further improved.
According to the technical scheme, traditional auxiliary heat transfer components such as the radiating fins and the temperature equalization plates are not required to be added, the occupied space size of the radiating components is reduced to the maximum extent, dense arrangement is facilitated, and the calculation speed is improved.
In the preferred implementation mode in the application, on the premise of not changing the existing chip production process, a cover plate is welded on the upper surface (smooth silicon substrate) of the chip in an additive mode, and a boiling microstructure such as a copper mesh bonding layer, a copper powder sintered layer and a cutting column is arranged on the cover plate through processing treatment of the cover plate, so that the quantity of vaporized cores is improved, the boiling performance of the silicon substrate is enhanced, and the problem that the evaporation cooling boiling performance of the polished surface of the chip is poor is effectively solved.
Meanwhile, by arranging the cover plate, the heat exchange area between the chip and the liquid refrigerant is increased, and the heat exchange area of the surface of the chip is increased by 3-20 times.
Through the technical scheme in the application, the heat flux density of the bare chip is improved by one order of magnitude, and the heat flux density is 10W/cm 2 Is increased to 80W/cm 2 The critical heat flow density is improved, the immersed liquid cooling radiating effect is optimized, the heat resistance of the phase-change liquid refrigerant and the chip is reduced to the maximum extent, the superheat degree of the refrigerant phase change is increased, and the heat exchange coefficient is improved.
In the preferred implementation mode in the application, the mask etching is carried out on the upper surface of the chip in a material reduction mode by changing the existing chip production process, the ultraviolet exposure parameters in the mask etching process are adjusted, the silicon bulge is formed on the upper surface of the chip and used as a boiling microstructure, and the improvement of the quantity of vaporization cores in the liquid refrigerant evaporation cooling process is realized, so that the problem that the evaporation cooling boiling performance of the polished surface of the chip is poor is effectively solved.
And through mask etching, the heat exchange area between the upper surface of the chip and the liquid refrigerant can be increased, and the heat dissipation effect of submerged liquid cooling heat dissipation is further improved.
Drawings
The advantages of the foregoing and/or additional aspects of the present application will become apparent and readily appreciated from the description of the embodiments, taken in conjunction with the accompanying drawings, wherein:
FIG. 1 is a schematic block diagram of a surface enhanced boiling heat dissipation structure in accordance with one embodiment of the present application;
FIG. 2 is a partial schematic view of a cutting post cover plate according to one embodiment of the present application;
FIG. 3 is a schematic diagram of a boiling microstructure according to one embodiment of the present application;
fig. 4 is a schematic diagram of a boiling microstructure with pits according to one embodiment of the present application.
Detailed Description
In order that the above-recited objects, features and advantages of the present application will be more clearly understood, a more particular description of the application will be rendered by reference to the appended drawings and appended detailed description. It should be noted that, without conflict, the embodiments of the present application and features of the embodiments may be combined with each other.
In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present application, however, the present application may be practiced otherwise than as described herein, and thus the scope of the present application is not limited to the specific embodiments disclosed below.
Compared with the traditional air cooling heat dissipation mode, the immersed liquid cooling heat dissipation mode has the advantages that the heat dissipation effect is better, particularly, the evaporative cooling heat dissipation mode fully utilizes the heat dissipation capability of liquid refrigerants.
In order to improve the heat dissipation effect of liquid refrigerant evaporation cooling, the upper surface of the chip is provided with a bulge which is used as a boiling heat dissipation structure, so that on one hand, the heat exchange area of the chip can be increased, on the other hand, the number of vaporization cores generating bubbles in the liquid refrigerant evaporation process can be increased, and the nucleate boiling heat exchange performance and critical heat flow density are obviously improved.
Embodiment one:
as shown in fig. 1, the present embodiment provides a surface enhanced boiling heat dissipation structure, which is suitable for a chip 3, wherein the chip 3 is formed by cutting a chip wafer, and the lower surface of the chip 3 is soldered on a PCB substrate 4. Conventionally, the lower surface of the chip 3 is a circuit layer, and the upper surface is a smooth silicon substrate.
In this embodiment, under the condition of fixed chip production process, by arranging the cover plate 1 on the chip 3 and arranging the boiling microstructure on the cover plate 1, the purpose of increasing the number of vaporization cores generating bubbles in the process of evaporating and cooling the liquid refrigerant is achieved, wherein the cover plate 1 is made of at least one of high heat conduction materials such as copper, aluminum, graphite and the like.
The present embodiment will be described with reference to a cover plate 1 made of pure copper.
When liquid refrigerant carries out evaporative cooling to chip 3, because the upper surface of chip 3 is smooth silicon substrate, be unfavorable for liquid refrigerant to produce the bubble when boiling, lead to liquid refrigerant's vaporization latent heat effect relatively poor, in order to increase liquid refrigerant boiling in-process vaporization core number, set up on chip 3 and strengthen boiling heat radiation structure, this heat radiation structure includes: a cover plate 1, a metal welding layer 2; the metal bonding layer 2 is bonded between the upper surface of the chip 3 and the lower surface of the cover plate 1 to connect the chip 3 and the cover plate 1 and transfer heat generated from the chip 3 to the cover plate 1.
In this embodiment, in order to achieve the welding between the chip 3 and the cover plate 1, two metal plating layers are also required to be respectively provided on the upper surface of the chip 3 and the lower surface (welding area) of the cover plate 1, and are respectively denoted as a first plating layer and a second plating layer.
The first coating is arranged on the upper surface of the chip 3, the first coating comprises a metal titanium layer, the metal titanium is attached to the upper surface of the chip 3 in a vapor deposition mode and used as a first layer (metal titanium layer) in the first coating, so that the binding force between the copper cover plate 1 and the silicon substrate of the chip 3 is improved, the metal welding layer 2 is prevented from falling off, and the thickness of titanium is 10-200nm.
In this embodiment, the first plating layer at least includes a metal titanium layer, a nickel-vanadium alloy layer, and a metal gold layer.
The second layer in the first coating is a nickel-vanadium alloy layer which is used as a transition layer, and the nickel-vanadium alloy is attached to the metal titanium layer so as to improve the binding force between the metal gold layer and the metal titanium layer, wherein the thickness of the nickel-vanadium alloy is 100-1000nm.
The third layer in the first plating layer is a metal gold layer, the metal gold layer is used as a welding layer with the cover plate 1, and oxidation of the first plating layer is avoided by utilizing inertia of gold.
Likewise, the lower surface of the cover plate 1 is electroplated with a second plating layer, and the second plating layer sequentially comprises a metal nickel layer and a metal gold layer, wherein the metal gold layer is electroplated on the metal nickel layer of the welding area of the lower surface of the cover plate 1 in a magnetron sputtering mode.
In the present embodiment, the material of the metal welding layer is not limited.
In order to weld the metal gold layers in the first and second plating layers together, metal indium is selected as a welding material of the metal welding layer, and the metal welding layer is used as an interface heat conduction layer to realize connection and heat conduction between the chip 3 and the cover plate 1, namely, heat generated by the chip 3 is transferred to the cover plate 1.
The gold layer of the chip 3 and the gold layer of the cover plate 1 are alloyed with metallic indium by soldering, and the thickness thereof is 100-500nm.
In this embodiment, the welding conditions of the chip 3 and the cover plate 1 are set as follows: the soldering temperature was 160℃and the soldering time was 4 hours, the pressure between the lid plate 1 and the chip 3 was 70LBF.
The lower surface of the cover plate 1 is fixed on the metal welding layer 2, the upper surface of the cover plate 1 is provided with a bulge which is marked as a boiling microstructure, wherein the cover plate 1 is groove-shaped, and the edge of the cover plate 1 is adhered to the PCB substrate 4 of the chip 3 through the sealant 5.
In this embodiment, the cover plate 1 is configured in a groove shape, and the surface area of the lower surface of the cover plate 1 is slightly larger than the surface area of the silicon substrate on the upper surface of the chip 3, so that on one hand, the heat dissipation area of the cover plate 1 can be increased, and on the other hand, the phenomenon that the cover plate 1 is connected with the chip 3 to trigger short circuit can be avoided. The edge of the groove of the cover plate 1 is adhered to the PCB substrate 4 of the chip 3 through the sealant 5, and meanwhile, the sealant 5 can also play a role in increasing structural strength.
In this embodiment, the boiling microstructure on the upper surface of the cover plate 1 may be one or more of the following ways.
In one implementation of the boiling microstructure, the boiling microstructure comprises a copper mesh bonding layer comprising at least one layer of copper mesh bonded to the upper surface of the cover plate 1, wherein copper wires in the copper mesh are raised as the boiling microstructure.
Specifically, copper nets with different mesh numbers and different layers can be adhered to the upper surface of the cover plate 1 to be used as a boiling strengthening structure. The number of layers of the copper net is preferably 3-5, the mesh number of the copper net is preferably 50-200, and the bonding copper net is pressure diffusion welding.
In another implementation of the boiling microstructure, the boiling microstructure comprises a copper powder sintered layer formed by sintering copper powder on the upper surface of the cover plate in an environment filled with a protective gas, wherein the copper powder bulges as the boiling microstructure.
Specifically, copper powder with different mesh numbers and different thicknesses can be sintered on the upper surface of the cover plate 1 to be used as a boiling strengthening structure. When sintering copper powder, the cover plate 1 is placed in an environment filled with protective gas for high-temperature sintering, the sintering temperature is 900-1100 ℃, the mesh number of the copper powder is preferably 100-300 meshes, wherein the protective gas is mainly inert gas such as nitrogen.
In this embodiment, the above process will be described using a 12-inch GPU chip wafer as an example.
Firstly, the circuit side of a 12-inch GPU chip wafer is protected, the specific protection layer is 12-inch silicon wafer bonding protection, and the edge of the circuit side of the GPU chip wafer is bonded with the edge of a pure silicon wafer by adopting epoxy sealant.
And then, putting the GPU chip wafer into a vacuum evaporation furnace, exposing the electroplating side of the GPU chip wafer to an evaporation atmosphere, and sequentially evaporating titanium, nickel-vanadium alloy and gold, wherein the thickness of the titanium layer is 100nm, the thickness of the nickel-vanadium alloy is 1000nm, and the thickness of the gold layer is 200nm.
Secondly, cutting the evaporated GPU chip wafer into single chips 3, welding the single chips 3 on corresponding PCB substrates 4 of the chips 3, and setting the welding temperature to 250 ℃ and the welding time to 30min.
In this embodiment, the cover plate 1 is made of pure copper, an adhesive is coated on the upper surface of the copper cover plate, copper powder with 200 meshes is coated on the upper surface of the cover plate 1, the copper powder thickness is 1000um, the cover plate 1 is placed in a sintering furnace, nitrogen is used as a protective gas, the cover plate 1 is sintered in a nitrogen atmosphere, the sintering temperature is set at 1020 ℃, the sintering time is set for 30min, the cover plate 1 is cleaned after the sintering is completed, and the sintered copper powder can be used as a reinforced boiling structure on the cover plate 1.
Finally, the cover plate 1 and the chip 3 are welded, metal indium is adopted as welding flux during welding, the welding temperature is set to 160 ℃, and the time is 4 hours, and the pressure of the cover plate 1 and the chip 3 is 70LBF.
In yet another implementation of the boiling microstructure, as shown in fig. 2, the boiling microstructure comprises a plurality of cutting pillars engraved on the upper surface of the cover plate, wherein an array of cutting pillars is distributed on the upper surface of the cover plate. At this point, the cut pillars act as boiling microstructure protrusions.
Specifically, the engraving mode adopts a machining, linear cutting process or laser mode, and a plurality of cutting columns distributed in an array are engraved above the cover plate 1 according to a preset size.
Firstly, the circuit side of a 12-inch GPU chip wafer is protected, the specific protection layer is 12-inch silicon wafer bonding protection, and the edge of the circuit side of the GPU chip wafer is bonded with the edge of a pure silicon wafer by epoxy sealing.
And then, putting the GPU chip wafer into a vacuum evaporation furnace, exposing the electroplating side of the GPU chip wafer to an evaporation atmosphere, and sequentially evaporating titanium, nickel-vanadium alloy and gold, wherein the thickness of the titanium layer is 100nm, the thickness of the nickel-vanadium alloy is 1000nm, and the thickness of the gold layer is 200nm.
Secondly, cutting the evaporated GPU chip wafer into single chips 3, welding the single chips 3 on corresponding PCB substrates 4 of the chips 3, and setting the welding temperature to 250 ℃ and the welding time to 30min.
In this embodiment, the cover plate 1 is made of pure copper, and a laser etching process is performed on the upper surface of the pure copper cover plate to etch the reinforced boiling cutting column with the length of 100um, the width of 100um and the height of 500 um.
It should be noted that, the boiling-strengthening cutting column can also be made on the pure copper cover plate 1, at this time, the copper cover plate 1 is shoveled in technology to form fins with thickness of 100um and height of 500um, and the fin interval is 100um. And then, carrying out a linear cutting process on the fins to form reinforced boiling cutting columns with the length of 100um, the width of 100um and the height of 500 um.
Finally, the cover plate 1 and the chip 3 are welded, metal indium is adopted as welding flux during welding, the welding temperature is set to 160 ℃, and the time is 4 hours, and the pressure of the cover plate 1 and the chip 3 is 70LBF.
The size of the cutting column in this embodiment is not limited.
In this embodiment, a cover plate made of pure copper is selected, the implementation manners of the three boiling microstructures are tested, and under the condition that the highest surface temperature is 85 ℃ and the refrigerant adopts non-conductive liquid with the boiling point of 47 ℃ in the running process of the chip, a comparison test is performed with a bare chip, and test data are shown in table 1.
TABLE 1
Compared with a bare chip, the chip provided with the surface enhanced boiling heat dissipation structure has the advantages that the heat flux density is improved by a plurality of times, the boiling heat dissipation structure has a good heat dissipation effect, the effective heat dissipation surface area is improved through the material increase treatment, the micro-nano structure treatment is performed, and the vaporization core number in the evaporation cooling process is improved.
Embodiment two:
the present embodiment provides a method for mounting a heat dissipation structure of a chip, which is suitable for mounting the surface enhanced boiling heat dissipation structure in the above embodiment on a chip, and the heat dissipation structure includes: the metal welding device comprises a cover plate 1, a metal welding layer 2 and a chip 3, wherein a boiling microstructure is arranged on the cover plate 1.
In this embodiment, a cover plate 1 made of pure copper is described as an example.
The method comprises the following steps:
step 101, bonding one of a blue film or a silicon wafer to the edge of the circuit side of a chip wafer, placing the bonded chip wafer in a vacuum evaporation furnace to perform metal evaporation on the non-circuit side of the chip wafer, and marking a plating layer as a first plating layer;
in this embodiment, the first plating layer at least includes a metal titanium layer, a nickel-vanadium alloy layer, and a metal gold layer.
The first layer in the first plating layer is a metal titanium layer, and the metal titanium layer is attached to the upper surface of the chip 3 in a vapor deposition mode, so that the binding force between the copper cover plate 1 and the silicon substrate of the chip 3 is improved, and the metal welding layer 2 is prevented from falling off, wherein the thickness of titanium is 10-200nm.
The second layer in the first coating is a nickel-vanadium alloy layer which is used as a transition layer, and the nickel-vanadium alloy is attached to the metal titanium layer so as to improve the binding force between the metal gold layer and the metal titanium layer, wherein the thickness of the nickel-vanadium alloy is 100-1000nm.
The third layer in the first plating layer is a metal gold layer, the metal gold layer is used as a welding layer with the cover plate 1, and oxidation of the first plating layer is avoided by utilizing inertia of gold.
And 102, cutting the evaporated chip wafer into a plurality of chips according to a preset size, and welding the cut chips on a PCB substrate.
And 103, setting a boiling microstructure on the upper surface of the cover plate, wherein the boiling microstructure is one of a copper mesh bonding layer, a copper powder sintering layer and a cutting column.
In one implementation of the boiling microstructure, the boiling microstructure comprises a copper mesh bonding layer comprising at least one layer of copper mesh bonded to the upper surface of the cover plate 1.
In another implementation of the boiling microstructure, the boiling microstructure includes a copper powder sintered layer formed by sintering copper powder on an upper surface of the cover plate in an atmosphere filled with a shielding gas.
In yet another implementation of the boiling microstructure, the boiling microstructure comprises cutting pillars engraved on the upper surface of the cover plate.
The present embodiment is not limited to the form of the boiling microstructure. The boiling microstructure is arranged on the upper surface of the cover plate so as to increase the vaporization core number in the boiling process of the liquid refrigerant and optimize the evaporative cooling effect of the liquid refrigerant.
Step 104, electroplating a layer of nickel metal on the lower surface of the cover plate in an electroplating manner, arranging a welding area on the nickel layer formed by electroplating, plating gold on the welding area, and recording the gold-plated welding area as a second plating layer, namely the second plating layer sequentially comprises a metal nickel layer and a metal gold layer, wherein the metal gold layer is electroplated on the metal nickel layer of the welding area on the lower surface of the cover plate 1 in a magnetron sputtering manner.
Step 105, adopting metal indium as solder, welding the second plating layer on the lower surface of the cover plate to the first plating layer on the upper surface of the chip, namely welding the metal gold layers in the first and second plating layers together, and simultaneously realizing heat conduction between the chip 3 and the cover plate 1, wherein the welding conditions are set as follows: the soldering temperature was 160℃and the soldering time was 4 hours, and the pressure of the lid plate 1 and the chip 3 was 70LBF.
The gold layer of the chip 3 and the gold layer of the cover plate 1 are alloyed with metallic indium by soldering, and the thickness thereof is 100-500nm.
And 106, bonding the edge of the cover plate on the PCB substrate by using epoxy sealant at the edge of the cover plate.
In this embodiment, set up the apron as the recess shape, and the surface area of the lower surface of apron slightly is greater than the surface area of chip upper surface silicon substrate, on the one hand can increase the radiating area of apron, on the other hand can also avoid apron and chip to meet and trigger the phenomenon of giving birth to the short circuit, and then bond the edge of apron on the PCB base plate of chip through the sealant, simultaneously, the sealant can also be given the effect that increases structural strength.
Embodiment III:
as shown in fig. 3 and 4, the present embodiment provides another surface enhanced boiling heat dissipation structure, which is suitable for chips, wherein the lower surface of the chip is set to be a circuit layer, and the upper surface of the chip is set to be a smooth silicon substrate.
In this embodiment, the mask etching method is not limited.
In this embodiment, the boiling microstructure may be rectangular, diamond, cylindrical, conical, rectangular, or diamond.
In this embodiment, the length range L (L 1 ) =100 to 5000um, width range K (K 1 ) The height range h=50um to 2000um, the pitch D of the structures=0 to 1000um.
In this embodiment, the shape and size of the boiling microstructure are determined by the pattern shape of the mask and the etching time, wherein the etching time is 80-200min.
In this embodiment, the boiling microstructure is etched on the upper surface of the chip by ultraviolet exposure and is further provided with pits etched on the surface of the boiling microstructure by ultraviolet exposure.
Embodiment four:
the embodiment provides another method for manufacturing the chip heat dissipation structure, which is suitable for manufacturing the surface enhanced boiling heat dissipation structure in the embodiment above on a chip.
Taking a GPU chip as an example, setting the shape of a boiling microstructure as a pattern drawing rectangular column, etching the boiling microstructure on the upper surface of the chip in a mask etching mode, and arranging pits on the surface of the boiling microstructure, wherein the method comprises the following steps:
step 201, cleaning the chip wafer, and covering and bonding the silicon wafer on the circuit layer of the chip wafer.
Specifically, the 12-inch GPU chip wafer with the circuit is cleaned, surface impurities on two sides of the chip are removed, pure silicon wafers with the same size are covered on the circuit side, the GPU chip wafer and the pure silicon wafers are bonded by adopting an adhesive, and the bonding part is the edge non-circuit part of the wafer.
Step 202, cleaning the bonded chip wafer, coating photoresist, enabling the photoresist to rotate, leveling and solidifying, and covering the manufactured mask plate on the upper surface of the chip wafer.
And 203, performing exposure and development treatment on the chip wafer covered with the mask plate, wherein ultraviolet light exposure is adopted during the exposure and development treatment, and a dry etching technology is adopted to etch the exposed chip wafer so as to form a boiling microstructure, and the specific etching time, temperature and pressure are determined by the size of the rectangular drawing column.
Step 204, cleaning the etched chip wafer, and exposing the upper surface of the whole wafer to ultraviolet light again, and exposing the whole wafer to ultraviolet light in a short time so as to form etching pits on the boiling microstructure, thereby further increasing the number of vaporization cores.
And 205, cutting the chip wafer subjected to ultraviolet light exposure according to a preset size, removing the edge of the non-circuit to prepare a chip, wherein the upper surface of the chip is provided with a smooth silicon substrate, and the chip becomes an enhanced boiling heat dissipation structure with a boiling microstructure.
In order to test the heat dissipation performance of the chip with the boiling microstructure enhanced boiling heat dissipation structure in this embodiment, the GPU chip size was 14.5×23×1mm, and the refrigerant was a nonconductive liquid with a boiling point of 47 ℃.
The etching conditions are set in the process of etching the boiling microstructure and the surface pits: by CF 4 The etching temperature is 40 ℃ under the condition of gas and vacuum, and the etching time is 90min, 110min, 130min, 150min, 170min and 190min in sequence.
The boiling microstructure surface temperature was set to 85 ℃ and a comparison test was performed with bare chips at the same temperature, and the test data are shown in table 2.
TABLE 2
Compared with a bare chip, the heat flux density of the chip with the rectangular column boiling microstructure is greatly improved, and particularly, the heat flux density of the chip reaches 82W/cm under the condition that the etching time is set to 150min 2 The heat flux density of the bare chip is about 6.3 times, and the immersed liquid cooling heat dissipation effect of the GPU chip is remarkably improved.
In the technical scheme of the embodiment, the heat flux density of the bare chip is increased by one order of magnitude, and the heat flux density is 10W/cm 2 Is increased to 80W/cm 2 Critical heat flow density is improved, and immersion liquid cooling heat dissipation effect is optimizedAs a result, the heat resistance of the phase-change liquid refrigerant and the chip is reduced to the maximum extent, the superheat degree of the refrigerant phase change is increased, and the heat exchange coefficient is improved.
The technical scheme of this application has been explained in detail in the above-mentioned combination drawing, this application provides a surface enhanced boiling heat radiation structure, and heat radiation structure is applicable to the chip in the submergence formula liquid cooling server, and heat radiation structure sets up in the chip upper surface, and heat radiation structure includes boiling microstructure, and wherein, boiling microstructure is protruding in order to increase the vaporization core quantity of chip upper surface. Through the technical scheme in this application, set up boiling microstructure on the smooth surface of chip silicon substrate to increase the vaporization core quantity of liquid refrigerant boiling in-process, make the liquid refrigerant boiling in-process can produce more bubbles, improve evaporative cooling's radiating effect.
The steps in the present application may be sequentially adjusted, combined, and pruned according to actual requirements.
The units in the device can be combined, divided and pruned according to actual requirements.
Although the present application is disclosed in detail with reference to the accompanying drawings, it is to be understood that such descriptions are merely illustrative and are not intended to limit the application of the present application. The scope of the present application is defined by the appended claims and may include various modifications, alterations, and equivalents to the invention without departing from the scope and spirit of the application.
Claims (10)
1. The preparation method of the chip heat dissipation structure is characterized in that the preparation method of the chip heat dissipation structure is used for preparing a boiling microstructure on the surface of a chip, and the preparation method of the chip heat dissipation structure comprises the following steps:
step 1, protecting a chip wafer circuit side;
step 2, setting a boiling microstructure on the surface of the chip;
and 3, cutting and mounting the chip wafer.
2. The method of manufacturing a heat dissipating structure for a chip as defined in claim 1, wherein in step 1, pure silicon wafers having the same size as the chip wafers are bonded on the circuit side, and the bonding sites are non-circuit sites on the edges of the wafers.
3. The method for manufacturing a heat dissipating structure for a chip according to claim 1, wherein in step 2, the chip is contacted with a liquid refrigerant through a cover plate, and the boiling microstructure is disposed on the cover plate;
the boiling microstructure comprises a copper mesh bonding layer, a copper powder sintering layer or a cutting column;
the copper mesh bonding layer comprises at least one layer of copper mesh bonded on the upper surface of the cover plate, and copper wires in the copper mesh are used as boiling microstructure bulges;
the copper powder sintering layer is formed by sintering copper powder on the upper surface of the cover plate in an environment filled with protective gas;
the cutting posts are engraved on the upper surface of the cover plate.
4. The method for manufacturing a heat dissipation structure for a chip as recited in claim 3, wherein in step 3, the method further comprises:
step 101, evaporating the non-circuit side of the chip wafer, and recording the coating as a first coating;
step 102, cutting the evaporated chip wafer into a plurality of chips according to a preset size, and welding the cut chips on a PCB substrate;
step 104, electroplating a layer of nickel metal on the lower surface of the cover plate in an electroplating mode, and plating gold on the nickel layer generated by electroplating, wherein the nickel layer is recorded as a second plating layer;
and 105, adopting metal indium as solder, and welding the second coating on the lower surface of the cover plate on the first coating on the upper surface of the chip.
5. The method for manufacturing a heat dissipating structure for a chip according to claim 4, wherein in step 3, the first plating layer is disposed on the upper surface of the chip, and the first plating layer includes metallic titanium, and the metallic titanium is attached to the upper surface of the chip by vapor deposition;
the first coating is formed by adhering one of a blue film or a silicon wafer to the edge of the circuit side of a chip wafer, placing the adhered chip wafer in a vacuum evaporation furnace to perform evaporation on the non-circuit side of the chip wafer, and marking the coating as the first coating;
and the second plating layer is formed by electroplating a layer of nickel metal on the lower surface of the cover plate in an electroplating mode, and the nickel layer formed by electroplating is plated with gold and is recorded as the second plating layer.
6. The method of manufacturing a heat dissipating structure for a chip according to claim 2, wherein in step 2, the boiling microstructure is disposed on an upper surface of the chip, the method further comprising:
step 202, cleaning a bonded chip wafer, coating photoresist, and covering a mask plate on the upper surface of the chip wafer;
step 203, performing exposure and development treatment on the chip wafer covered with the mask plate, and etching the exposed chip wafer to form the boiling microstructure, wherein the boiling microstructure is a silicon bump;
step 204, cleaning the etched chip wafer and exposing the etched chip wafer to ultraviolet light so as to form pits on the boiling microstructure to increase the number of vaporized cores on the surface of the boiling microstructure.
7. The method of claim 6, wherein in step 203, the boiling microstructure is a drawn rectangular column.
8. The method of claim 6, wherein in step 203, the boiling microstructure is formed by dry etching for the chip wafer.
9. The method of manufacturing a heat spreader structure according to claim 6, wherein in step 203, the boiling microstructure has a length ranging from 100um to 5000um, a width ranging from 50um to 2000um, a height ranging from 50um to 2000um, and a pitch of the structure ranging from 0um to 1000um; the etching time is 80 to 200min.
10. The method of claim 6, wherein in step 204, the pit uses CF 4 The etching temperature is 40 ℃ under the condition of gas and vacuum, and the etching time is 90min, 110min, 130min, 150min, 170min and 190min in sequence.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310549460.9A CN116487269A (en) | 2020-08-26 | 2020-08-26 | Preparation method of chip heat dissipation structure |
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010872202.0A CN112151481B (en) | 2020-08-26 | 2020-08-26 | Surface enhanced boiling heat radiation structure |
| CN202310549460.9A CN116487269A (en) | 2020-08-26 | 2020-08-26 | Preparation method of chip heat dissipation structure |
Related Parent Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202010872202.0A Division CN112151481B (en) | 2020-08-26 | 2020-08-26 | Surface enhanced boiling heat radiation structure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN116487269A true CN116487269A (en) | 2023-07-25 |
Family
ID=73888275
Family Applications (2)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202310549460.9A Pending CN116487269A (en) | 2020-08-26 | 2020-08-26 | Preparation method of chip heat dissipation structure |
| CN202010872202.0A Active CN112151481B (en) | 2020-08-26 | 2020-08-26 | Surface enhanced boiling heat radiation structure |
Family Applications After (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202010872202.0A Active CN112151481B (en) | 2020-08-26 | 2020-08-26 | Surface enhanced boiling heat radiation structure |
Country Status (1)
| Country | Link |
|---|---|
| CN (2) | CN116487269A (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113357953B (en) * | 2021-04-28 | 2022-05-20 | 西安交通大学 | Immersion type liquid cooling sintering porous capillary core coupling micro-channel heat dissipation device |
| CN113973460B (en) * | 2021-11-05 | 2023-10-20 | 天津航空机电有限公司 | Regenerative cooling thermal protection case |
| CN114131018A (en) * | 2021-12-10 | 2022-03-04 | 中国矿业大学 | Preparation method of heat dissipation material of net pressing copper nano packed bed |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102709425A (en) * | 2012-05-30 | 2012-10-03 | 华南理工大学 | LED (Light-Emitting Diode) chip with pyramid array structure and manufacturing method thereof |
| CN106637194A (en) * | 2016-12-08 | 2017-05-10 | 曙光节能技术（北京）股份有限公司 | Surface treatment method for CPU cover |
| CN107168493A (en) * | 2017-06-01 | 2017-09-15 | 曙光节能技术（北京）股份有限公司 | A kind of CPU heat dissipating methods and device |
| CN207517667U (en) * | 2017-11-08 | 2018-06-19 | 中电普瑞电力工程有限公司 | A kind of micro-nano structure array heat-delivery surface |
| CN108321135B (en) * | 2018-01-24 | 2019-08-23 | 西安交通大学 | A kind of columnar chip enhanced boiling heat transfer micro-structure of combined type and its manufacturing method |
-
2020
- 2020-08-26 CN CN202310549460.9A patent/CN116487269A/en active Pending
- 2020-08-26 CN CN202010872202.0A patent/CN112151481B/en active Active
Also Published As
| Publication number | Publication date |
|---|---|
| CN112151481B (en) | 2023-07-18 |
| CN112151481A (en) | 2020-12-29 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN112151481B (en) | Surface enhanced boiling heat radiation structure | |
| US6803324B2 (en) | Semiconductor device and its manufacturing method | |
| JP2500086B2 (en) | Method of applying solder to metal land | |
| US6872594B2 (en) | Method of fabricating an electronic component | |
| EP0797247B1 (en) | Substrate on which bumps are formed and method of forming the same | |
| US6664128B2 (en) | Bump fabrication process | |
| EP1998370A2 (en) | Electronic assembly comprising solderable thermal interface and methods of manufacture | |
| CN1759477A (en) | The manufacture method of electronic components packaging substrate | |
| JP2008091471A (en) | Substrate with built-in semiconductor, and its manufacturing method | |
| JP2007214534A (en) | Manufacturing method of circuit board having conductive structure | |
| KR20210120810A (en) | Ic die and heat spreaders with solderable thermal interface structures for assemblies including solder array thermal interconnects | |
| US11322456B2 (en) | Die back side structures for warpage control | |
| TW201417196A (en) | Package substrate, package structure and methods for manufacturing same | |
| WO2022127748A1 (en) | Ultra-thin soldering gasket and preparation method therefor, soldering method, and semiconductor device | |
| TWI242866B (en) | Process of forming lead-free bumps on electronic component | |
| CN213212154U (en) | Processor with surface-enhanced boiling heat dissipation structure | |
| JP2002016178A (en) | Semiconductor device and manufacturing method therefor | |
| KR100744149B1 (en) | Semiconductor package having silver bump and method for fabricating the same | |
| JP2022145713A (en) | Metal member for manufacturing vapor chamber | |
| WO1997001866A1 (en) | Ball grid array package utilizing solder coated spheres | |
| JP3124224B2 (en) | Solder bump formation method | |
| JP2012146781A (en) | Mounting structure, interposer, and method of manufacturing those, and electronic device | |
| JP2002016198A (en) | Semiconductor device | |
| CN104103527A (en) | Improved fanout panel level semiconductor chip package process | |
| TWI829484B (en) | Package carrier board integrated with magnetic element structure and manufacturing method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |