CN116483189A

CN116483189A - Circuit system

Info

Publication number: CN116483189A
Application number: CN202210044497.1A
Authority: CN
Inventors: 林品宏
Original assignee: Realtek Semiconductor Corp
Current assignee: Realtek Semiconductor Corp
Priority date: 2022-01-14
Filing date: 2022-01-14
Publication date: 2023-07-25

Abstract

The invention discloses a circuit system which comprises a multimode switching multiplexer, a control circuit and a receiver. The multimode switching multiplexer is used for receiving a plurality of mode settings from firmware and selecting one of the mode settings as an output mode setting; the control circuit is used for generating a mode switching signal to control the multimode switching multiplexer, and the receiver is used for setting the internal elements according to the output mode setting.

Description

Circuit system

Technical Field

The invention relates to a circuit system capable of switching modes rapidly.

Background

In a related specification of a display interface (DP), an advanced link power management (Advanced Link Power Management, ALPM) is proposed that requires a display device to be able to quickly leave a sleep mode to enter a subsequent mode. Since the above modes involve control of hardware components and different modes require different settings for component control, it is generally determined that the control signals corresponding to the different modes are transmitted to the receiver by the firmware to control the components therein after the decision to switch to the different modes. However, the above-mentioned processing by firmware is time-consuming, and thus affects the speed of mode switching.

Disclosure of Invention

It is therefore an objective of the claimed invention to provide a circuit system that can perform fast mode switching to solve the above-mentioned problems in the prior art.

In one embodiment of the invention, a circuit system is disclosed that includes a multimode switching multiplexer, a control circuit, and a receiver. The multimode switching multiplexer is used for receiving a plurality of mode settings from firmware and selecting one of the mode settings as an output mode setting; the control circuit is used for generating a mode switching signal to control the multimode switching multiplexer, and the receiver is used for setting the internal elements according to the output mode setting.

Drawings

Fig. 1 is a schematic diagram of circuitry according to an embodiment of the invention.

FIG. 2 is a timing diagram of a multimode switching multiplexer according to an embodiment of the invention.

Fig. 3 is a schematic diagram of the operation of the components within the receiver when the circuitry is operating in sleep mode.

Fig. 4 is a schematic diagram of the operation of the components within the receiver when the circuitry is operating in the wake-up mode.

Fig. 5 is a schematic diagram of the operation of the components within the receiver when the circuitry is operating in a receive mode.

Detailed Description

Fig. 1 is a schematic diagram of a circuit system 100 according to an embodiment of the invention. As shown in fig. 1, the circuitry 100 includes a receiver 110, a detection circuit 120, a control circuit 130, a multimode switching multiplexer 140, a microprocessor 150, and a memory element 160, wherein the memory element 160 includes program code 162. In this embodiment, the circuit system 100 is disposed at a receiving end of the display, and the circuit system 100 supports a display interface (DP) standard, and the circuit system 100 can be used to receive a DP signal and perform subsequent processing.

Circuitry 100 may operate in a number of different modes and in different modes, receiver 110 may have different settings. In this embodiment, the circuit system 100 can operate in three different modes, and the receiver 110 uses the mode setting S1 to set the internal components when the circuit system 100 operates in the first mode, uses the mode setting S2 to set the internal components when the circuit system 100 operates in the second mode, and uses the mode setting S3 to set the internal components when the circuit system 100 operates in the third mode, wherein each of the mode settings S1, S2, S3 includes a plurality of different control bits/signals. In order to enable the receiver 110 to quickly obtain the required mode setting S1/S2/S3 for setting the internal components during the mode switching, the microprocessor 150 of the present embodiment generates three mode settings S1, S2, S3 to the multimode switching multiplexer 140 after executing the program code 162 (i.e. firmware or called software), and the three mode settings S1, S2, S3 are written to the input of the multimode switching multiplexer 140, and when the circuit system 100 needs to perform the mode switching, the control circuit 130 generates the mode switching signals Vc1, vc2 to the multimode switching multiplexer 140 so that the multimode switching multiplexer 140 directly uses one of the mode settings S1, S2, S3 as the output mode setting SC for the receiver 110.

In the present embodiment, since the firmware directly writes the three mode settings S1, S2, S3 to the input terminal of the multimode switching multiplexer 140, and the three mode settings S1, S2, S3 are continuously present at the input terminal of the multimode switching multiplexer 140 during the operation of the circuit system 100, when the circuit system 100 needs to switch to different modes (for example, from the first mode to the second mode), the control circuit 130 can generate the mode switching signals Vc1, vc2 to directly control the multimode switching multiplexer 140 to output different mode settings, without the microprocessor 150 outputting different mode settings according to the mode switching. As described above, the operation of outputting different mode settings S1/S2/S3 in the mode switching of the present embodiment can be completed only by a hardware circuit without intervention of firmware, so that the purpose of rapidly switching modes can be achieved.

In the embodiment, the circuit system 100 is disposed on the display, and when the display is turned on and the circuit system 100 is powered on, the microprocessor 150 writes the mode settings S1, S2, S3 to the input terminal of the multimode switching multiplexer 140, even though the circuit system 100 does not need to operate in the first mode, the second mode and the third mode, so that the microprocessor 150 does not need to spend time writing the mode settings S1, S2, S3 to the multimode switching multiplexer 140 in the subsequent operation of the circuit system 100.

Fig. 2 is a timing diagram of the multimode switching multiplexer 140 according to an embodiment of the invention. As shown in fig. 2, the multimode switching multiplexer 140 includes multiplexers 210, 220, wherein the multiplexer 210 receives the mode settings S1, S2 and selects one of the mode settings S1, S2 for output according to the mode switching signal Vc 1; the multiplexer 220 receives the mode setting S3 and the output of the multiplexer 210, and selects one of the mode setting S3 and the output of the multiplexer 210 to output according to the mode switching signal Vc 2. For example, when the mode switching signals Vc1, vc2 are both at a low voltage level, the mode switching multiplexer 140 selects the mode setting S1 as the output mode setting SC; when the mode switching signals Vc1, vc2 are the high voltage level and the low voltage level, respectively, the mode switching multiplexer 140 selects the mode setting S2 as the output mode setting SC; and when the mode switching signal Vc2 is at a high voltage level, the multimode switching multiplexer 140 selects the mode setting S3 as the output mode setting SC. It should be noted that the mode switching signals Vc1, vc2 and the corresponding mode settings are merely exemplary and are not limiting.

In an embodiment, the first mode, the second mode and the third mode of the circuit system 100 are a sleep mode, an awake mode and a receive mode, respectively, and the mode settings S1, S2 and S3 shown in fig. 1 and fig. 2 correspond to the sleep mode, the awake mode and the receive mode, respectively. Specifically, when the circuit system 100 enters the sleep mode, the transmitting end outside the system circuit 100 transmits the data with the sleep information to the receiver 110, and the receiver 110 transmits the received data to the control circuit 130 for interpretation, and if the control circuit 130 determines that the received data indicates to enter the sleep mode, the control circuit 130 outputs the mode switching signals Vc1 and Vc2 to the multimode switching multiplexer 140 to select the mode setting S1 as the output mode setting SC for setting the receiver 110.

Fig. 3 is a schematic diagram of the operation of the components within the receiver 110 when the circuitry 100 is operating in sleep mode. As shown in fig. 3, the receiver 110 includes a switch SW1, an equalizer (equalizer) 310, an analog-to-digital converter 320, a processing circuit 330, a clock generating circuit 340, and a bias generating circuit 350. Under the control of the mode setting S1, the equalizer 310, the adc 320, the processing circuit 330 and the clock generation circuit 340 stop operating, and since the bias generation circuit 350 takes a long time to generate a stable bias after powering up or waking up, the bias generation circuit 350 still generates a bias to the equalizer 310, the adc 320 and the clock generation circuit 340 in the sleep mode.

In addition, the detection circuit 120, the control circuit 130 and the multimode switching multiplexer 140 of fig. 1 still operate normally when the circuit system 100 is operated in the sleep mode, so as to ensure that the subsequent wake-up signal can be received and the mode can be switched.

Then, when the circuit system 100 needs to be woken up, the transmitting end located outside the system circuit 100 transmits a wake-up signal, such as a low frequency periodic signal (Low Frequency Periodic Signaling, LFPS), and the detecting circuit 120 detects the wake-up signal and generates a detection result to the control circuit 130 for judgment, when the control circuit 130 judges the wake-up signal, the control circuit 130 outputs the mode switching signals Vc1, vc2 to the multimode switching multiplexer 140 to select the mode setting S2 as the output mode setting SC for setting the receiver 110.

Fig. 4 is a schematic diagram of the operation of the components within the receiver 110 when the circuitry 100 is operating in the wake-up mode. As shown in fig. 4, under the control of the mode setting S2, the equalizer 310 and the adc 320 start to operate to establish a bias voltage and an operation point, and the clock generation circuit 340 switches to a Phase-Locked Loop (PLL) mode to oscillate the clock signal to a frequency near a required frequency for providing to the adc 320. In the wake mode, the receiver 110 still does not receive the video and audio data from the outside.

Then, after the circuit system 100 enters the wake-up mode, the circuit system 100 is ready to enter the receive mode, and the control circuit 130 outputs the mode switching signals Vc1 and Vc2 to the multimode switching multiplexer 140 to select the mode setting S3 as the output mode setting SC for setting the receiver 110. Fig. 5 is a schematic diagram of the operation of the components within the receiver 110 when the circuitry 100 is operating in the receive mode. As shown in fig. 5, under the control of the mode setting S3, the clock generating circuit 340 operates in a frequency and data recovery (Clock and Data Recovery Circuit, CDR) mode, and the receiver 110 starts to operate normally to receive the video and audio data from the outside. Specifically, the equalizer 310 receives an external input signal (audio/video signal) to generate an equalized signal, the adc 320 performs an adc operation on the equalized signal to generate a digital signal to the processing circuit 330, the processing circuit 330 processes the received digital signal to be transmitted to the control circuit 130 or other audio/video processing circuits for subsequent processing, and the processing circuit 330 further transmits the received digital signal to the clock generating circuit 340 for generating a clock signal.

As described above, by the design of the circuit system 100 of the present embodiment, the circuit system 100 can be quickly switched when the switch to the sleep mode, the wake-up mode and the receive mode is required, so as to solve the problem of delay caused by the need of firmware intervention in the prior art.

In this embodiment, the control circuit 130 may be a digital circuit and the multimode switching multiplexer 140 may be an analog circuit. However, in other embodiments, both the control circuit 130 and the multimode switching multiplexer 140 may be implemented using digital circuitry.

Briefly summarized, in the circuit system of the present invention, by using the multimode switching multiplexer to receive a plurality of mode settings from firmware at power-up, when the mode is switched subsequently, the appropriate mode settings can be generated to the receiver for element setting only through the processing of hardware, without involving the control of firmware, so that the purpose of rapidly switching modes can be achieved.

The foregoing description is only of the preferred embodiments of the invention, and all changes and modifications that come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein.

Reference numerals illustrate:

100: circuit system

110: receiver with a receiver body

120: detection circuit

130: control circuit

140: multimode switching multiplexer

150: microprocessor

160: memory element

162: program code

Vc1, vc2: mode switch signal

S1, S2 and S3: mode setting

SC: output mode setting

210. 220: multiplexer for multiplexing

310: equalizer

320: analog-to-digital converter

330: processing circuit

340: clock generating circuit

350: bias voltage generating circuit

SW1: and (3) a switch.

Claims

1. A circuit system, comprising:

a multimode switching multiplexer for receiving a plurality of mode settings from the firmware and selecting one of the plurality of mode settings as an output mode setting;

a control circuit for generating a mode switching signal to control the multimode switching multiplexer; and

the receiver is used for setting the internal elements according to the output mode setting.

2. The circuitry of claim 1, wherein the multimode switching multiplexer receives the plurality of mode settings from the firmware, and the plurality of mode settings are written to a receiving end of the multimode switching multiplexer.

3. The circuitry of claim 2, wherein the multimode switching multiplexer receives the plurality of mode settings from the firmware upon power up of the circuitry.

4. The circuitry of claim 2, wherein after the plurality of mode settings are written to the receiving end of the multimode switching multiplexer, the multimode switching multiplexer does not re-receive the plurality of mode settings from the firmware when the circuitry requires mode switching.

5. The circuit system of claim 2, wherein the control circuit is a digital circuit, the multimode switching multiplexer is a digital circuit or an analog circuit, and the control circuit generates the mode switching signal to control the multimode switching multiplexer to generate the output mode setting without involving control of the firmware.

6. The circuitry of claim 1, wherein the plurality of mode settings includes a first mode setting, a second mode setting, and a third mode setting, the control circuit generating a first mode switch signal and a second mode switch signal to control the multimode switching multiplexer; and the multimode switching multiplexer includes:

a first multiplexer for receiving the first mode setting and the second mode setting, and selecting one of the first mode setting and the second mode setting as an output of the first multiplexer according to the first mode switching signal; and

and a second multiplexer for receiving the third mode setting and the output of the first multiplexer, and selecting one of the third mode setting and the output of the first multiplexer as the output mode setting according to the second mode switching signal.

7. The circuitry of claim 1, wherein the circuitry is operable in a sleep mode, an awake mode, and a receive mode, the plurality of mode settings including a first mode setting corresponding to the sleep mode, a second mode setting corresponding to the awake mode, and a third mode setting corresponding to the receive mode.

8. The circuitry of claim 7, further comprising:

a detection circuit;

when the receiver receives an input signal and the control circuit judges that the input signal indicates the sleep mode, the circuit system operates in the sleep mode, and the control circuit generates the mode switching signal to control the multimode switching multiplexer to select the first mode setting as the output mode setting so as to set the receiver; when the circuit system is operated in the sleep mode and the detection circuit receives a wake-up signal, the circuit system is switched to the wake-up mode, and the control circuit generates the mode switching signal to control the multimode switching multiplexer to select the second mode setting as the output mode setting so as to set the receiver; and a period of time after the circuitry is operating in the wake-up mode, the circuitry switches to the receive mode, and the control circuitry generates the mode switch signal to control the multimode switch multiplexer to select the third mode setting as the output mode setting to set the receiver.

9. The circuitry of claim 8, wherein the receiver comprises an equalizer, an analog-to-digital converter, and clock generation circuitry; when the circuit system is operated in the sleep mode, the receiver is configured to turn off the equalizer, the analog-to-digital converter and the clock generation circuit according to the first mode; when the circuit system is operated in the wake-up mode, the receiver is set according to the second mode to start the equalizer, the analog-digital converter and the clock generation circuit, and the clock generation circuit is operated in a phase-locked loop mode; and when the circuitry is operating in the receive mode, the clock generation circuit is operating in a frequency and data recovery mode.

10. The circuitry defined in claim 1 wherein the circuitry supports a display interface standard.