CN116470927A

CN116470927A - Data processing method, device, equipment and storage medium

Info

Publication number: CN116470927A
Application number: CN202310411477.8A
Authority: CN
Inventors: 袁学龙
Original assignee: Shanghai Nano Technology Co ltd
Current assignee: Shanghai Nano Technology Co ltd
Priority date: 2023-04-17
Filing date: 2023-04-17
Publication date: 2023-07-21
Anticipated expiration: 2043-04-17

Abstract

The invention discloses a data processing method, a device, equipment and a storage medium. The method comprises the following steps: acquiring first data corresponding to at least one receiving antenna; obtaining a compression factor corresponding to each receiving antenna, and compressing the first data according to the compression factor corresponding to each receiving antenna to obtain second data corresponding to each receiving antenna; and determining target data according to the second data corresponding to each receiving antenna. According to the technical scheme, the first data corresponding to at least one receiving antenna are obtained, the compression factor corresponding to each receiving antenna is obtained, the first data are compressed according to the compression factor corresponding to each receiving antenna, the second data corresponding to each receiving antenna are obtained, and the target data are determined according to the second data corresponding to each receiving antenna. By adopting the technical scheme of the invention, the data of the receiving antenna can be compressed and rearranged, the data transmission efficiency is improved, and the resource consumption is reduced.

Description

Data processing method, device, equipment and storage medium

Technical Field

Embodiments of the present invention relate to the field of data processing technologies, and in particular, to a data processing method, apparatus, device, and storage medium.

Background

The transmitting antenna can send mass data to the receiving antenna, so that the requirements of the receiving antenna on data storage space, data processing efficiency and data transmission speed are increased. In this way, when data is stored, the data is processed in advance, and more data can be stored in the same storage space. For example by compression processing the data. The data compression refers to a technical method for reducing the data volume to reduce the storage space so as to improve the data transmission efficiency on the premise of not losing useful information, or reorganizing the data according to a certain algorithm so as to reduce the redundancy and the storage space of the data. However, the current data compression method has the problems of slow speed or data disorder and rearrangement in the compression process when the data is read and compressed, so that the subsequent data transmission efficiency is poor.

Disclosure of Invention

The embodiment of the invention provides a data processing method, a device, equipment and a storage medium, which can realize compression rearrangement of data of a receiving antenna, improve data transmission efficiency and reduce resource consumption.

According to an aspect of the present invention, there is provided a data processing method including:

Acquiring first data corresponding to at least one receiving antenna;

obtaining a compression factor corresponding to each receiving antenna, and compressing the first data according to the compression factor corresponding to each receiving antenna to obtain second data corresponding to each receiving antenna;

and determining target data according to the second data corresponding to each receiving antenna.

According to another aspect of the present invention, there is provided a data processing apparatus comprising:

the acquisition module is used for acquiring first data corresponding to at least one receiving antenna;

the acquisition and compression module is used for acquiring the compression factor corresponding to each receiving antenna, and compressing the first data according to the compression factor corresponding to each receiving antenna to obtain second data corresponding to each receiving antenna;

and the determining module is used for determining target data according to the second data corresponding to each receiving antenna.

According to another aspect of the present invention, there is provided an electronic apparatus including:

at least one processor; and

a memory communicatively coupled to the at least one processor; wherein,,

the memory stores a computer program executable by the at least one processor to enable the at least one processor to perform the data processing method according to any one of the embodiments of the present invention.

According to another aspect of the present invention, there is provided a computer readable storage medium storing computer instructions for causing a processor to execute a data processing method according to any one of the embodiments of the present invention.

According to the technical scheme, the first data corresponding to at least one receiving antenna are obtained, the compression factor corresponding to each receiving antenna is obtained, the first data are compressed according to the compression factor corresponding to each receiving antenna, the second data corresponding to each receiving antenna are obtained, and the target data are determined according to the second data corresponding to each receiving antenna. By adopting the technical scheme of the invention, the data of the receiving antenna can be compressed and rearranged, the data transmission efficiency is improved, and the resource consumption is reduced.

It should be understood that the description in this section is not intended to identify key or critical features of the embodiments of the invention or to delineate the scope of the invention. Other features of the present invention will become apparent from the description that follows.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are needed in the embodiments will be briefly described below, it being understood that the following drawings only illustrate some embodiments of the present invention and therefore should not be considered as limiting the scope, and other related drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

FIG. 1 is a flow chart of a data processing method in an embodiment of the invention;

FIG. 2 is a flow chart of a data processing method according to an embodiment of the invention;

FIG. 3 is a schematic diagram of a data processing apparatus according to an embodiment of the present invention;

fig. 4 is a schematic structural diagram of an electronic device implementing a data processing method according to an embodiment of the present invention.

Detailed Description

In order that those skilled in the art will better understand the present invention, a technical solution in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in which it is apparent that the described embodiments are only some embodiments of the present invention, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the present invention without making any inventive effort, shall fall within the scope of the present invention.

It should be noted that the terms "first," "second," and the like in the description and the claims of the present invention and the above figures are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate such that the embodiments of the invention described herein may be implemented in sequences other than those illustrated or otherwise described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.

Example 1

Fig. 1 is a flowchart of a data processing method in an embodiment of the present invention, where the present embodiment is applicable to a data processing case, and the method may be performed by a data processing apparatus in an embodiment of the present invention, where the apparatus may be implemented in software and/or hardware, as shown in fig. 1, and the method specifically includes the following steps:

s101, acquiring first data corresponding to at least one receiving antenna.

The first data may be data received by the receiving antenna and transmitted by the transmitting antenna.

In this embodiment, the number of antennas of one transmitting antenna array may be denoted as L, and the number of antennas of one receiving antenna array may be denoted as M. Where L and M are both nonzero numbers, preferably M may have a value of 32. The transmitting antenna transmits data to the receiving antenna, and the receiving antenna receives the data transmitted by the transmitting antenna.

S102, obtaining a compression factor corresponding to each receiving antenna, and compressing the first data according to the compression factor corresponding to each receiving antenna to obtain second data corresponding to each receiving antenna.

It should be noted that the compression factor may be a compression parameter when the first data corresponding to the receiving antenna is compressed, and one receiving antenna may correspond to one compression factor.

The second data may be data obtained by compressing the first data.

Specifically, after the first data corresponding to at least one receiving antenna is obtained, a compression factor corresponding to each receiving antenna is obtained, and then the first data corresponding to each receiving antenna is compressed according to the compression factor corresponding to each receiving antenna, so as to obtain second data corresponding to each receiving antenna after compression.

S103, determining target data according to the second data corresponding to each receiving antenna.

The target data may be data obtained by rearranging the second data corresponding to each receiving antenna.

Specifically, the second data corresponding to each receiving antenna is subjected to data rearrangement to obtain target data.

Optionally, acquiring first data corresponding to at least one receiving antenna includes:

and if the current condition meets the first preset condition, acquiring first data of a first preset quantity from the target memory.

The first preset condition comprises: the target memory writes at least one of the data corresponding to the target array surface or the memory is in an empty state.

In this embodiment, the target memory may be a memory for storing data transmitted by the transmitting antenna received by all the receiving antennas. Preferably, the target memory may be a DDR (Double Data Rate synchronous dynamic random Access memory).

It should be noted that the target array plane may be an antenna array plane formed by all receiving antennas.

The memory may be a memory for storing data read from the target memory. Preferably, the memory in this embodiment may be a DATA RAM (Data Random Access Memory, DATA memory bank).

The first preset number may be a number of data fetched from the target memory preset by a user according to an actual situation. Preferably, the first preset number may be 128×256 bits (128 is the maximum number of frequency points corresponding to the receiving antenna, and the effective data in 256 bits is 240 bits).

Specifically, when the DDR writes the DATA on the target array surface or the DATA RAM is empty, 128×256 bits of first DATA starts to be fetched from the DDR.

The first data is stored in the memory.

Specifically, the first DATA of 128×256 bits extracted from DDR is stored in the DATA RAM.

And if the current condition meets the second preset condition, reading the first data from the memory.

Wherein the second preset condition includes: the memory is full.

Specifically, when the DATA RAM is full, the reading of the first DATA from the DATA RAM is started.

Optionally, the memories include a first memory and a second memory, the first memory includes a first odd memory and a first even memory, and the second memory includes a second odd memory and a second even memory.

In this embodiment, the first DATA read from the DDR may be buffered using a ping-pong DATA RAM, that is, the memory DATA RAM may include 2 blocks of DATA RAM, which are respectively named as a first memory and a second memory, where the first memory may be a ping-pong RAM and the second memory may be a pong RAM. Specifically, the first memory, i.e. the ping RAM, may include 2 blocks of RAM, i.e. a first odd memory and a first even memory, where the first odd memory may be denoted as data_ram_o1, and is configured to store first data of odd frequency points; the first even memory may be denoted as data_ram_e1 for storing the first data of the even frequency bin. Similarly, the second memory, i.e. pong RAM, may include 2 blocks of RAM, i.e. a second odd-numbered memory and a second even-numbered memory, where the second odd-numbered memory may be denoted as data_ram_o2, and is configured to store first data of odd-numbered frequency points; the second even memory may be denoted as data_ram_e2 for storing the first data of the even frequency bins. In the actual operation process, the capacity of each RAM (i.e., the first odd memory, the first even memory, the second odd memory, and the second even memory) is 256×240 bits, the DATA RAM is a simple dual-port RAM, the input is a write port, the output is a read port, the input DATA width is 240 bits, and the output DATA width is 30 bits.

Storing the first data into the memory, including:

a set of data packets is determined from the first data.

Wherein the set of data packets includes at least one data subgroup.

In this embodiment, the data packet set may be a data packet set formed by grouping the first data into one data subgroup according to 8 pieces of 240-bit data, where one data subgroup includes 8 pieces of 240-bit first data.

Specifically, the first data is grouped into a data group according to 8 pieces of 240-bit data, so as to obtain a data group set, wherein the data group set comprises at least one data group, and each data group comprises 8 pieces of 240-bit first data.

And storing the second preset number of high-order data in each data group into the first odd-numbered memory.

The second preset number may be preset by a user according to an actual situation, and the number of data stored in the first odd-numbered memory in each data group is stored in the first odd-numbered memory. Preferably, the first preset number may be 4.

In this embodiment, the high-order data may be the data of the first second preset number of bits in the data group.

In the implementation process, when the first data is stored in the memory, the parity RAM, i.e., the first odd memory and the first even memory, is alternately written with data_ram_o1 and data_ram_e1.

Specifically, the first data of 8 240 bits is a data subgroup, and the first 4 240 bits of data in each data subgroup are written into the first odd memory data_ram_o1.

And storing the second preset number of low-order data in each data group into the first even-numbered memory.

In this embodiment, the low-order data may be the data of the second predetermined number of bits in the data group.

Specifically, the first data of 8 240 bits is a data subgroup, and the last 4 240 bits of data in each data subgroup are written into the first even memory data_ram_e1.

And when the first odd memory and the first even memory are detected to be full, storing a second preset number of high-order data in each data subgroup which is not stored in the data group set into the second odd memory, and storing a second preset number of low-order data in each data subgroup into the second even memory.

Specifically, when it is detected that the first odd memory data_ram_o1 and the first even memory data_ram_e1 are already full, the first 4 240-bit data of each data subgroup in each data subgroup remaining to be not stored in the data group set are written into the second odd memory data_ram_o2, and the last 4 240-bit data of each data subgroup are written into the second even memory data_ram_e2.

The parity RAM, namely data_ram_e and data_ram_o alternately writes first data, 8 240 bits are a data subgroup, the first 4 240 bits of data in each data subgroup are written into data_ram_e, and the last 4 240 bits of data are written into data_ram_o. Therefore, the data of even frequency points can be ensured to be written into data_ram_e, and the data of odd frequency points can be ensured to be written into data_ram_o. Meanwhile, ping pong DATA RAMs are also written alternately, when one of the DATA RAMs (e.g., ping pong RAM) is full, if the other DATA RAM (e.g., pong RAM) is empty, the DATA is written into the pong RAM.

Optionally, reading the first data from the memory includes:

and obtaining the maximum frequency point number corresponding to each receiving antenna and the preset frequency point number corresponding to each receiving antenna.

In this embodiment, the maximum frequency number corresponding to each receiving antenna may be 128.

The preset frequency point number corresponding to each receiving antenna may be a frequency point number preset by a user according to actual conditions. Specifically, the preset number of frequency points may be represented by N. Illustratively, the value of N may be 8, 16, 32, 64, or 128, as this is not limiting in this embodiment.

Specifically, the maximum frequency number 128 corresponding to each receiving antenna and the preset frequency number N corresponding to each receiving antenna are obtained.

In the actual operation process, the basic length of data compression is the preset frequency number N configured, each data is 15 bits, the data becomes 9 bits after compression, and N data of each receiving antenna is a compression unit.

And determining the cycle reading times of reading the first data from the memory according to the maximum frequency number corresponding to each receiving antenna and the preset frequency number corresponding to each receiving antenna.

It should be explained that the number of loop reading may be the number of loop reading the first data from the memory.

Specifically, when the DATA RAM is full, reading from the DATA RAM is started, and the number of cyclic readings for reading the first DATA from the memory is determined according to the maximum frequency number 128 corresponding to each receiving antenna and the preset frequency number N corresponding to each receiving antenna. For example, P may be used to represent the number of cyclic reads of the first data from the memory, and the determining manner of the number of cyclic reads P of the first data from the memory may be: the number of cyclic readings p=128/64=2 of the first data from the memory, i.e. the first data is read from the memory in 2 cycles, if the number of the preset frequency points N corresponding to each receiving antenna is 64.

And reading the first data from the memory according to the cycle reading times.

Specifically, the first data is read from the memory according to the number of cycle reading, and the reading sequence and the reading mode of the first data are the same in each cycle reading.

Optionally, reading the first data from the memory according to the number of cycle reads includes:

and sequentially reading the odd frequency point data of the target number corresponding to at least one receiving antenna from the first odd memory according to the cycle reading times.

The target number may be the number of data read from the first odd memory. Preferably, in this embodiment, the target number may be N/2, where N may be a preset number of frequency points, and N data of each receiving antenna is a compression unit.

The odd-frequency point data may be first data of odd-frequency points stored in the first odd-frequency memory.

Specifically, according to the cycle reading times, each reading reads the odd-frequency point data of N/2 number corresponding to the same receiving antenna from the first odd-frequency memory.

And sequentially reading even frequency point data of the target number corresponding to at least one receiving antenna from the first even memory according to the cycle reading times.

The even frequency point data may be first data of even frequency points stored in the first even memory.

Specifically, according to the number of cyclic reading times, each reading reads N/2 number of even frequency point data corresponding to the same receiving antenna from the first even memory.

The first data is determined from the odd-numbered frequency point data and the even-numbered frequency point data.

Specifically, after the N data (N/2 data are read from each of the first odd memory and the first even memory) of the same receiving antenna are read, the odd frequency point data and the even frequency point data are combined to form first data, where the data width of the first data is 2×30 bits.

In the actual operation process, after N data of one receiving antenna are read, N data of a next receiving antenna are read, where the next antenna may be an adjacent receiving antenna, and the adjacent may be specifically understood as that ID numbers of the receiving antennas are adjacent. After all the N data of the receiving antennas are read, the next cycle is performed.

Optionally, obtaining the compression factor corresponding to each receiving antenna includes:

and determining the compression factor corresponding to each receiving antenna according to the preset frequency number corresponding to each receiving antenna.

Specifically, for each receiving antenna, the compression FACTORs of the M receiving antennas are calculated by taking the data of N frequency points (i.e., the preset frequency point number N) as a group, and the compression FACTORs of all the receiving antennas are stored in corresponding compression FACTOR RAMs, where the compression FACTOR RAMs may be represented by a FACTOR RAM.

Optionally, obtaining a compression factor corresponding to each receiving antenna, and compressing the first data according to the compression factor corresponding to each receiving antenna to obtain second data corresponding to each receiving antenna, including:

identification information of each receiving antenna is acquired.

The identification information may be information having identification corresponding to each receiving antenna. Preferably, in the present embodiment, the identification information of each receiving antenna may be an ID number of each receiving antenna.

Specifically, the ID number of each receiving antenna is acquired.

And acquiring the compression factor corresponding to each receiving antenna according to the cycle reading times and the identification information of each receiving antenna.

Specifically, the compression factor of the corresponding receiving antenna is taken out from the compression factor RAM according to the cycle times and the identification information of each receiving antenna.

And compressing the first data according to the compression factor corresponding to each receiving antenna to obtain second data corresponding to each receiving antenna.

Specifically, according to the compression factor corresponding to each receiving antenna, the read odd-frequency point data and even-frequency point data are compressed in parallel (two paths of compression) at the same time, so as to obtain second data corresponding to each receiving antenna.

Optionally, determining the target data according to the second data corresponding to each receiving antenna includes:

and inputting the second data corresponding to each receiving antenna into a data rearrangement buffer to carry out data rearrangement according to the preset frequency number corresponding to each receiving antenna, so as to obtain target data, wherein the target data comprises a target compression factor and AXC data.

Wherein the target compression factor includes an I-component compression factor and a Q-component compression factor.

In this embodiment, the data rearrangement of the second data corresponding to each receiving antenna is implemented by using a data rearrangement buffer, that is, a data buffer, which is implemented by using a shift register.

The target compression factor may be a compression factor corresponding to the target data after the rearrangement of the second data, and the AXC data may be other data except the target compression factor in the target data after the rearrangement of the second data.

Specifically, the second data corresponding to each receiving antenna may be data arranged according to the ID number of the receiving antenna, where the second data may be an 18-bit data stream, and needs to be converted into a 30-bit data stream (thereby implementing data rearrangement), that is, N (preset frequency number) 18 bits are changed into nc=round dup (n×18/30) (where round dup is an upward integer) 30 bits. The rearranged data format may be: the lower 6 bits are the target compression factor (the I component compression factor and the Q component compression factor are each 3 bits, specifically, bits 2 to 0 are the I component compression factor, bits 5 to 3 are the Q component compression factor), and the other 24 bits are the AXC data.

In the actual operation, the rearranged data format may also be pure 30-bit AXC data.

As an exemplary description of an embodiment of the present invention, fig. 2 is a schematic flow chart of a data processing method in an embodiment of the present invention. As shown in fig. 2, taking the number M of receiving antennas as 32 as an example, a data processing method includes the following operations:

the first DATA read from the DDR is buffered using ping pong DATA RAMs (the ping pong DATA RAMs are not labeled in fig. 2, and may be respectively a ping pong DATA RAM and a ping pong DATA RAM, or may be respectively a ping pong DATA RAM and a ping pong DATA RAM, which is not limited in this embodiment), each of the two ping pong DATA RAMs includes 2 parity RAMs for storing the first DATA of the parity frequency point, the parity RAMs may be respectively represented by data_ram_o and data_ram_e (the parity RAMs, that is, the data_ram_o and the data_ram_e, are not labeled in fig. 2, the 2 parity RAMs may be respectively data_ram_o and data_ram_e, or may be respectively data_ram_e and data_ram_o, which is not limited in this embodiment), and the capacity of each parity RAM is 256×240 bits. The two DATA RAMs are simple dual-port RAMs, the input is a write port, the output is a read port, the DATA width of the input is 240 bits, and the DATA width of the output is 30 bits. In fig. 2, the MUX represents a selector, and the MUX at the DATA RAM is used to select which DATA RAM is to be compressed, and in fig. 2, the compression represents the compression of DATA, and the data_reorder represents the rearrangement of DATA.

After the compression FACTORs of the 32 receiving antennas are calculated, the compression FACTORs are stored in a FACTOR RAM, and the compression FACTORs are also stored by two RAMs, namely the FACTOR RAM comprises two RAMs which respectively correspond to the DATA of the ping-pong DATA RAMs. In fig. 2, MUX means a selector, and MUX at the FACTOR RAM is used to select two FACTOR RAMs from which to read compression FACTORs.

In this embodiment, the basic length of the contracted data compression is the preset frequency number N configured, each data is 15 bits, and the compressed data becomes 9 bits. The number of antennas of one transmitting antenna array is L, and the number of antennas of one receiving antenna array is M. The N data for each receive antenna is a compression unit.

A specific implementation of a data processing method may be described as: when the DDR finishes writing the first DATA of one array surface or the DATA RAM is empty, the first DATA of 128 (maximum frequency point number) x 256 bits (the effective DATA in 256 bits is 240 bits) are taken out from the DDR and sequentially stored in the DATA RAM (the first DATA corresponding to the odd frequency point is stored in the data_ram_o, and the first DATA corresponding to the even frequency point is stored in the data_ram_e), and meanwhile, the 32 receiving antennas respectively calculate respective compression factors and store the respective compression factors in the corresponding compression factor RAMs. When the DATA RAM is full, reading of the first DATA from the DATA RAM is started, and the number of cyclic reads P of the first DATA from the DATA RAM is determined according to the value of the maximum number of frequency points 128/the preset number of frequency points N.

Specifically, each cycle of reading the first DATA from the DATA RAM may be: at each reading, simultaneously reading N first data of the same receiving antenna from the parity RAM (N/2 first data are respectively read from the parity RAM), and merging the data widths into 2 x 30 bits; and simultaneously, the compression factors of the corresponding receiving antennas are taken out from the compression factor RAM according to the cycle reading times and the ID numbers of the receiving antennas, and the read parity frequency data are compressed in parallel (two paths of compression). And after the N first data of the same receiving antenna are read, the N data of the next receiving antenna are read, and after the N data of all the receiving antennas are read, the next cycle is carried out.

The compressed second data is changed into 18 bits (30 bits in the non-compression state), the two paths of compression are combined into 36 bits, and the 36 bits are sent to a data rearrangement buffer and converted into continuous 30-bit data. The data rearrangement buffer is realized by using a shift register, and each time 36 bits are shifted in, 30 bits are shifted out.

The DATA of one DATA RAM can be read completely by P times of DATA cycle reading, and the DATA of the other DATA RAM is read after the DATA cycle reading is completed. The final AXC data stream should be guaranteed to be continuous without interruption in the middle to facilitate subsequent reception processing.

In actual operation, the storage format of the first data at DDR is shown in table 1:

TABLE 1

Where ti represents the ith transmitting antenna, one transmitting antenna array has L antennas, f represents the number of frequency points, and in this embodiment, the preset number of frequency points is N.

In actual operation, the storage format of the first DATA in the DATA RAM is as shown in table 2:

TABLE 2

Wherein, only the storage format of the x-th group is listed, x is an integer from 0 to P-1. x in fact represents the transmit antenna number (modulo the value of P).

The parity RAM, namely data_ram_e and data_ram_o, is written alternately, 8 240 bits are set as a group, the first 4 are written into data_ram_e, and the last 4 are written into data_ram_o. Therefore, the data of even frequency points can be ensured to be written into data_ram_e, and the data of odd frequency points can be ensured to be written into data_ram_o. Ping pong DATA RAMs are also written alternately, with one DATA RAM (e.g., ping pong DATA RAM) being written full and the first DATA being written if the other DATA RAM (e.g., pong DATA RAM) is already read empty.

The data_ram_e and the data_ram_o have the same read address, and the specific addressing mode is as follows:

S_dram_raddr＝S_dram_raddr+M；

the initial address for each round of reading is:

S_dram_raddr＝S_rx_ant_cnt+S_loop_cnt*M*N/2。

wherein M is the total number of receiving antennas, N is the number of preset frequency points, S_rx_ant_cnt is a receiving antenna counter (counting from 0), 1 is added when N/2 data of one receiving antenna are read out each time, until M-1 is counted, and the corresponding N/2 data are returned to 0 after the reading out. S_loop_cnt is a loop counter that is incremented by 1 every time N/2 data (i.e., a set of data) for M receive antennas are read until P-1 is counted.

When one of the ping-pong DATA RAMs is read, the DATA is seamlessly switched to the other DATA RAM.

In the actual operation, the storage format of the compression FACTOR in the FACTOR RAM is shown in table 3:

TABLE 3 Table 3

Wherein, p=128/N, 128 is the maximum frequency point number, and N is the preset frequency point number. The FACTOR RAM is a double-open RAM, the bit width of the input port and the output port is 6*M bits, and M is the antenna number of a receiving antenna array.

In actual operation, the write address when the compression FACTOR is written into the FACTOR RAM can be expressed as: s_wrader= (s_freq_cnt= N-1)? S_wrader+1, and the value range is 0-P-1. Wherein s_freq_cnt is a frequency point counter, and N frequency points data obtain a compression factor.

The read address when the compression FACTOR is read from the FACTOR RAM is s_loop_cnt, and the corresponding antenna compression FACTOR is selected by s_rx_ant_cnt after data is read.

In the actual operation process, the data rearrangement can be realized by using a data buffer, and the data buffer is realized by a shift register. The size of the data buffer is 66 bits, S_din_Buff [65:0].

During data input, each cycle is shifted to the right by 36 bits to s_din_buff, wherein when s_6_cnt=5 or s_data_cnt=nc-1, the input 36 bits data is 0 while s_6_cnt is 0. When s_6_cnt=1, 30 bits of data are sequentially output from s_din_buff, but it is required to ensure that the corresponding output data when s_6_cnt=1 is always s_din_buff [59:30], and the bit position of the output data of the next beat is 6 smaller than the bit position of the output data of the previous beat. The truth table is shown in table 4:

TABLE 4 Table 4

In actual operation, the compressed second data arrangement is shown in table 5:

TABLE 5

f0

f1

f2

f3

f4

f5

f6

f7

...

f _N-1

r _m

D(r _m ,f0)

D(r _m ,f1)

D(r _m ,f2)

D(r _m ,f3)

D(r _m ,f4)

D(r _m ,f5)

D(r _m ,f6)

D(r _m ,f7)

...

D(r _m ,f _N-1 )

Wherein r is _m The ID number of the receiving antenna is m, the data width is 18 bits, and the data quantity of N frequency points of one receiving antenna is 18 x N bits.

The data in table 5 is an 18-bit data stream, which needs to be converted into a 30-bit data stream (thereby realizing data rearrangement), that is, N18 bits, into nc=round (n×18/30) (where round is rounded up) 30 bits. The compression factor is then inserted in the 30-bit data stream. Since the last data (AXC data) of each compression block (data set of N frequency points for one receiving antenna, i.e. the preset number of frequency points is N) is not filled, i.e. there are enough dummy bits remaining, which are enough to carry the target compression factor (6 bits). Of course, for the convenience of processing at the receiving end, a compression factor can be inserted into bits 5-0 of the first AXC of each data block, other data bit streams are forward by 6 bits, and the last AXC is automatically discarded by 6 bits (dummy bits). The data format of the rearranged target data is shown in table 6:

TABLE 6

0	1	2	3	4	5	6	7	...	Nc
										axc0	axc1	axc2	axc3	axc4	axc5	axc6	axc7	...	axcNc-1

Wherein, the data bit width of AXC-AXC (Nc-1) is 30 bits, the low 6 bits of AXC0 are the target compression factors (3 bits of each of the I component compression factor and the Q component compression factor, bit 2-0 is the I component compression factor, bit 5-3 is the Q component compression factor), and the other 24 bits are the AXC data. Specifically, the data format of axc0 is shown in table 7:

TABLE 7

The overall processing cycle from DDR read out to complete the compression rearrangement of the data is approximately 2560 cycles. Specifically, when the preset frequency point number N is 8, 16 or 32 frequency points, the processing period is 2560 cycles; when the preset frequency point number N is 64 frequency points, the processing period is 2496 cycles; when the preset frequency point number N is 128 frequency points, the processing period is 2464 cycles.

According to the technical scheme provided by the embodiment of the invention, the function designed for the data processing method has reasonable implementation architecture, the design is simplified, and the consumption of resources is low. In addition, during the data processing, other operations are processed in real time except for a certain time overhead caused by the need of buffering when the first data is read from the DDR, so that the processing delay is small. Meanwhile, the data processing method supports the compression function, so that the data transmission efficiency is improved.

Example two

Fig. 3 is a schematic structural diagram of a data processing apparatus according to an embodiment of the present invention. The present embodiment may be applied to the case of data processing, and the apparatus may be implemented in software and/or hardware, and the apparatus may be integrated in any device that provides a function of data processing, as shown in fig. 3, where the data processing apparatus specifically includes: an acquisition module 201, an acquisition and compression module 202 and a determination module 203.

The acquiring module 201 is configured to acquire first data corresponding to at least one receiving antenna;

the acquiring and compressing module 202 is configured to acquire a compression factor corresponding to each receiving antenna, and compress the first data according to the compression factor corresponding to each receiving antenna to obtain second data corresponding to each receiving antenna;

and the determining module 203 is configured to determine target data according to the second data corresponding to each receiving antenna.

Optionally, the obtaining module 201 includes:

the first obtaining unit is configured to obtain a first preset number of first data from the target memory if the current condition meets a first preset condition, where the first preset condition includes: the target memory is written with at least one of data corresponding to the target array surface or the memory is in an empty state;

the storage unit is used for storing the first data into the memory;

the reading unit is configured to read the first data from the memory if the current condition meets a second preset condition, where the second preset condition includes: the memory is full.

Optionally, the memory includes a first memory and a second memory, the first memory includes a first odd memory and a first even memory, and the second memory includes a second odd memory and a second even memory;

The memory cell includes:

a first determining subunit, configured to determine a set of data packets according to the first data, where the set of data packets includes at least one data subgroup;

a first storage subunit, configured to store a second preset number of high-order data in each data group into the first odd-numbered memory;

a second storage subunit, configured to store a second preset number of low-order data in each data group into the first even-numbered memory;

and the third storage subunit is used for storing a second preset number of high-order data in each data subgroup which is not stored in the data group set into the second odd-numbered memory when the first odd-numbered memory and the first even-numbered memory are detected to be full, and storing a second preset number of low-order data in each data subgroup into the second even-numbered memory.

Optionally, the reading unit includes:

the acquisition subunit is used for acquiring the maximum frequency point number corresponding to each receiving antenna and the preset frequency point number corresponding to each receiving antenna;

the second determining subunit is used for determining the cycle reading times of reading the first data from the memory according to the maximum frequency point number corresponding to each receiving antenna and the preset frequency point number corresponding to each receiving antenna;

And the reading subunit is used for reading the first data from the memory according to the cycle reading times.

Optionally, the reading subunit is specifically configured to:

sequentially reading odd-frequency point data of a target number corresponding to at least one receiving antenna from the first odd-frequency memory according to the cycle reading times;

sequentially reading the even frequency point data of the target number corresponding to at least one receiving antenna from the first even memory according to the cycle reading times;

and determining first data according to the odd frequency point data and the even frequency point data.

Optionally, the acquiring and compressing module 202 includes:

and the determining unit is used for determining the compression factor corresponding to each receiving antenna according to the preset frequency number corresponding to each receiving antenna.

Optionally, the acquiring and compressing module 202 includes:

a second obtaining unit, configured to obtain identification information of each receiving antenna;

the third acquisition unit is used for acquiring the compression factor corresponding to each receiving antenna according to the cycle reading times and the identification information of each receiving antenna;

and the compression unit is used for compressing the first data according to the compression factor corresponding to each receiving antenna to obtain second data corresponding to each receiving antenna.

Optionally, the determining module 203 includes:

and the data rearrangement unit is used for inputting the second data corresponding to each receiving antenna into the data rearrangement buffer for data rearrangement according to the preset frequency number corresponding to each receiving antenna to obtain target data, wherein the target data comprises a target compression factor and AXC data, and the target compression factor comprises an I component compression factor and a Q component compression factor.

The product can execute the data processing method provided by any embodiment of the invention, and has the corresponding functional modules and beneficial effects of executing the data processing method.

Example III

Fig. 4 shows a schematic diagram of an electronic device 30 that may be used to implement an embodiment of the invention. Electronic devices are intended to represent various forms of digital computers, such as laptops, desktops, workstations, personal digital assistants, servers, blade servers, mainframes, and other appropriate computers. Electronic equipment may also represent various forms of mobile devices, such as personal digital processing, cellular telephones, smartphones, wearable devices (e.g., helmets, glasses, watches, etc.), and other similar computing devices. The components shown herein, their connections and relationships, and their functions, are meant to be exemplary only, and are not meant to limit implementations of the inventions described and/or claimed herein.

As shown in fig. 4, the electronic device 30 includes at least one processor 31, and a memory, such as a Read Only Memory (ROM) 32, a Random Access Memory (RAM) 33, etc., communicatively connected to the at least one processor 31, wherein the memory stores a computer program executable by the at least one processor, and the processor 31 can perform various suitable actions and processes according to the computer program stored in the Read Only Memory (ROM) 32 or the computer program loaded from the storage unit 38 into the Random Access Memory (RAM) 33. In the RAM 33, various programs and data required for the operation of the electronic device 30 may also be stored. The processor 31, the ROM 32 and the RAM 33 are connected to each other via a bus 34. An input/output (I/O) interface 35 is also connected to bus 34.

Various components in electronic device 30 are connected to I/O interface 35, including: an input unit 36 such as a keyboard, a mouse, etc.; an output unit 37 such as various types of displays, speakers, and the like; a storage unit 38 such as a magnetic disk, an optical disk, or the like; and a communication unit 39 such as a network card, modem, wireless communication transceiver, etc. The communication unit 39 allows the electronic device 30 to exchange information/data with other devices via a computer network, such as the internet, and/or various telecommunication networks.

The processor 31 may be a variety of general and/or special purpose processing components having processing and computing capabilities. Some examples of processor 31 include, but are not limited to, a Central Processing Unit (CPU), a Graphics Processing Unit (GPU), various specialized Artificial Intelligence (AI) computing chips, various processors running machine learning model algorithms, digital Signal Processors (DSPs), and any suitable processor, controller, microcontroller, etc. The processor 31 performs the various methods and processes described above, such as the data processing method:

acquiring first data corresponding to at least one receiving antenna;

In some embodiments, the data processing method may be implemented as a computer program tangibly embodied on a computer-readable storage medium, such as the storage unit 38. In some embodiments, part or all of the computer program may be loaded and/or installed onto the electronic device 30 via the ROM 32 and/or the communication unit 39. When the computer program is loaded into RAM 33 and executed by processor 31, one or more steps of the data processing method described above may be performed. Alternatively, in other embodiments, the processor 31 may be configured to perform the data processing method in any other suitable way (e.g., by means of firmware).

Various implementations of the systems and techniques described here above may be implemented in digital electronic circuitry, integrated circuit systems, field Programmable Gate Arrays (FPGAs), application Specific Integrated Circuits (ASICs), application Specific Standard Products (ASSPs), systems On Chip (SOCs), load programmable logic devices (CPLDs), computer hardware, firmware, software, and/or combinations thereof. These various embodiments may include: implemented in one or more computer programs, the one or more computer programs may be executed and/or interpreted on a programmable system including at least one programmable processor, which may be a special purpose or general-purpose programmable processor, that may receive data and instructions from, and transmit data and instructions to, a storage system, at least one input device, and at least one output device.

A computer program for carrying out methods of the present invention may be written in any combination of one or more programming languages. These computer programs may be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus, such that the computer programs, when executed by the processor, cause the functions/acts specified in the flowchart and/or block diagram block or blocks to be implemented. The computer program may execute entirely on the machine, partly on the machine, as a stand-alone software package, partly on the machine and partly on a remote machine or entirely on the remote machine or server.

In the context of the present invention, a computer-readable storage medium may be a tangible medium that can contain, or store a computer program for use by or in connection with an instruction execution system, apparatus, or device. The computer readable storage medium may include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination of the foregoing. Alternatively, the computer readable storage medium may be a machine readable signal medium. More specific examples of a machine-readable storage medium would include an electrical connection based on one or more wires, a portable computer diskette, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

To provide for interaction with a user, the systems and techniques described here can be implemented on an electronic device having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to a user; and a keyboard and a pointing device (e.g., a mouse or a trackball) through which a user can provide input to the electronic device. Other kinds of devices may also be used to provide for interaction with a user; for example, feedback provided to the user may be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user may be received in any form, including acoustic input, speech input, or tactile input.

The systems and techniques described here can be implemented in a computing system that includes a background component (e.g., as a data server), or that includes a middleware component (e.g., an application server), or that includes a front-end component (e.g., a user computer having a graphical user interface or a web browser through which a user can interact with an implementation of the systems and techniques described here), or any combination of such background, middleware, or front-end components. The components of the system can be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include: local Area Networks (LANs), wide Area Networks (WANs), blockchain networks, and the internet.

The computing system may include clients and servers. The client and server are typically remote from each other and typically interact through a communication network. The relationship of client and server arises by virtue of computer programs running on the respective computers and having a client-server relationship to each other. The server can be a cloud server, also called a cloud computing server or a cloud host, and is a host product in a cloud computing service system, so that the defects of high management difficulty and weak service expansibility in the traditional physical hosts and VPS service are overcome.

It should be appreciated that various forms of the flows shown above may be used to reorder, add, or delete steps. For example, the steps described in the present invention may be performed in parallel, sequentially, or in a different order, so long as the desired results of the technical solution of the present invention are achieved, and the present invention is not limited herein.

The above embodiments do not limit the scope of the present invention. It will be apparent to those skilled in the art that various modifications, combinations, sub-combinations and alternatives are possible, depending on design requirements and other factors. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the scope of the present invention.

Claims

1. A method of data processing, comprising:

acquiring first data corresponding to at least one receiving antenna;

2. The method of claim 1, wherein obtaining first data corresponding to at least one receive antenna comprises:

if the current condition meets a first preset condition, acquiring first data of a first preset quantity from a target memory, wherein the first preset condition comprises: the target memory is written with at least one of data corresponding to the target array surface or the memory is in an empty state;

storing the first data into the memory;

if the current condition meets a second preset condition, reading the first data from the memory, wherein the second preset condition comprises: the memory is full.

3. The method of claim 2, wherein the memory comprises a first memory and a second memory, the first memory comprising a first odd memory and a first even memory, the second memory comprising a second odd memory and a second even memory;

storing the first data into the memory, including:

determining a set of data packets from the first data, wherein the set of data packets includes at least one data subgroup therein;

storing a second preset number of high-order data in each data subgroup into the first odd memory;

Storing a second preset number of low-order data in each data subgroup into the first even memory;

4. The method of claim 2, wherein reading the first data from the memory comprises:

obtaining the maximum frequency point number corresponding to each receiving antenna and the preset frequency point number corresponding to each receiving antenna;

determining the cycle reading times of reading the first data from the memory according to the maximum frequency point number corresponding to each receiving antenna and the preset frequency point number corresponding to each receiving antenna;

5. The method of claim 3, wherein reading the first data from the memory according to the number of loop reads comprises:

6. The method of claim 4, wherein obtaining the compression factor for each of the receive antennas comprises:

7. The method of claim 4, wherein obtaining the compression factor corresponding to each of the receiving antennas, and compressing the first data according to the compression factor corresponding to each of the receiving antennas, to obtain the second data corresponding to each of the receiving antennas, comprises:

acquiring identification information of each receiving antenna;

acquiring a compression factor corresponding to each receiving antenna according to the cycle reading times and the identification information of each receiving antenna;

8. A method according to claim 3, wherein determining target data from the second data corresponding to each of the receive antennas comprises:

and inputting the second data corresponding to each receiving antenna into a data rearrangement buffer for data rearrangement according to the preset frequency number corresponding to each receiving antenna to obtain target data, wherein the target data comprises a target compression factor and AXC data, and the target compression factor comprises an I component compression factor and a Q component compression factor.

9. A data processing apparatus, comprising:

10. An electronic device, the electronic device comprising:

at least one processor; and

a memory communicatively coupled to the at least one processor; wherein,,

the memory stores a computer program executable by the at least one processor to enable the at least one processor to perform the data processing method of any one of claims 1-8.

11. A computer-readable storage medium, characterized in that the computer-readable storage medium stores computer instructions for causing a processor to implement the data processing method of any one of claims 1-8 when executed.