CN116469804A

CN116469804A - Chip grouping method and device, power module, power equipment and electronic equipment

Info

Publication number: CN116469804A
Application number: CN202310410301.0A
Authority: CN
Inventors: 周彦栋; 叶忠; 杨义
Original assignee: Inventchip Technology Co Ltd
Current assignee: Inventchip Technology Co Ltd
Priority date: 2023-04-14
Filing date: 2023-04-14
Publication date: 2023-07-21

Abstract

The disclosure relates to a chip grouping method and device, a power module, power equipment and electronic equipment, wherein the method comprises the following steps: dividing each chip subjected to qualification test on a wafer into a plurality of chip sets, wherein the difference of the same parameters of any two chips in each chip set is smaller than a corresponding parameter threshold; and sequencing the chip groups according to the target parameters, and sequentially dividing the sequenced chip groups into a plurality of chip units, wherein each chip unit comprises at least one chip group. According to the embodiment of the disclosure, the difference of each parameter of each chip is smaller in one chip unit, the adjacent chip units after sequencing also have continuity, and the target parameter difference value between the adjacent chip units is smaller, so that the chip units are used for realizing high-power modules or other devices, dynamic and static uneven flow cannot be caused, and the reliability is improved.

Description

Chip grouping method and device, power module, power equipment and electronic equipment

Technical Field

The disclosure relates to the technical field of semiconductors, and in particular relates to a chip grouping method and device, a power module, power equipment and electronic equipment.

Background

The high-power module is realized by connecting multiple dies in parallel to improve the current capability, and at present, a technician usually selects the dies to be connected in parallel at will, however, the method easily causes dynamic and static uneven flow, so that the temperature of one die is higher than that of the other dies, and the reliability problem is caused.

Disclosure of Invention

According to an aspect of the present disclosure, there is provided a chip grouping method, the method including:

dividing each chip subjected to qualification test on a wafer into a plurality of chip sets, wherein the difference of the same parameters of any two chips in each chip set is smaller than a corresponding parameter threshold;

and sequencing the chip groups according to the target parameters, and sequentially dividing the sequenced chip groups into a plurality of chip units, wherein each chip unit comprises at least one chip group.

In one possible implementation manner, the dividing the chips on the wafer after passing the qualification test into a plurality of chip sets includes:

sequencing the chips according to preset parameters, continuously selecting K chips according to sequencing results, and dividing the chips into a plurality of chip groups;

sequentially determining first parameters of chips in each chip set according to a set parameter comparison sequence, if the difference between the first parameters of any pair of chips in any one chip set is larger than a first parameter threshold corresponding to the first parameters, removing the chips corresponding to the parameter outliers in the pair of chips, sequencing and dividing the chip sets according to the preset parameters, and executing comparison of the first parameters until the difference between the first parameters of any two chips in each chip set is smaller than the first parameter threshold;

And sequentially selecting other parameters according to the set parameter comparison sequence to perform the above operation until the difference between the same parameters of any two chips in each chip set is smaller than the corresponding parameter threshold.

and taking the preset parameters as the last comparison parameters, sequentially determining the preset parameters of all chips in all the chip sets, if the difference of the preset parameters of any pair of chips in any one chip set is larger than a preset parameter threshold corresponding to the preset parameters, removing the chips corresponding to the parameter outliers in the pair of chips, sequencing and dividing the chip sets according to the preset parameters, and executing the comparison of the preset parameters until the difference of the preset parameters of any two chips in all the chip sets is smaller than the preset parameter threshold.

processing preset parameters of chips in each chipset to obtain target parameters, sequencing each chipset according to the target parameters, removing the chipsets corresponding to the parameter outliers in the chipsets if the difference between the target parameters of any two adjacent chipsets is larger than a target parameter threshold corresponding to the target parameters, sequencing and dividing the chipsets again according to the preset parameters, and executing comparison of the target parameters until the difference between the target parameters of each chipset is smaller than the target parameter threshold.

In a possible implementation manner, the processing the preset parameters of each chip in each chipset to obtain target parameters includes:

and taking any one of the average value, the median, the mean square error and the variance of preset parameters of each chip in each chip group as the target parameter.

In one possible implementation manner, the wafer is a MOSFET wafer based on a composite semiconductor material, the parameter includes at least one of on-current, threshold current, on-resistance, on-voltage, threshold voltage, transconductance, coss output capacitance, temperature drift coefficient, and device leakage inductance, the target parameter is obtained according to a preset parameter, the preset parameter is any one of on-current, threshold current, on-resistance, on-voltage, and threshold voltage,

wherein the method further comprises:

and testing the MOSFET wafer, and eliminating chips which are unqualified in the test.

According to an aspect of the present disclosure, there is provided a method of manufacturing a power module, the method including:

determining a plurality of chip units by using the chip grouping method;

and connecting the chips in the chip units in parallel, and manufacturing the power module by using the chip units.

In one possible implementation, the power modules include half-bridge power modules, full-bridge power modules, three-phase bridge power modules, and multi-phase bridge power modules.

According to an aspect of the present disclosure, there is provided a power module manufactured by the method of manufacturing a power module.

According to an aspect of the present disclosure, there is provided a power device including the power module.

According to an aspect of the present disclosure, there is provided a chip grouping apparatus, the apparatus including:

the dividing module is used for dividing each chip subjected to the qualification test on the wafer into a plurality of chip sets, and the difference of the same parameters of any two chips in each chip set is smaller than a corresponding parameter threshold;

the sorting module is used for sorting the chip sets according to the target parameters and dividing the sorted chip sets into a plurality of chip units in sequence, wherein each chip unit comprises at least one chip set.

According to an aspect of the present disclosure, there is provided an electronic apparatus including: a processor; a memory for storing processor-executable instructions; wherein the processor is configured to invoke the instructions stored in the memory to perform the above method.

According to an aspect of the present disclosure, there is provided a computer readable storage medium having stored thereon computer program instructions which, when executed by a processor, implement the above-described method.

According to the embodiment of the disclosure, each chip subjected to qualification test on the wafer is divided into a plurality of chip sets, and the difference of the same parameters of any two chips in each chip set is smaller than a corresponding parameter threshold; the chip sets are ordered according to the target parameters, the ordered chip sets are sequentially divided into a plurality of chip units, each chip unit comprises at least one chip set, so that the difference of the parameters of each chip is smaller in one chip unit, adjacent chip units after the ordering are also continuous, the target parameter difference between the adjacent chip units is smaller, the chip units are used for realizing high-power modules or other devices, dynamic and static uneven flow cannot be caused, and the reliability is improved.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure. Other features and aspects of the present disclosure will become apparent from the following detailed description of exemplary embodiments, which proceeds with reference to the accompanying drawings.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the disclosure and together with the description, serve to explain the technical aspects of the disclosure.

Fig. 1 shows a flow chart of a chip grouping method according to an embodiment of the present disclosure.

Fig. 2 shows a flow chart of a chip grouping method according to an embodiment of the present disclosure.

Fig. 3 shows a schematic diagram of a chip grouping method according to an embodiment of the disclosure.

Fig. 4 shows a schematic diagram of screening chips according to an embodiment of the disclosure.

Fig. 5 shows a chip unit division schematic according to an embodiment of the present disclosure.

Fig. 6 shows a schematic diagram of a new wafer Map formed in accordance with an embodiment of the present disclosure.

Fig. 7 illustrates a method of manufacturing a power module according to an embodiment of the present disclosure.

Fig. 8 shows a block diagram of a chip grouping apparatus according to an embodiment of the disclosure.

Fig. 9 shows a block diagram of an electronic device according to an embodiment of the disclosure.

Detailed Description

Various exemplary embodiments, features and aspects of the disclosure will be described in detail below with reference to the drawings. In the drawings, like reference numbers indicate identical or functionally similar elements. Although various aspects of the embodiments are illustrated in the accompanying drawings, the drawings are not necessarily drawn to scale unless specifically indicated.

In the description of the present disclosure, it should be understood that the terms "length," "width," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," and the like indicate orientations or positional relationships based on the orientation or positional relationships shown in the drawings, merely to facilitate description of the present disclosure and simplify the description, and do not indicate or imply that the devices or elements referred to must have a particular orientation, be configured and operated in a particular orientation, and thus should not be construed as limiting the present disclosure.

Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature. In the description of the present disclosure, the meaning of "a plurality" is two or more, unless explicitly defined otherwise.

In the present disclosure, unless explicitly specified and limited otherwise, the terms "mounted," "connected," "secured," and the like are to be construed broadly, and may be, for example, fixedly connected, detachably connected, or integrally formed; can be mechanically or electrically connected; can be directly connected or indirectly connected through an intermediate medium, and can be communicated with the inside of two elements or the interaction relationship of the two elements. The specific meaning of the terms in this disclosure will be understood by those of ordinary skill in the art as the case may be.

The word "exemplary" is used herein to mean "serving as an example, embodiment, or illustration. Any embodiment described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments.

The term "and/or" is herein merely an association relationship describing an associated object, meaning that there may be three relationships, e.g., a and/or B, may represent: a exists alone, A and B exist together, and B exists alone. In addition, the term "at least one" herein means any one of a plurality or any combination of at least two of a plurality, for example, including at least one of A, B, C, and may mean including any one or more elements selected from the group consisting of A, B and C.

Furthermore, numerous specific details are set forth in the following detailed description in order to provide a better understanding of the present disclosure. It will be understood by those skilled in the art that the present disclosure may be practiced without some of these specific details. In some instances, methods, means, elements, and circuits well known to those skilled in the art have not been described in detail in order not to obscure the present disclosure.

As described in the background art, the technician usually selects the dies to implement the high-power module in parallel at will, because the most mature in the semiconductor industry is the silicon-based semiconductor at present, because the silicon-based semiconductor technology is mature, the random combination basically does not have the reliability problem caused by uneven flow, and because of the long-term inertia thinking, even for the third generation semiconductor taking the composite semiconductor material (silicon carbide, gallium nitride and the like) as the substrate, the technician usually also selects the dies to implement each device at will, even if the subsequent problem occurs in the device, the technician cannot realize where the root of the problem is, that is, the technician cannot effectively solve the problem that the problem is caused by the fact that the chip screening is not performed because of the limitation caused by the inertia thinking, the inventor has sharp problems about the problem that the problem occurs in the device because of the fact that the material and the process of the die is sensitive, the number of the die is different along with different batches or the parameters of the same batch at different positions are different, even the parameters of the same wafer at different positions are different, because the yield and edge factors are different from the adjacent to the die, even if the parameters of the same wafer are different from the adjacent to the semiconductor material, namely the semiconductor is different from the semiconductor at the same time, the semiconductor is easy to implement the high-speed because of the semiconductor is different from the semiconductor material due to the fact that the semiconductor is different from the current batch, the semiconductor is different from the wafer, especially high-quality factors, the semiconductor is easy to be the wafer has the semiconductor to be different from the wafer due to the fact that the semiconductor is different from the wafer has the fact different to be the wafer due to be the fact different to be the wafer due to the fact different from the wafer factors.

Therefore, the disclosure provides a chip grouping method, which divides each chip subjected to qualification test on a wafer into a plurality of chip groups, wherein the difference of the same parameters of any two chips in each chip group is smaller than a corresponding parameter threshold; the chip sets are ordered according to the target parameters, the ordered chip sets are sequentially divided into a plurality of chip units, each chip unit comprises at least one chip set, so that the difference of the parameters of each chip is smaller in one chip unit, adjacent chip units after the ordering are also continuous, the target parameter difference between the adjacent chip units is smaller, the chip units are used for realizing high-power modules or other devices, dynamic and static uneven flow cannot be caused, and the reliability is improved.

In one possible embodiment, the subject of execution of the method may be an apparatus. For example, the method may be performed by a terminal device or a server or other processing device. The terminal device may be a User Equipment (UE), a mobile device, a User terminal, a handheld device, a computing device, or a vehicle-mounted device, and examples of some terminals are: a Mobile Phone, a tablet, a notebook, a palm, a Mobile internet device (Mobile Internetdevice, MID), a wearable device, a Virtual Reality (VR) device, an Augmented Reality (AR) device, a wireless terminal in industrial control (Industrial Control), a wireless terminal in unmanned driving (Selfdriving), a wireless terminal in teleoperation (Remote medical Surgery), a wireless terminal in Smart Grid (Smart Grid), a wireless terminal in transportation security (Transportation Safety), a wireless terminal in Smart City (Smart City), a wireless terminal in Smart Home (Smart Home), a wireless terminal in the internet of vehicles, and the like. For example, the server may be a local server or a cloud server.

In some possible implementations, the method may be implemented by the processing component invoking computer readable instructions stored in memory. In one example, the processing component includes, but is not limited to, a separate processor, or a discrete component, or a combination of a processor and a discrete component. The processor may include a controller in an electronic device having the functionality to execute instructions, and may be implemented in any suitable manner, for example, by one or more Application Specific Integrated Circuits (ASICs), digital Signal Processors (DSPs), digital Signal Processing Devices (DSPDs), programmable Logic Devices (PLDs), field Programmable Gate Arrays (FPGAs), controllers, microcontrollers, microprocessors, or other electronic elements. Within the processor, the executable instructions may be executed by hardware circuits such as logic gates, switches, application specific integrated circuits (Application Specific Integrated Circuit, ASIC), programmable logic controllers, and embedded microcontrollers.

Referring to fig. 1, fig. 1 shows a flowchart of a chip grouping method according to an embodiment of the present disclosure.

As shown in fig. 1, the method includes:

step S11, dividing each chip subjected to qualification test on a wafer into a plurality of chip sets, wherein the difference of the same parameters of any two chips in each chip set is smaller than a corresponding parameter threshold;

Step S12, sorting the chip sets according to the target parameters, and dividing the sorted chip sets into a plurality of chip units in sequence, wherein each chip unit comprises at least one chip set.

The type of the wafer and the type of each parameter are not limited in the embodiments of the present disclosure, a person skilled in the art may perform group screening on chips in various types of wafers according to actual situations and needs, and may select appropriate parameters according to actual situations and needs, for example, in a possible implementation manner, the wafer may be a MOSFET wafer with a composite semiconductor material as a substrate, for example, a silicon carbide (SiC) MOSFET wafer, where the parameters may include at least one of an on-current, a threshold current, an on-resistance, an on-voltage, a threshold voltage, a transconductance, a coss output capacitance, a temperature drift coefficient, a device leakage inductance, and the like, the target parameters may be obtained according to preset parameters, and the preset parameters may be any one of an on-current, a threshold current, an on-resistance, an on-voltage, a threshold voltage, and the like.

It should be understood that, although the foregoing description has exemplified the MOSFET as the respective parameters, it should not be construed as limiting the embodiments of the disclosure, and in other implementations, the wafer may be of other types, and accordingly, the parameters of the chip (may also be referred to as die, wafer, etc.) may be set according to actual situations and needs.

The number of the chip sets and the number of the chips in each chip set are not limited in the embodiments of the present disclosure, and may be set by those skilled in the art according to actual situations and needs.

The specific implementation manner of dividing each chip subjected to the qualification test on the wafer into the plurality of chip sets in step S11 is not limited in the embodiments of the present disclosure, and a person skilled in the art may adopt suitable means to implement the method as long as the difference between the same parameters of any two chips in each chip set is smaller than the corresponding parameter threshold, and the following exemplary description is given to possible implementation manners of implementing step S11.

Referring to fig. 2, fig. 2 shows a flowchart of a chip grouping method according to an embodiment of the disclosure.

In one possible implementation, as shown in fig. 2, step S11 divides each die on the wafer after passing the qualification test into a plurality of chip sets, which may include:

Step S111, sorting the chips according to preset parameters, continuously selecting K chips according to sorting results, and dividing the chips into a plurality of chip groups, wherein K is a positive integer;

step S112, according to the set parameter comparison sequence, sequentially determining the first parameters of the chips in each chip group, if the difference between the first parameters of any pair of chips in any one chip group is larger than a first parameter threshold corresponding to the first parameters, removing the chips corresponding to the parameter outliers in the pair of chips, sequencing and dividing the chip groups again according to the preset parameters, and executing the comparison of the first parameters until the difference between the first parameters of any two chips in each chip group is smaller than the first parameter threshold;

step S113, selecting other parameters in turn according to the set parameter comparison sequence to perform the above operation until the difference between the same parameters of any two chips in each chipset is smaller than the corresponding parameter threshold.

The embodiment of the disclosure is not limited to a specific implementation manner of obtaining parameters of each chip in a wafer, and a person skilled in the art may determine the parameters of each chip in a suitable manner according to actual situations and needs, for example, may first perform KGD (Known qualified Die) test on a cut wafer by using a test device, obtain corresponding parameters from a Map (Map) of the wafer obtained by the test, and of course, may also perform test on the required parameters in other manners to obtain the corresponding parameters.

For example, the parameters to be compared and the preset parameters may be selected in advance according to the actual situation and needs, and the preset parameters may be, for example, the on-resistances Ron of the chips may be ordered according to step S111 (that is, the chips are ordered according to the on-resistances Ron), and the ordered chips are grouped, for example, the first chip to the kth chip are grouped, the (k+1) th chip to the (K) th chip are grouped, and so on. The embodiment of the disclosure does not limit the specific size of K, and does not limit the specific size of the divided chipset number, and those skilled in the art can set the number according to actual situations and needs.

The comparison sequence of the parameters is not limited in the embodiment of the present disclosure, and a person skilled in the art can set the comparison sequence according to the actual situation and needs, and it is assumed that the parameters to be compared include the parameter 1 and the parameter 2 in addition to the preset parameters, and the set sequence is to compare the parameter 1 first and then compare the parameter 2 (which may also be random). For example, according to step S112, the embodiment of the present disclosure may determine the parameter 1 of each chip in each group of chips, obtain the largest parameter 1 and the smallest parameter 1 in the same group to obtain the parameter difference value, compare with the parameter threshold of the parameter 1, reject the pair of chips if the parameter difference value is greater than the parameter threshold, reorder and group the chips, and of course, if the largest parameter 1 and the smallest parameter 1 obtain the parameter difference value is less than the parameter threshold, directly perform comparison and screening of the next group of chips. For example, the reordering may refer to an ordering sequence obtained after removing chips that do not meet the requirement in the original ordering sequence, for example, assume that the chip ordering sequence is chip 1, chip 2, chip 3 … chip K-1, chip K, chip k+ … chip 2K, chip 2k+1, chip 2k+2, and chip 2k+3, and if the parameter difference between chip K and chip 1 in the first group of chips (chip 1 to chip K) is greater than the parameter threshold, chip 1 and chip K are removed, and comparison between the current round and the parameter threshold is stopped, and the reordering is performed, and the reordered ordering sequence is chip 2, chip 3 … chip K-1, chip k+1 … chip 2K, chip 2k+1, chip 2k+2, and chip 2k+3. Then grouping in the new ordering order, and continuing the above steps until the difference between the parameter 1 of any two chips in each chip group is smaller than the parameter threshold.

For example, after the comparison and screening of the parameters 1 of each group of chips are completed, other parameters may be sequentially selected according to the set parameter comparison sequence to perform the above operations until the difference between the same parameters of any two chips in each chipset is smaller than the corresponding parameter threshold, for example, the above comparison and screening operations may be performed on the parameters 2 until the difference between the parameters 2 of any two chips in each chipset is smaller than the corresponding parameter threshold, where the comparison manner is similar to that described in the description of the parameters 1 and will not be repeated herein.

According to the embodiment of the disclosure, each chip is sequenced according to preset parameters, K chips are continuously selected according to sequencing results, and each chip is divided into a plurality of chip groups; sequentially determining first parameters of chips in each chip set according to a set parameter comparison sequence, if the difference between the first parameters of any pair of chips in any one chip set is larger than a first parameter threshold corresponding to the first parameters, removing the chips corresponding to the parameter outliers in the pair of chips, sequencing and dividing the chip sets according to the preset parameters, and executing comparison of the first parameters until the difference between the first parameters of any two chips in each chip set is smaller than the first parameter threshold; and sequentially selecting other parameters according to the set parameter comparison sequence to perform the operations until the difference between the same parameters of any two chips in each chipset is smaller than the corresponding parameter threshold, so that the smaller difference of each parameter in each chipset can be realized, dynamic and static uneven flow can not be caused, and the reliability is improved. Of course, the above-described manner of dividing the dice that are qualified on the wafer into the plurality of die sets is exemplary, and should not be construed as limiting the embodiments of the disclosure, and in other embodiments, those skilled in the art may also divide the dice that are qualified on the wafer into the plurality of die sets in other manners.

By way of example, an outlier (also called an escape value) refers to one or more values in the data that differ significantly from other values. The embodiment of the disclosure does not limit a specific method for determining the parameter outlier, and can determine the average value and the median value of the parameters of each chip, and utilize the difference value of each parameter relative to the average value and the median value to determine the absolute value of the difference value to be the parameter outlier, or if the probability of one parameter deviating from the observed average value is less than or equal to 1/(2K), the parameter is taken as the parameter outlier, the probability can be estimated according to the distribution of the data, the standard deviation can be determined, and the parameter outlier is determined according to the standard deviation. Of course, other technical means may be employed by those skilled in the art to determine parameter outliers.

step S114, using the preset parameters as the last comparison parameters, sequentially determining the preset parameters of each chip in each chipset, if the difference between the preset parameters of any pair of chips in any one chipset is greater than the preset parameter threshold corresponding to the preset parameters, removing the chips corresponding to the parameter outliers in the pair of chips, sorting the chipsets again according to the preset parameters, dividing the chipsets, and executing the comparison of the preset parameters until the difference between the preset parameters of any two chips in each chipset is less than the preset parameter threshold.

After completing the comparison operation on other parameters to screen the chips, the embodiment of the disclosure may compare a preset parameter, such as the on-resistance Ron, as a last parameter to screen each group of chips, for example, may determine the on-resistance Ron of each chip in each group of chips, to reduce the comparison times, may obtain a parameter difference value from the largest on-resistance Ron and the smallest on-resistance Ron in the same group, and compare the parameter difference value with a parameter threshold of the on-resistance Ron, if the parameter difference value is greater than the parameter threshold, reject the pair of chips, reorder and group the chips, and, of course, if the parameter difference value obtained from the largest on-resistance Ron and the smallest on-resistance Ron is less than the parameter threshold, directly compare and screen the chips of the next group until the difference between the on-resistance Ron of any two chips in each group of chips is less than the parameter threshold. Of course, reference to the previous description of the parameter 1 is similar to that of the specific comparative screening operation, and will not be repeated here.

According to the embodiment of the disclosure, the preset parameters are used as the last comparison parameter, the preset parameters of all chips in all chip sets are sequentially determined, if the difference of the preset parameters of any pair of chips in any one chip set is larger than the preset parameter threshold corresponding to the preset parameters, the chips corresponding to the parameter outliers in the pair of chips are removed, the chip sets are sorted and divided again according to the preset parameters, and comparison of the preset parameters is executed until the difference of the preset parameters of any two chips in all chip sets is smaller than the preset parameter threshold, so that the accuracy of chip group screening can be improved, and the difference of all parameters in all chip sets is further reduced.

Of course, it should be understood that the preset parameter may also be a comparison between other arbitrary parameters for performing the packet screening of the chip, which is not limited by the embodiment of the present disclosure.

It should be noted that the chips rejected by the above comparison parameter method may be used for other purposes, and not to be discarded, for example, may be used as a single tube, and the additional rejection (or removal) method may be to add a rejection flag, where the chips with the rejection flag are not used to divide the chip units in the embodiment of the disclosure, so as to avoid increasing the risk of uneven flow when the chips are connected in parallel, thereby reducing the reliability of the power module.

step S115, processing preset parameters of each chip in each chip group to obtain target parameters, sorting each chip group according to the target parameters, if the difference between the target parameters of any two adjacent chip groups is larger than a target parameter threshold corresponding to the target parameters, removing the chip group corresponding to the parameter outlier in the pair of chip groups, sorting and dividing the chip groups according to the preset parameters, and executing comparison of the target parameters until the difference between the target parameters of each chip group is smaller than the target parameter threshold.

The specific implementation method of processing the preset parameters of each chip in each chipset in step S15 to obtain the target parameters is not limited, and a person skilled in the art can select a suitable method according to actual situations and needs to implement the method.

In a possible implementation manner, the processing the preset parameters of each chip in each chipset to obtain target parameters may include:

By taking a preset parameter as an on-resistance Ron as an example, the embodiment of the disclosure may take any one of an average value, a median, a mean square error and a variance of on-resistances Ron of chips in each chipset as the target parameter, process the on-resistances Ron of chips in each chipset to obtain a target parameter, sort the chipsets according to the target parameter, if a difference between the target parameters of any two adjacent chipsets is greater than a target parameter threshold corresponding to the target parameter, remove the chipsets corresponding to parameter outliers in the pair of chipsets, and sort and divide the chipsets and perform comparison of the target parameters again according to the on-resistances Ron until a difference between the target parameters of each chipsets is less than the target parameter threshold, so that adjacent chipsets also have continuity, and a target parameter difference between adjacent chipsets is small, so as to implement a high-power module or other devices without causing dynamic and static uneven flow, thereby improving reliability.

Of course, in the embodiment of the disclosure, each chip is sorted according to preset parameters, and K chips are continuously selected according to sorting results to divide each chip into a plurality of chip groups; sequentially determining first parameters of chips in each chip set according to a set parameter comparison sequence, if the difference between the first parameters of any pair of chips in any one chip set is larger than a first parameter threshold corresponding to the first parameters, removing the chips corresponding to the parameter outliers in the pair of chips, sequencing and dividing the chip sets according to the preset parameters, and executing comparison of the first parameters until the difference between the first parameters of any two chips in each chip set is smaller than the first parameter threshold; and sequentially selecting other parameters according to the set parameter comparison sequence to perform the operations until the difference between the same parameters of any two chips in each chip set is smaller than the corresponding parameter threshold value, and then directly sequencing the chip sets according to the target parameters, and defining chip units, for example, two chip sets are taken as one chip unit, 6 chip sets are taken as one unit, and the chip units can be continuously divided, for example, a first chip set and a second chip set in the sequencing sequence are defined as the first chip unit, and a third chip set and a fourth chip set are defined as the second chip unit, so that the parameter difference of each chip set in the chip units is reduced, dynamic and static uneven flow is avoided, and the reliability is improved.

In one possible embodiment, as shown in fig. 2, the method may further include:

and step S10, testing the MOSFET wafer, and eliminating chips which are unqualified in testing.

The embodiments of the present disclosure are not limited to the specific manner of testing, which may be KGD testing as described above, and those skilled in the art may refer to the related art to implement the qualification test of each chip (die) in a MOSFET wafer or other types of wafers.

It will be appreciated that the above-mentioned method embodiments of the present disclosure may be combined with each other to form a combined embodiment without departing from the principle logic, and are limited to the description of the present disclosure. It will be appreciated by those skilled in the art that in the above-described methods of the embodiments, the particular order of execution of the steps should be determined by their function and possible inherent logic.

The chip grouping method of the embodiments of the present disclosure is described below in detail by way of example.

Referring to fig. 3, fig. 3 shows a schematic diagram of a chip grouping method according to an embodiment of the disclosure.

In one example, as shown in fig. 3, after dicing the MOSFET wafer, KGD testing may be performed on the MOSFET wafer to obtain a wafer Map, where relevant parameters of each chip (Die) are included in the wafer Map, such as parameters of threshold current, on-resistance, and the like of the MOSFET.

In one example, as shown in fig. 3, the embodiment of the disclosure may receive parameter setting information as screening conditions (condition Cond1, condition Cond2, condition CondX), where each condition corresponds to each parameter, e.g., condition Cond1 may indicate whether a difference Δron between on-resistances of two chips is smaller than an on-resistance threshold (e.g., 1mΩ), condition Con2 may indicate whether a difference Δvth between threshold currents of two chips is smaller than a threshold current threshold (e.g., 0.3V), and so on. As shown in fig. 3, embodiments of the present disclosure may also receive the number of chipsets to divide and the number of chips per chipset.

In one example, as shown in fig. 3, the embodiments of the disclosure may sort the chips according to a preset parameter (i.e., the parameter on-resistance Ron corresponding to the condition Cond 1), and group the sorted chips into, for example, M groups.

In one example, as shown in fig. 3, the embodiment of the disclosure may sequentially determine the first parameters of each chip in each chipset according to a set parameter comparison sequence (e.g., condition Cond 2-condition CondX), if the difference between the first parameters of any pair of chips in any one chipset is greater than a first parameter threshold corresponding to the first parameter, remove the chips corresponding to the parameter outliers in the pair of chips, and reorder and divide the chipsets according to the preset parameters and perform the comparison of the first parameters until the difference between the first parameters of any two chips in each chipset is less than the first parameter threshold, and sequentially select other parameters according to the set parameter comparison sequence to perform the above operations until the difference between the same parameters of any two chips in each chipset is less than the corresponding parameter threshold.

Referring to fig. 4, fig. 4 is a schematic diagram illustrating a chip screening according to an embodiment of the disclosure.

In one example, as shown in fig. 4, assuming that the condition Con2 indicates whether the difference Δvth between the threshold currents of the two chips is smaller than the threshold current threshold (e.g., 0.3V), the disclosed embodiment may determine the threshold currents of the chips in each group, obtain the maximum threshold current and the minimum threshold current in the same group to obtain the parameter difference value for reducing the comparison times, and compare the parameter difference value with the threshold current threshold (e.g., 0.3V), and reject the pair of chips if the parameter difference value is greater than the parameter threshold (e.g., 0.3V).

In one example, as shown in fig. 3, after completing the grouping screening of the conditions Cond2 to Cond x, the embodiment of the disclosure may compare the on-resistance Ron as the last parameter to realize the screening of each group of chips, for example, the on-resistance Ron of each chip in each group of chips may be determined, the parameter difference value may be obtained by the largest on-resistance Ron and the smallest on-resistance Ron in the same group, and compared with the parameter threshold value of the on-resistance Ron, if the parameter difference value is greater than the parameter threshold value, the pair of chips are removed and reordered and grouped, and if the parameter difference value obtained by the largest on-resistance Ron and the smallest on-resistance Ron is less than the parameter threshold value, the comparison and screening of the next group of chips are directly performed until the difference value of the on-resistance Ron of any two chips in each group of chips is less than the parameter threshold value. Of course, if the erasure fails, a message may be sent to the terminal informing the technician to modify the screening conditions.

In one example, as shown in fig. 3, after the grouping of the chipsets is completed, embodiments of the present disclosure may sort the respective chipsets according to the target parameters and divide the sorted chipsets into a plurality of chip units in order, each chip unit including at least one chipset. For example, the chip units may be divided by the number of groups N, each chip unit including N chip groups, N being a positive integer.

Referring to fig. 5, fig. 5 shows a schematic diagram of chip unit division according to an embodiment of the disclosure.

In one example, as shown in fig. 5, after the grouping of the chipsets is completed, embodiments of the present disclosure may sort the respective chipsets according to the target parameters and divide the sorted chipsets into 3 chip units (modules 1-3) in order, where the remaining 3 chipsets may be combined with the next wafer to form another chip unit (module 4).

In one example, as shown in fig. 3, finally, the embodiment of the disclosure may form a new wafer Map according to the arrangement manner after the chip units are divided.

Referring to fig. 6, fig. 6 is a schematic diagram of a new wafer Map formed according to an embodiment of the disclosure.

In one example, as shown in fig. 6, the same letter or number representation may be used in the same chip unit (module), thereby improving the reliability of the device.

Referring to fig. 7, fig. 7 illustrates a method of manufacturing a power module according to an embodiment of the present disclosure.

As shown in fig. 7, the method includes:

step S21, determining a plurality of chip units by using the chip grouping method;

and S22, connecting all chips in all the chip units in parallel, and manufacturing the power module by using all the chip units.

According to the embodiment of the disclosure, each chip subjected to qualification test on the wafer is divided into a plurality of chip sets, and the difference of the same parameters of any two chips in each chip set is smaller than a corresponding parameter threshold; sorting the chip sets according to the target parameters, dividing the sorted chip sets into a plurality of chip units according to the sequence, wherein each chip unit comprises at least one chip set, connecting all chips in all the chip units in parallel, and manufacturing a power module by using all the chip units, so that the difference of all the parameters of all the chips in one chip unit is smaller, adjacent chip units after sorting also have continuity, the difference of the target parameters between the adjacent chip units is smaller, and the chip units are used for realizing high-power modules or other devices without causing dynamic and static uneven flow, thereby improving the reliability.

The specific type of the power module in the embodiments of the present disclosure is not limited, and a person skilled in the art may determine according to actual situations and needs, and in one possible implementation manner, the power module includes a half-bridge power module, a full-bridge power module, a three-phase bridge power module, and a multi-phase bridge power module.

In addition, the disclosure further provides a chip grouping device, an electronic device, a computer readable storage medium and a program, and the foregoing may be used to implement any one of the chip grouping methods provided in the disclosure, and the corresponding technical schemes and descriptions and corresponding descriptions referring to the method parts are not repeated.

Referring to fig. 8, fig. 8 shows a block diagram of a chip grouping apparatus according to an embodiment of the disclosure.

As shown in fig. 8, the apparatus includes:

the dividing module 10 is configured to divide each chip subjected to the qualification test on the wafer into a plurality of chip sets, where the difference between the same parameters of any two chips in each chip set is smaller than a corresponding parameter threshold;

The sorting module 20 is configured to sort the respective chipsets according to the target parameters, and divide the sorted chipsets into a plurality of chip units according to a sequence, where each chip unit includes at least one chipset.

In one possible implementation manner, the wafer is a MOSFET wafer based on a composite semiconductor material, the parameter includes at least one of on-current, threshold current, on-resistance, on-voltage, threshold voltage, transconductance, coss output capacitance, temperature drift coefficient, and device leakage inductance, and the target parameter is obtained according to a preset parameter, where the preset parameter is any one of on-current, threshold current, on-resistance, on-voltage, and threshold voltage.

In one possible embodiment, the apparatus further comprises:

and the testing module is used for testing the MOSFET wafer and eliminating chips which are unqualified in testing.

In some embodiments, functions or modules included in an apparatus provided by the embodiments of the present disclosure may be used to perform a method described in the foregoing method embodiments, and specific implementations thereof may refer to descriptions of the foregoing method embodiments, which are not repeated herein for brevity.

The disclosed embodiments also provide a computer readable storage medium having stored thereon computer program instructions which, when executed by a processor, implement the above-described method. The computer readable storage medium may be a non-volatile computer readable storage medium.

The embodiment of the disclosure also provides an electronic device, which comprises: a processor; a memory for storing processor-executable instructions; wherein the processor is configured to invoke the instructions stored in the memory to perform the above method.

Embodiments of the present disclosure also provide a computer program product comprising computer readable code, or a non-transitory computer readable storage medium carrying computer readable code, which when run in a processor of an electronic device, performs the above method.

The electronic device may be provided as a terminal, server or other form of device.

Referring to fig. 9, fig. 9 shows a block diagram of an electronic device according to an embodiment of the disclosure.

For example, electronic device 800 may be a mobile phone, computer, digital broadcast terminal, messaging device, game console, tablet device, medical device, exercise device, personal digital assistant, or the like.

Referring to fig. 9, an electronic device 800 may include one or more of the following components: a processing component 802, a memory 804, a power component 806, a multimedia component 808, an audio component 810, an input/output (I/O) interface 812, a sensor component 814, and a communication component 816.

The processing component 802 generally controls overall operation of the electronic device 800, such as operations associated with display, telephone calls, data communications, camera operations, and recording operations. The processing component 802 may include one or more processors 820 to execute instructions to perform all or part of the steps of the methods described above. Further, the processing component 802 can include one or more modules that facilitate interactions between the processing component 802 and other components. For example, the processing component 802 can include a multimedia module to facilitate interaction between the multimedia component 808 and the processing component 802.

The memory 804 is configured to store various types of data to support operations at the electronic device 800. Examples of such data include instructions for any application or method operating on the electronic device 800, contact data, phonebook data, messages, pictures, videos, and so forth. The memory 804 may be implemented by any type or combination of volatile or nonvolatile memory devices such as Static Random Access Memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic memory, flash memory, magnetic or optical disk.

The power supply component 806 provides power to the various components of the electronic device 800. The power components 806 may include a power management system, one or more power sources, and other components associated with generating, managing, and distributing power for the electronic device 800.

The multimedia component 808 includes a screen between the electronic device 800 and the user that provides an output interface. In some embodiments, the screen may include a Liquid Crystal Display (LCD) and a Touch Panel (TP). If the screen includes a touch panel, the screen may be implemented as a touch screen to receive input signals from a user. The touch panel includes one or more touch sensors to sense touches, swipes, and gestures on the touch panel. The touch sensor may sense not only the boundary of a touch or slide action, but also the duration and pressure associated with the touch or slide operation. In some embodiments, the multimedia component 808 includes a front camera and/or a rear camera. When the electronic device 800 is in an operational mode, such as a shooting mode or a video mode, the front camera and/or the rear camera may receive external multimedia data. Each front camera and rear camera may be a fixed optical lens system or have focal length and optical zoom capabilities.

The audio component 810 is configured to output and/or input audio signals. For example, the audio component 810 includes a Microphone (MIC) configured to receive external audio signals when the electronic device 800 is in an operational mode, such as a call mode, a recording mode, and a voice recognition mode. The received audio signals may be further stored in the memory 804 or transmitted via the communication component 816. In some embodiments, audio component 810 further includes a speaker for outputting audio signals.

The I/O interface 812 provides an interface between the processing component 802 and peripheral interface modules, which may be a keyboard, click wheel, buttons, etc. These buttons may include, but are not limited to: homepage button, volume button, start button, and lock button.

The sensor assembly 814 includes one or more sensors for providing status assessment of various aspects of the electronic device 800. For example, the sensor assembly 814 may detect an on/off state of the electronic device 800, a relative positioning of the components, such as a display and keypad of the electronic device 800, the sensor assembly 814 may also detect a change in position of the electronic device 800 or a component of the electronic device 800, the presence or absence of a user's contact with the electronic device 800, an orientation or acceleration/deceleration of the electronic device 800, and a change in temperature of the electronic device 800. The sensor assembly 814 may include a proximity sensor configured to detect the presence of nearby objects without any physical contact. The sensor assembly 814 may also include a photosensor, such as a Complementary Metal Oxide Semiconductor (CMOS) or Charge Coupled Device (CCD) image sensor, for use in imaging applications. In some embodiments, the sensor assembly 814 may also include an acceleration sensor, a gyroscopic sensor, a magnetic sensor, a pressure sensor, or a temperature sensor.

The communication component 816 is configured to facilitate communication between the electronic device 800 and other devices, either wired or wireless. The electronic device 800 may access a wireless network based on a communication standard, such as a wireless network (WiFi), a second generation mobile communication technology (2G) or a third generation mobile communication technology (3G), or a combination thereof. In one exemplary embodiment, the communication component 816 receives broadcast signals or broadcast related information from an external broadcast management system via a broadcast channel. In one exemplary embodiment, the communication component 816 further includes a Near Field Communication (NFC) module to facilitate short range communications. For example, the NFC module may be implemented based on Radio Frequency Identification (RFID) technology, infrared data association (IrDA) technology, ultra Wideband (UWB) technology, bluetooth (BT) technology, and other technologies.

In an exemplary embodiment, the electronic device 800 may be implemented by one or more Application Specific Integrated Circuits (ASICs), digital Signal Processors (DSPs), digital Signal Processing Devices (DSPDs), programmable Logic Devices (PLDs), field Programmable Gate Arrays (FPGAs), controllers, microcontrollers, microprocessors, or other electronic elements for executing the methods described above.

In an exemplary embodiment, a non-transitory computer readable storage medium is also provided, such as memory 804 including computer program instructions executable by processor 820 of electronic device 800 to perform the above-described methods.

The present disclosure may be a system, method, and/or computer program product. The computer program product may include a computer readable storage medium having computer readable program instructions embodied thereon for causing a processor to implement aspects of the present disclosure.

The computer readable storage medium may be a tangible device that can hold and store instructions for use by an instruction execution device. The computer readable storage medium may be, for example, but not limited to, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination of the foregoing. More specific examples (a non-exhaustive list) of the computer-readable storage medium would include the following: portable computer disks, hard disks, random Access Memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), static Random Access Memory (SRAM), portable compact disk read-only memory (CD-ROM), digital Versatile Disks (DVD), memory sticks, floppy disks, mechanical coding devices, punch cards or in-groove structures such as punch cards or grooves having instructions stored thereon, and any suitable combination of the foregoing. Computer-readable storage media, as used herein, are not to be construed as transitory signals per se, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through waveguides or other transmission media (e.g., optical pulses through fiber optic cables), or electrical signals transmitted through wires.

The computer readable program instructions described herein may be downloaded from a computer readable storage medium to a respective computing/processing device or to an external computer or external storage device over a network, such as the internet, a local area network, a wide area network, and/or a wireless network. The network may include copper transmission cables, fiber optic transmissions, wireless transmissions, routers, firewalls, switches, gateway computers and/or edge servers. The network interface card or network interface in each computing/processing device receives computer readable program instructions from the network and forwards the computer readable program instructions for storage in a computer readable storage medium in the respective computing/processing device.

Computer program instructions for performing the operations of the present disclosure can be assembly instructions, instruction Set Architecture (ISA) instructions, machine-related instructions, microcode, firmware instructions, state setting data, or source or object code written in any combination of one or more programming languages, including an object oriented programming language such as Smalltalk, c++ or the like and conventional procedural programming languages, such as the "C" programming language or similar programming languages. The computer readable program instructions may be executed entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer or entirely on the remote computer or server. In the case of a remote computer, the remote computer may be connected to the user's computer through any kind of network, including a Local Area Network (LAN) or a Wide Area Network (WAN), or may be connected to an external computer (for example, through the Internet using an Internet service provider). In some embodiments, aspects of the present disclosure are implemented by personalizing electronic circuitry, such as programmable logic circuitry, field Programmable Gate Arrays (FPGAs), or Programmable Logic Arrays (PLAs), with state information of computer readable program instructions, which can execute the computer readable program instructions.

Various aspects of the present disclosure are described herein with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems) and computer program products according to embodiments of the disclosure. It will be understood that each block of the flowchart illustrations and/or block diagrams, and combinations of blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer-readable program instructions.

These computer readable program instructions may be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions/acts specified in the flowchart and/or block diagram block or blocks. These computer readable program instructions may also be stored in a computer readable storage medium that can direct a computer, programmable data processing apparatus, and/or other devices to function in a particular manner, such that the computer readable medium having the instructions stored therein includes an article of manufacture including instructions which implement the function/act specified in the flowchart and/or block diagram block or blocks.

The computer readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other devices to cause a series of operational steps to be performed on the computer, other programmable apparatus or other devices to produce a computer implemented process such that the instructions which execute on the computer, other programmable apparatus or other devices implement the functions/acts specified in the flowchart and/or block diagram block or blocks.

The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods and computer program products according to various embodiments of the present disclosure. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of instructions, which comprises one or more executable instructions for implementing the specified logical function(s). In some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.

The computer program product may be realized in particular by means of hardware, software or a combination thereof. In an alternative embodiment, the computer program product is embodied as a computer storage medium, and in another alternative embodiment, the computer program product is embodied as a software product, such as a software development kit (Software Development Kit, SDK), or the like.

The foregoing description of the embodiments of the present disclosure has been presented for purposes of illustration and description, and is not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the various embodiments described. The terminology used herein was chosen in order to best explain the principles of the embodiments, the practical application, or the improvement of technology in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.

Claims

1. A method of chip grouping, the method comprising:

2. The method of claim 1, wherein the dividing the dice that are eligible for testing on the wafer into a plurality of chipsets comprises:

3. The method of claim 2, wherein the dividing the dice that are eligible for testing on the wafer into a plurality of chipsets comprises:

4. A method according to claim 2 or 3, wherein the dividing the dice passing the qualification test on the wafer into a plurality of chipsets comprises:

5. The method of claim 4, wherein the processing the preset parameters of each chip in each chipset to obtain the target parameters includes:

6. The method of claim 1, wherein the wafer is a composite semiconductor material based MOSFET wafer, the parameter comprises at least one of on-current, threshold current, on-resistance, on-voltage, threshold voltage, transconductance, coss output capacitance, temperature drift coefficient, and device leakage inductance, the target parameter is obtained according to a predetermined parameter, the predetermined parameter is any one of on-current, threshold current, on-resistance, on-voltage, and threshold voltage,

wherein the method further comprises:

7. A method of manufacturing a power module, the method comprising:

determining a plurality of chip units using the chip grouping method according to any one of claims 1 to 6;

8. The method of manufacturing of claim 7, wherein the power modules include half-bridge power modules, full-bridge power modules, three-phase bridge power modules, and multi-phase bridge power modules.

9. A power module, characterized in that the power module is manufactured by the manufacturing method of a power module according to claim 7 or 8.

10. A power device comprising the power module of claim 9.

11. A chip grouping apparatus, the apparatus comprising:

12. An electronic device, comprising:

a processor;

a memory for storing processor-executable instructions;

wherein the processor is configured to invoke the instructions stored in the memory to perform the method of any of claims 1 to 6.

13. A computer readable storage medium having stored thereon computer program instructions, which when executed by a processor, implement the method of any of claims 1 to 6.