CN116467230A

CN116467230A - Computer module

Info

Publication number: CN116467230A
Application number: CN202210030523.5A
Authority: CN
Inventors: 包云兵; 冯官成; 亓延军; 刘洪辉
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2022-01-12
Filing date: 2022-01-12
Publication date: 2023-07-21

Abstract

A computer module relates to the technical field of communication. The computer module may be considered a minimized computer system. In the present application, the computer module may include a processor and a golden finger, wherein: the processor is operable to perform information processing of the computer module, the processor including a plurality of first signal interfaces. The golden finger can be a plurality of golden fingers, each first signal interface can be connected with at least one golden finger, and the connected first signal interfaces and golden fingers are used for transmitting the same signals, so that the golden fingers are used as external ports of the computer module, and the connection between the processor and external equipment is realized. The computer module can be easily subjected to secondary development so as to obtain a server or a mainboard applicable to the computer, thereby saving development time and cost.

Description

Computer module

Technical Field

The present application relates to the field of communications technologies, and in particular, to a computer module.

Background

The processor is used as the operation and control core of the computer system and is the final execution unit for information processing and program running. Under the development strategy of processor localization, more and more manufacturers are pushing out respective localization processors. Meanwhile, more and more computer complete machine manufacturers produce computer complete machine products based on the domestic processors.

However, the existing domestic processors have no unified design standard, which results in a large difference between the processors provided by each manufacturer. The computer complete machine manufacturer needs to develop and design the carrier board aiming at different processors, and has long development period, high risk and higher cost.

Therefore, how to solve the problems of large processor variability, difficulty in secondary development, etc. has become a direction of further research by those skilled in the art.

Disclosure of Invention

The application provides a computer module, so that the computer module provided with different processors can be matched with the same carrier plate, and the computer module is easy to develop secondarily.

In a first aspect, the present application provides a computer module comprising a processor and a golden finger. The processor is used as an operation and control core of the computer module and can be used for information processing and program running. The processor may include a plurality of first signal interfaces. The plurality of first signal interfaces may include a serial display interface, a serial network interface, a serial ATA interface, a high-speed serial computer expansion bus standard interface, a universal serial bus interface, a clock output interface, an I2C interface, a serial peripheral interface, a universal asynchronous receiver-transmitter interface, a system control interface, an input or output interface, a power input interface, and a serial peripheral interface memory controller interface. In this application, the number of golden fingers is also plural, each first signal interface mentioned above may be connected with at least one golden finger, and the connected first signal interfaces and golden fingers may be used to transmit the same signal. By adopting the computer module, the golden finger can be used as an external port of the computer module, and can be used for realizing a connection port for connecting the computer module with other external equipment, so that signal connection between the computer module and the external equipment is realized. Based on the design, the computer modules provided with different processors can be matched with the same carrier plate, so that secondary development of the computer modules is facilitated, the development cost is reduced, and a main board suitable for a server or a computer is obtained.

In some possible implementations of the application, the computer module may further include a circuit module in signal connection with the processor. The circuit module may be, but is not limited to being, one or more of a double rate synchronous dynamic random access memory circuit module, a clock circuit module, a memory circuit module, and a power circuit module.

In some possible implementations of the present application, the computer module may further include a carrier board, and the computer module may be signal-connected to the carrier board to perform its task. When the connection between the computer module and the carrier plate is specifically realized, a golden finger connector is further arranged on the carrier plate, the golden finger connector is in signal connection with the carrier plate, and the golden finger of the computer module can be inserted into the golden finger connector, so that the carrier plate can be connected with the signal of the processor through the golden finger connector.

The golden finger connector can be provided with a plurality of second signal interfaces. The plurality of second signal interfaces are connected with the plurality of golden fingers in a one-to-one correspondence manner, and the connected first signal interfaces and golden fingers can be used for transmitting the same signals.

In addition, the golden finger connector is provided with a connecting port, and the second signal interface is arranged in the connecting port. It will be appreciated that the opening orientation of the connection port has an important effect on the plugging direction of the computer module with the golden finger connector. In one possible implementation manner of the present application, the opening direction of the connection port may be perpendicular to the board surface of the carrier board; or the opening direction of the connecting port is parallel to the plate surface of the carrier plate; or the opening direction of the connecting port and the plate surface of the carrier plate form a set angle alpha, wherein 0 degrees < alpha <90 degrees. Therefore, when the computer module is plugged with the golden finger connector, the computer module can be plugged with the carrier plate along the direction perpendicular to the plate surface of the carrier plate, or along the direction parallel to the plate surface of the carrier plate, or along the direction forming a set angle (0 degrees < alpha <90 degrees) with the plate surface of the carrier plate. Therefore, the limitation of the setting space of the computer system on the connection of the computer module and the carrier plate can be effectively reduced, and the expansion of the application scene of the computer system is facilitated.

In one possible implementation manner of the present application, the computer module may further include a storage module, a first switch, a second switch, a third switch, and a security check hardware component, where the third switch and the security check hardware component are disposed on the carrier board. One first signal interface of the processor is an SFC interface, one first signal interface is an SPI, the SFC interface accesses the memory module through the first switch, and the SPI is connected with SPI peripherals through the second switch and the third switch; or the safety verification hardware component is connected with the memory module through the first switch, the second switch and the third switch.

In specific implementation, the first switch may include a first source interface, a second source interface, a selection interface, and a target interface; the second change-over switch can comprise a first source end interface, a second source end interface, a selection interface and a target end interface; the third transfer switch may include a first source interface, a second source interface, a selection interface, and a target interface;

the SFC interface is connected with a first source end interface of the first change-over switch, the SPI is connected with a first source end interface of the second change-over switch, a second source end interface of the first change-over switch is connected with a second source end interface of the second change-over switch, and a target end interface of the first change-over switch is connected with the memory module; the target end interface of the second change-over switch is connected with the target end interface of the third change-over switch; the first source end interface of the third change-over switch is connected with the SPI peripheral equipment, and the second source end interface of the third change-over switch is connected with the safety verification hardware component;

the selection interface of the first switch, the selection interface of the second switch and the selection interface of the third switch are used for receiving selection signals output by the safety verification hardware component; the selection signal is used for controlling the switching of the conducting states of the first source end interface and the second source end interface of the first change-over switch and the target end interface, the switching of the conducting states of the first source end interface and the second source end interface of the second change-over switch and the target end interface, and the switching of the conducting states of the first source end interface and the second source end interface of the third change-over switch and the target end interface.

In one possible implementation manner of the present application, when the selection signal is in the first state, the first source end interface of the first switch is conducted with the target end interface, the first source end interface of the second switch is conducted with the target end interface, and the first source end interface of the third switch is conducted with the target end interface; when the selection signal is in the second state, the second source end interface of the first change-over switch is conducted with the target end interface, the second source end opening of the second change-over switch is conducted with the target end interface, and the second source end opening of the third change-over switch is conducted with the target end interface.

By adopting the computer module provided by the application, the on states of the first change-over switch, the second change-over switch and the third change-over switch can be controlled through the change of the state of the selection signal, so that the processor can be connected with SPI (serial peripheral interface) through the SPI of the processor, and the safety verification hardware component can also carry out safety verification on the storage module through the SPI of the processor, thereby avoiding that the SFC interface used for connecting the safety verification hardware component and the storage module is independently arranged in the computer module, and being beneficial to reducing the requirements on the number of signal interfaces of the golden finger and the golden finger connector so as to enlarge the application range of the computer module.

Drawings

FIG. 1 is a block diagram of a computer module provided in one embodiment of the present application;

fig. 2 is a schematic structural diagram of a computer system according to another embodiment of the present application.

Reference numerals:

1-a computer module; a 101-processor; 1011-a first signal interface; 102-golden finger; 103-a memory module;

104-memory; a 105-DDR SDRAM circuit module; 106-a clock circuit module; 107-a memory circuit module;

108-a power circuit module; 4-a security check hardware component; SW 1-a first change-over switch;

SW 2-a second switch; SW 3-third switch;

s1, S2, S3, S1', S2', S1', S2' -source interfaces; D. d', D "-target end interface;

s3, S3', S3 "-SEL interface; 5-SPI peripheral.

Detailed Description

For the purpose of making the objects, technical solutions and advantages of the present application more apparent, the present application will be described in further detail with reference to the accompanying drawings. In the description of the present application, "at least one" means one or more, wherein a plurality means two or more. In view of this, the term "plurality" may also be understood as "at least two" in embodiments of the present invention. "and/or", describes an association relationship of an association object, and indicates that there may be three relationships, for example, a and/or B, and may indicate: a exists alone, A and B exist together, and B exists alone. The character "/", unless otherwise specified, generally indicates that the associated object is an "or" relationship. In addition, it should be understood that in the description of this application, the words "first," "second," and the like are used merely for distinguishing between the descriptions and not for indicating or implying any relative importance or order.

Reference in the specification to "one embodiment" or "some embodiments" or the like means that a particular feature, structure, or characteristic described in connection with the embodiment is included in one or more embodiments of the application. Thus, appearances of the phrases "in one embodiment," "in some embodiments," "in other embodiments," and the like in the specification are not necessarily all referring to the same embodiment, but mean "one or more but not all embodiments" unless expressly specified otherwise. The terms "comprising," "including," "having," and variations thereof mean "including but not limited to," unless expressly specified otherwise.

Computer modules refer to software systems, hardware systems, and network systems for database management. Database systems require large capacity hosts to store and run operating systems, database management system programs, applications, and databases, directories, system buffers, etc., while secondary stores require large capacity direct access devices, all of which can be implemented by computer modules. In this application, the specific arrangement of the computer module is not limited, and the computer module may be integrated on a circuit board, which may be used for development of a motherboard of a communication device such as a server and a computer.

The processor, generally referred to as a central processing unit (central processing unit, CPU), is a final execution unit for information processing and program running, and serves as an operation and control core of the computer module. Since the generation of the CPU, great development is made on the aspects of logic structure, operation efficiency and functional extension.

Currently, processors on the market are produced by different factories, and there is no unified standard for the production of the processors among the factories. This results in the need of secondary development design for the characteristics (such as the functions to be implemented) of each processor, which results in problems of long development cycle, high development risk, and high development cost.

In view of this, the application provides a computer module to make the computer module that is provided with different processors can carry out the adaptation with same carrier plate, thereby be favorable to realizing the secondary development of computer module, with the development cost that reduces, and be convenient for obtain the mainboard of communication equipment such as server and computer. Computer modules, also referred to as core boards, computer modules, etc., may generally include a processor or be a microcontroller, memory module, power management module, etc. In addition, the computer module is also provided with an operating system such as Linux, WINCE, QNX, etc., which constitutes a minimized computer system.

Referring to fig. 1, fig. 1 is a schematic block diagram of a computer module 1 according to one possible embodiment of the present application. The computer module 1 includes a processor 101 and a golden finger 102. The processor 101 may be used as an operation and control core of the computer module 1 for performing information processing or program running, etc., so as to implement the functions of the computer module 1. The processor 101 has a plurality of first signal interfaces 1011, and the specific arrangement of the processor 101 is not limited in this application.

The golden finger 102 is used as an external port of the computer module 1, and can be used for realizing a connection port for connecting the computer module 1 with other external devices, so as to realize signal connection between the computer module 1 and the external devices. The number of golden fingers 102 is plural, each golden finger 102 is used as a signal interface, and each first signal interface 1011 of the processor 101 can be connected with at least one golden finger 102. It will be appreciated that the first signal interface 1011 and the golden finger 102 connected may be used to transmit the same signal, and that each cable used to transmit the signal is connected to one golden finger 102. For example, in order to transmit the signal, two cables need to be led out from one first signal interface 1011, and the two cables are respectively connected to one gold finger 102, so that the first signal interface 1011 is connected to two gold fingers 102. Thus, the processor 101 of the computer module 1 can be in signal connection with external equipment through the golden finger 102.

With continued reference to fig. 1, in one possible embodiment of the present application, the first signal interface 1011 may be, but is not limited to, a serial display interface (display serial interface, DSI), a serial network interface (serial gigabit media independent interface, SGMII), a serial ATA (SATA) interface, a high-speed serial computer expansion bus standard (peripheral component interconnect express, PCIE) interface, a universal serial bus (universal serial bus, USB) interface, a clock output interface, an I2C interface, a serial peripheral interface (serial peripheralinterface, SPI), a universal asynchronous receiver/transmitter (universal asynchronous receiver/transmitter, UART) interface, a system control interface, a general-purpose input/output (GPIO) interface, a power input interface, or a serial peripheral interface memory controller (SPI FLASH controller, SFC) interface, or the like.

The DSI is used for displaying output, and can support 2 paths of DSI output, HDMI, DVI, DP, LVDS protocols and the like. The SGMII may support a 2-way network interface that may support connections for electrical ports that may support 10/100/1000M rates and optical modules that may support up to 1/10G rates. The SATA interface can support a 2-way SATA interface, and support an external hard disk or an optical drive. The PCIE interface may support 12Lanes PCIE, supporting flexible splitting manners, for example: x8+4x1, 2x4+4x1, 4xx2+4x1, etc., wherein 12lanes represent a total of 12 PCIE lanes. PCIE interfaces may operate in different channel modes, such as single channel (X1), 4 channel (X4), 8 channel (X8), 16 channel (X16), etc. The maximum support is 12 channels, and any combination of the above channels can be made.

The USB interface may support, but is not limited to, 2-way USB2.0 and 1-way USB3.0 signals. The clock output interface may be used to support 2-way 100M clock output. The I2C interface may support a 4-way I2C interface. The SPI interface can support a 1-path SPI interface, and supports security check of a basic input output system (basic input output system, BIOS) and control of SPI peripherals. The UART interface may support a 1-way UART interface. The system control interface may support expansion of the embedded controller (embedded controller, EC), and may be specifically used to support sleep management and peripheral management of the computer module 1 by the EC, where the EC is generally used for a motherboard of a desktop computer, a notebook computer, or the like. The GPIO interface has a plurality of GPIO pins, and each GPIO pin may be used as a general-purpose input (GPI), a general-purpose output (GPO), or a general-purpose input or output according to a specific application scenario, so as to implement management of peripheral devices. The SFC interface may scan the integrity of all protected system files.

As can be appreciated from the foregoing description of the computer module 1, the first signal interface 1011 and the golden finger 102 that are connected may be used to transmit the same signal, so that each golden finger 102 may be set according to a specific setting manner of the first signal interface 1011, which is not described herein.

With continued reference to fig. 1, the computer module 1 of the present application may further include a memory module 103 in addition to the above-described structure, where the memory module 103 is in signal connection with the processor 101. The storage module 103 may be, for example, a Flash memory, which is a type of memory device, and is a non-volatile memory, and the storage module 103 may include a basic input output system (basic input output system, BIOS), which may be used to perform self-detection (power on self test) on a computer component when the computer system is started, and load a boot program or store the boot program in a main operating system.

As is known from the foregoing, the memory module 103 is generally not easy to lose due to power failure. The memory 104 in the computer module 1 is lost due to power failure, and the memory 104 is connected to a memory controller in the processor 101 and is used as a buffer space for programs or data during the running of the system or software (the memory 104 is, for example, a memory bank in a computer).

It should be noted that the specific connection medium among the processor 101, the golden finger 102 and the storage module 103 is not limited in the embodiments of the present application. In the embodiment shown in fig. 1, the processor 101, the golden finger 102 and the memory module 103 are connected by a bus. The bus may be illustratively classified as an address bus, a data bus, a control bus, or the like. For ease of illustration, only one line is shown in FIG. 1, but not only one bus or one type of bus.

In addition, the computer module 1 further includes a circuit module, which may be in signal connection with the processor 101, and the circuit module may be, but is not limited to, one or more of a double data rate SDRAM (ddr SDRAM) circuit module 105, a clock circuit module 106, a memory circuit module 107, or a power supply circuit module 108. The storage circuit module 107 may be, for example, a solid state drive (solid state drive, SSD) storage circuit module. The power circuit module 108 may be connected to a power input interface of the golden finger 102. In the embodiment of the present application, the specific connection manner between each circuit module and the processor 101 is not limited, but the connection manner shown in the drawings is only illustrative and not limited thereto.

The computer module 1 usually requires a carrier board (also called motherboard, motherboard) to operate, and the carrier board includes an application interface, bus logic, and the like. The golden finger 102 on the computer module 1 is connected with the application interface on the carrier plate, and can be used for realizing the signal connection between the processor 101 in the computer module 1 and the carrier plate. In addition, a plurality of application interfaces may be disposed on the same carrier board, so that a plurality of processors 101 may be plugged into one application interface through the golden finger 102 correspondingly, so as to realize signal connection between each processor 101 and the carrier board 2. On the basis, signal transmission among a plurality of processors 101 can be realized by reasonably designing the carrier plate 2.

As can be seen from the above connection of the processor 101 to the carrier plate 2, the application interface is an important structure for realizing signal connection between the two. There are many ways to set up the application interface, and there are many ways to plug in the golden finger 102 and the application interface. However, in some situations, the connection direction between the golden finger 102 and the application interface is required to be flexible due to the limitation of the setting space of the computer module 1.

As a possible implementation manner, the computer module may further include a carrier board and a golden finger connector, where the golden finger connector is in signal connection with the carrier board as an application interface of the carrier board. The processor 101 in any of the above embodiments may be plugged into the golden finger connector through the golden finger 102, so as to realize signal connection between the processor 101 and the carrier board.

The golden finger connector may include a plurality of second signal interfaces, and the second signal interfaces may be connected to the golden fingers 102 (refer to fig. 1) in a one-to-one correspondence. It will be appreciated that the connected second signal interface and gold finger 102 may be used to transmit the same signal.

In addition, in the embodiment of the present application, the specific structure of the golden finger connector is not limited, and the golden finger connector has a connection port, and the second signal interface is disposed at the connection port. In the present application, the golden finger connector may provide at least one surface to provide a connection port for the carrier plate, for example, the golden finger connector may be located on a first surface of a peripheral side of the connection port, and a second surface located on a back side of the connection port is connected to the carrier plate respectively. The first surface and the second surface of the golden finger connector can be contacted with any plate surface of the carrier plate in a direct contact or indirect contact mode so as to realize signal connection between the first surface and the second surface. In addition, a clamping part can be further arranged at the end part of the golden finger connector, which is far away from the connecting port, and the clamping part can be clamped and fixed with the carrier plate at the edge of the carrier plate, and the fixing mode can be, but is not limited to, threaded connection, bonding or welding. Therefore, the contact between the second surface of the golden finger connector and the end surface of the carrier plate is realized, and the signal connection between the second surface of the golden finger connector and the end surface of the carrier plate is realized. Thus, after the golden finger connector is connected with the carrier plate, the opening direction of the connecting port of the golden finger connector can be perpendicular to the plate surface of the carrier plate, or parallel to the plate surface of the carrier plate, or form a set angle alpha with the plate surface of the carrier plate, wherein 0 degree < alpha <90 degrees.

When the golden finger 102 is plugged with the golden finger connector, the golden finger 102 can be plugged with the carrier plate along the direction perpendicular to the surface of the carrier plate, or along the direction parallel to the surface of the carrier plate, or along the direction forming a set angle (0 ° < α <90 °) with the surface of the carrier plate. The limitation of the setting space of the computer module on the connection between the golden finger 102 and the carrier plate is reduced, so that the expansion of the application scene of the computer module is facilitated.

In general, for example, in the computer module 1 shown in fig. 1, the number of the first signal interfaces 1011 and the golden fingers 102 of the processor 101 is limited, so that only a limited variety of signals can be transmitted, thereby realizing a limited function. The same signal interface can be used for realizing transmission of different signals through switching the connection relation, namely multiplexing of the signal interfaces, so that corresponding functions are realized in different application scenes, and the problems can be effectively solved.

As can be seen from the foregoing description of the computer module 1, some of the first signal interfaces 1011, such as DSI, SGMII, SATA interface, PCIE interface, USB interface, of the processor 101 of the computer module 1 are high-speed signal interfaces. The high-speed signal interfaces can be switched by adjusting the multiplexing relation of serializer/deserializer (Serdes), for example, the SATA interface can be configured as a PCIE interface through Serdes, so that the SATA interface can realize the function of the PCIE interface. The switching of functions between the high-speed signal interfaces by adjustment of the Serdes multiplexing relationship is a well-established technique in the art, and therefore will not be described in detail here.

In addition, the first signal interface 1011 for implementing signal connection between the processor 101 and the golden finger 102 includes some low-speed signal interfaces, such as SPI and SFC interfaces, in addition to the above-mentioned high-speed signal interfaces, and multiplexing between the low-speed signal interfaces may further implement expansion of functions of the computer module 1. Next, multiplexing between low-speed signal interfaces will be described using an SPI function switching scheme as an example.

Referring to fig. 2, fig. 2 is a schematic structural diagram of a computer module according to one possible embodiment of the present application, in which the principle of function switching between an SFC interface and an SPI is illustrated. In the computer module, a first switch SW1, a second switch SW2, a third switch SW3 and a security verification hardware component 4 (which may also be referred to as a security card) are provided, and the third switch SW3 and the security verification hardware component 4 are provided on the carrier board 2. The first switching switch SW1 includes a source terminal interface S1, a source terminal interface S2, a Select (SEL) interface S3 and a destination terminal interface D. The second changeover switch SW2 includes a source terminal interface S1', a source terminal interface S2', a SEL interface S3 'and a target terminal interface D'. The third changeover switch SW3 includes a source terminal interface S1 ", a source terminal interface S2", a SEL interface S3 "and a target terminal interface D".

The SPI interface of the CPU is connected to the source interface S1 of the first switch SW1, the SFC interface of the CPU is connected to the source interface S1 'of the second switch SW2, and the source interface S2 of the first switch SW1 is connected to the source interface S2' of the second switch SW 2.

With continued reference to fig. 2, the target terminal interface D of the first switch SW1 is connected to the storage module 103. In addition, the target port interface D' of the second changeover switch SW2 is connected with the target port interface d″ of the SW 3; the source interface S1 "of the third switch SW3 is connected to the SPI peripheral device 5 and the source interface S2" of the third switch SW3 is connected to the security check hardware component 4.

The SEL interface S3 of the first switch SW1, the SEL interface S3' of the second switch SW2 and the SEL interface S3″ of the third switch SW3 may be used to receive the SEL signal output from the security check hardware component 4. The SEL signal may be used to control the switching of the on states of the source port S1 and the source port S2 of the first switch SW1 and the target port D, the switching of the on states of the source port S1' and the source port S2' of the second switch SW2 and the target port D ', and the switching of the on states of the source port S1″ and the source port S2″ of the third switch SW3 and the target port d″.

In specific implementation, referring to fig. 2, in a default state (the default state of the SEL signal is referred to as a first state of the SEL signal in this application), the source port S1 and the destination port D of the first switch SW1 are turned on, the source port S1 'and the destination port D' of the second switch SW2 are turned on, and the source port S1″ and the destination port d″ of the third switch SW3 are turned on. At this time, the CPU can normally access the memory module 103 through the SFC interface, and the SPI interface of the processor 101 is connected to the SPI peripheral 5 through SW2 and SW 3.

When the state of the SEL signal output by the security check hardware component 4 changes (the state of the SEL signal at this time is denoted as the second state of the SEL signal, and the second state is different from the first state), the source port S2 and the destination port D of the first switch SW1 are turned on, the source port S2 'and the destination port D' of the second switch SW2 are turned on, and the source port S2″ and the destination port d″ of the third switch SW3 are turned on. At this time, the security check hardware component 4 may be connected to the memory module 103 through the third switch SW3, the second switch SW2 and the first switch SW1 in sequence, so as to implement the security check operation on the memory module 103. After the security check of the memory module 103 is completed, the SEL signal state output by the security check hardware component 4 may be restored to a default state (first state) for realizing the normal functions of the computer module.

In the computer module of the embodiment of the present application, the on states of the first switch SW1, the second switch SW2 and the third switch SW3 are controlled by the SEL signal, so that the processor 101 is connected to the SPI peripheral 5 through its own SPI; the safety verification hardware component 4 can also carry out safety verification on the storage module 103 through the SPI of the processor 101, so that an SFC interface for connecting the safety verification hardware component 4 with the storage module 103 is prevented from being independently arranged in the computer module, and the requirements on the number of signal interfaces of the golden finger 102 and the golden finger connector 3 are favorably reduced, so that the application range of the computer module is enlarged.

It is to be understood that the multiplexing of SPI functions described above is just one exemplary illustration given in this application. On the basis, the functional multiplexing of other low-speed signal interfaces can be realized through reasonable design, and the functional multiplexing is not listed here, but all the functional multiplexing is understood to fall within the protection scope of the application.

It will be appreciated by those skilled in the art that embodiments of the present application may be provided as a method, system, or computer program product. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.

The present application is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems) and computer program products according to the application. It will be understood that each flow and/or block of the flowchart illustrations and/or block diagrams, and combinations of flows and/or blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present application without departing from the scope of the application. Thus, if such modifications and variations of the present application fall within the scope of the claims and the equivalents thereof, the present application is intended to cover such modifications and variations.

Claims

1. A computer module comprising a processor and a golden finger, wherein:

the processor is used for processing information of the computer module, and comprises a plurality of first signal interfaces;

the plurality of first signal interfaces comprise a serial display interface, a serial network interface, a serial ATA interface, a high-speed serial computer expansion bus standard interface, a universal serial bus interface, a clock output interface, an I2C interface, a serial peripheral interface, a universal asynchronous receiving and transmitting device interface, a system control interface, an input or output interface, a power input interface and a serial peripheral interface storage controller interface;

the golden finger is a plurality of, each first signal interface is connected with at least one golden finger, and the connected first signal interfaces and golden fingers are used for transmitting the same signals.

2. The computer module of claim 1, further comprising a circuit module in signal connection with the processor.

3. The computer module of claim 2, wherein the circuit module comprises one or more of a double rate synchronous dynamic random access memory circuit module, a clock circuit module, a memory circuit module, and a power circuit module.

4. A computer module according to any one of claims 1 to 3, further comprising a carrier plate in signal connection with the processor via a golden finger connector; the golden finger is inserted into the golden finger connector.

5. The computer module of claim 4, wherein the golden finger connector comprises a plurality of second signal interfaces, the plurality of second signal interfaces are connected with the plurality of golden fingers in a one-to-one correspondence, and the connected second signal interfaces and the golden finger signals are used for transmitting the same signals.

6. The computer module of claim 4 or 5, wherein the golden finger connector has a connection port, an opening direction of the connection port being perpendicular to the board surface of the carrier board; or the opening direction of the connecting port is parallel to the plate surface of the carrier plate; or the opening direction of the connection port and the plate surface of the carrier plate form a set angle alpha, wherein 0 degrees < alpha <90 degrees.

7. The computer module of any of claims 4-6, further comprising a memory module, a first switch, a second switch, a third switch, and a security check hardware component, the third switch and the security check hardware component disposed on the carrier plate;

one of the first signal interfaces of the processor is an SFC interface, one of the first signal interfaces is an SPI, the SFC interface accesses the memory module through the first switch, and the SPI is connected with SPI peripherals through the second switch and the third switch; or, the safety verification hardware component is connected with the memory module through the first switch, the second switch and the third switch.

8. The computer module of claim 7, wherein the first switch comprises a first source interface, a second source interface, a selection interface, and a destination interface; the second change-over switch comprises a first source end interface, a second source end interface, a selection interface and a target end interface; the third change-over switch comprises a first source end interface, a second source end interface, a selection interface and a target end interface;

the SFC interface is connected with a first source end interface of the first change-over switch, the SPI is connected with a first source end interface of the second change-over switch, a second source end interface of the first change-over switch is connected with a second source end interface of the second change-over switch, and a target end interface of the first change-over switch is connected with the memory module; the target end interface of the second change-over switch is connected with the target end interface of the third change-over switch; the first source end interface of the third change-over switch is connected with the SPI peripheral, and the second source end interface of the third change-over switch is connected with the safety verification hardware component;

9. The computer module of claim 8, wherein when the select signal is in the first state, the first source interface of the first switch is in communication with the target interface, the first source interface of the second switch is in communication with the target interface, and the first source interface of the third switch is in communication with the target interface;

when the selection signal is in a second state, the second source end interface of the first change-over switch is communicated with the target end interface, the second source end opening of the second change-over switch is communicated with the target end interface, and the second source end opening of the third change-over switch is communicated with the target end interface.