CN116466784A - MOS bias circuits, analog circuits, digital circuits and chips to improve circuit withstand voltage - Google Patents

Abstract

The present invention provides a MOS bias circuit, an analog circuit, a digital circuit and a chip for increasing circuit withstand voltage. The MOS bias circuit for increasing circuit withstand voltage includes a start-up branch, a PMOS bias voltage generating branch, and an NMOS bias voltage generating branch. The start-up branch, the PMOS bias voltage generating branch, and the NMOS bias voltage generating branch are connected in parallel to a power supply terminal and a ground terminal; the PMOS bias voltage generating branch includes a first bias generating module having at least two PMOS transistors connected in series, and the PMOS transistors are arranged in a diode-connected manner; The NMOS bias voltage generation branch includes a second bias generation module with at least two NMOS transistors connected in series, and the NMOS transistors are arranged in a diode connection manner. The analog circuit employs the MOS bias circuit. The digital circuit employs the MOS bias circuit. The chip employs the analog circuit or the digital circuit. The MOS bias circuit of the present invention can generate a stable output voltage within a certain fluctuating power supply voltage range and improve the withstand voltage performance of the circuit.

Description

MOS bias circuits, analog circuits, digital circuits and chips to improve circuit withstand voltage

technical field

The present invention relates to the technical field of analog and digital hybrid circuit design, in particular, to a MOS bias circuit for boosting circuit withstand voltage, to an analog circuit based on MOS tube withstand voltage protection using the MOS bias circuit for boosting circuit withstand voltage, to a digital circuit based on MOS tube withstand voltage protection using the MOS bias circuit for boosting circuit withstand voltage, and to a chip using the analog circuit or digital circuit.

Background technique

At present, the demand for SoC (System on Chip, System on Chip) computing power and energy efficiency ratio improvement has prompted the use of more low-voltage devices such as 0.8V and 1.8V in advanced processes. Modules such as IOs and ADCs designed with the above-mentioned devices are difficult to directly meet applications in high-voltage power domains such as 3.3V. In addition, power chips are often damaged by EOS due to pre-stage surges or high-voltage mis-insertion. It is urgent to improve IC reliability, or there may be risks of similar high-voltage operation in some protection modules. Therefore, it is necessary to improve the overall withstand voltage of the circuit, specifically to solve various withstand voltage problems including MOS tubes, such as the withstand voltage between Source-Drain, the withstand voltage between Gate and Source/Drain/Body, etc.

In the existing technical solutions, it mainly relies on the structural replacement of some circuits, such as the use of Cascode circuit modules for operational amplifiers, or the use of higher withstand voltage LDMOS in the process, such as 6V, 12V, 30V, 40V and other high-voltage tubes. However, if the Casecode architecture is used to improve the withstand voltage of the op amp, there will be problems of limited operating voltage and output swing, which will affect the circuit performance. If high-voltage devices are used, the chip area and Mask will be excessively increased, and the cost will be increased.

Therefore, a more economical and reliable withstand voltage circuit design needs to be considered.

Contents of the invention

The first object of the present invention is to provide a MOS bias circuit capable of generating a stable output voltage within a certain fluctuating power supply voltage range, and a voltage-resistant boost circuit.

The second object of the present invention is to provide an analog circuit based on MOS tube withstand voltage protection that improves the withstand voltage performance of the circuit.

The third object of the present invention is to provide a digital circuit that improves the withstand voltage performance of the circuit.

The fourth object of the present invention is to provide a chip that improves the withstand voltage performance of the circuit.

In order to achieve the above-mentioned first object, the MOS bias circuit for increasing circuit withstand voltage provided by the present invention includes a start-up branch, a PMOS bias voltage generation branch and an NMOS bias voltage generation branch, the start-up branch, the PMOS bias voltage generation branch and the NMOS bias voltage generation branch are connected in parallel at the power supply terminal and the ground terminal; the PMOS bias voltage generation branch includes a first controlled switch circuit, a first bias generation module with at least two PMOS transistors connected in series, and a PMOS bias voltage output terminal. The first end of the first bias generation module is electrically connected to the power supply terminal, the second end of the first bias generation module is electrically connected to the ground terminal through the first controlled switch circuit, the second end of the first bias generation module is also electrically connected to the PMOS bias voltage output end; the NMOS bias voltage generation branch circuit includes a second controlled switch circuit, a second bias generation module with at least two NMOS transistors connected in series, and an NMOS bias voltage output end. connected, the second end of the second bias generation module is electrically connected to the ground terminal, and the first end of the second bias generation module is also electrically connected to the NMOS bias voltage output end; the start-up branch provides start-up voltage to the first controlled switch circuit and/or the second controlled switch circuit.

It can be seen from the above scheme that the MOS bias circuit for boosting circuit withstand voltage of the present invention can output a bias voltage that changes according to the power supply voltage by setting the PMOS bias voltage generation branch and the NMOS bias voltage generation branch, and provide the bias voltage to the PMOS transistor and NMOS transistor that play a protective role. At the same time, the PMOS bias voltage generation branch and the NMOS bias voltage generation branch adopt a diode-connected PMOS tube and NMOS tube in series, which can divide the voltage when the power supply voltage is high, and stabilize the voltage when the power supply voltage is low, so as to achieve a relatively stable output voltage within a certain fluctuating power supply voltage range.

In a further solution, the starting branch circuit includes a first resistor, a second resistor, a first PMOS transistor and a first NMOS transistor, the first end of the first resistor is electrically connected to the power supply terminal, the second end of the first resistor is electrically connected to the first end of the second resistor, the second end of the second resistor is electrically connected to the source of the first PMOS transistor, the gate of the first PMOS transistor is electrically connected to the gate of the first NMOS transistor, the drain of the first PMOS transistor is electrically connected to the drain of the first NMOS transistor, the gate of the first PMOS transistor is electrically connected to the drain of the first PMOS transistor, and the first PMOS transistor is electrically connected to the drain of the first PMOS transistor. The source of the NMOS transistor is electrically connected to the ground terminal; the first controlled switch circuit includes a second NMOS transistor and a third NMOS transistor, the drain of the second NMOS transistor is electrically connected to the second end of the first bias generating module, the gate of the second NMOS transistor is electrically connected to the first end of the second resistor, the source of the second NMOS transistor is electrically connected to the drain of the third NMOS transistor, the gate of the third NMOS transistor is electrically connected to the source of the first PMOS transistor, and the source of the third NMOS transistor is electrically connected to the ground terminal.

It can be seen that, by connecting the first PMOS transistor and the first NMOS transistor connected in diode in series, the start-up branch can generate a relatively stable start-up voltage when the power supply voltage is low or high, and is used to start the PMOS bias voltage generation branch and the NMOS bias voltage generation branch to work. At the same time, the second NMOS transistor and the third NMOS transistor are provided in the first controlled switch circuit, which can reduce the voltage to a certain extent and improve the withstand voltage of the circuit.

In a further solution, the second controlled switching circuit includes a second PMOS transistor and a third PMOS transistor, the source of the second PMOS transistor is electrically connected to the power supply terminal, the drain of the second PMOS transistor is electrically connected to the source of the third PMOS transistor, and the drain of the third PMOS is electrically connected to the first end of the second bias generation module; The voltage is greater than the voltage output by the second voltage output end.

It can be seen that the first bias generation module is further provided with a first voltage output terminal and a second voltage output terminal for providing a start-up voltage to the second controlled switch circuit, which can simplify the configuration of the circuit structure.

In a further solution, in the first bias generating module, at least one PMOS transistor and/or at least one resistor are connected in parallel to at least one of the PMOS transistors connected in series.

It can be seen that at least one of the PMOS transistors in series is connected in parallel with a PMOS transistor or a resistor, which can further improve the shunt effect of the first bias generation module and stabilize the output.

In a further solution, in the second bias generation module, at least one NMOS transistor and/or at least one resistor are connected in parallel to at least one of the NMOS transistors connected in series.

It can be seen that at least one of the NMOS transistors in series is connected in parallel with an NMOS transistor or a resistor, which can further improve the shunt effect of the second bias generation module and stabilize the output.

In a further solution, a resistor is further arranged between the first terminal of the first bias generating module and the power supply terminal.

In a further solution, a resistor is further arranged between the second controlled switch circuit and the power supply terminal.

It can be seen that a resistor is provided between the first terminal of the first bias generating module and the power supply terminal, and a resistor is provided between the second controlled switch circuit and the power supply terminal, which can perform current limiting and voltage division to reduce the risk of breakdown and reduce power consumption.

In order to achieve the above-mentioned second purpose, the analog circuit based on MOS tube withstand voltage protection provided by the present invention includes a PMOS tube to be protected, an NMOS tube to be protected, a PMOS tube for protection, an NMOS tube for protection, and a MOS tube bias circuit. The gate of the PMOS transistor for protection is electrically connected, and the NMOS bias voltage output terminal is electrically connected to the gate of the NMOS transistor for protection.

It can be seen from the above scheme that the analog circuit based on MOS tube withstand voltage protection of the present invention inserts the same type of withstand voltage MOS tube into the circuit node where the PMOS tube to be protected and the NMOS tube to be protected are arranged, and protects the surrounding devices at high voltage; at the same time, combined with the MOS bias circuit that improves the circuit withstand voltage, two bias voltages that can be changed according to the power supply voltage are generated. The withstand voltage of the tube is improved to achieve the purpose of improving the overall withstand voltage of the circuit module.

In order to achieve the above-mentioned third purpose, the digital circuit based on MOS tube withstand voltage protection provided by the present invention includes a PMOS tube to be protected, an NMOS tube to be protected, a PMOS tube for protection, an NMOS tube for protection, and a MOS tube bias circuit. The gate of the PMOS transistor for protection is electrically connected, and the NMOS bias voltage output terminal is electrically connected to the gate of the NMOS transistor for protection.

It can be seen that the digital circuit based on the MOS tube withstand voltage protection of the present invention inserts the same type of withstand voltage MOS tube into the circuit node with the PMOS tube to be protected and the NMOS tube to be protected, and plays a protective role to the surrounding devices at high voltage; at the same time, it combines the MOS bias circuit that improves the circuit withstand voltage to generate two bias voltages that can be changed according to the power supply voltage. Voltage, to achieve the purpose of improving the overall withstand voltage of the circuit module. In addition, when the MOS bias circuit and voltage-resistant MOS tube that increase the withstand voltage of the circuit are combined and applied to the digital circuit, it not only protects the VDS (source-drain) withstand voltage of the MOS tube, but also reduces the VGS (gate-source) voltage due to the characteristics of the digital circuit, which is not VDD or 0, and prevents the gate of the MOS tube from being broken down by overvoltage.

In order to achieve the above-mentioned fourth purpose, the chip provided by the present invention is provided with an analog circuit based on MOS tube withstand voltage protection or a digital circuit based on MOS tube withstand voltage protection, the analog circuit based on MOS tube withstand voltage protection uses the above-mentioned analog circuit; the digital circuit based on MOS tube withstand voltage protection uses the above-mentioned digital circuit.

Description of drawings

FIG. 1 is a circuit schematic diagram of an embodiment of a MOS bias circuit for increasing circuit withstand voltage according to the present invention.

Fig. 2 is a circuit schematic diagram applied to a fully symmetrical operational amplifier circuit in an embodiment of an analog circuit based on MOS tube withstand voltage protection in the present invention.

FIG. 3 is a schematic diagram of a circuit applied to a comparator circuit in an embodiment of an analog circuit based on MOS tube withstand voltage protection in the present invention.

FIG. 4 is a schematic diagram of a circuit applied to an inverter in an embodiment of a digital circuit based on MOS tube withstand voltage protection according to the present invention.

FIG. 5 is a schematic diagram of a circuit applied to a NAND gate circuit in an embodiment of a digital circuit based on MOS tube withstand voltage protection according to the present invention.

FIG. 6 is a schematic diagram of a circuit applied to a NOR gate circuit in an embodiment of a digital circuit based on MOS tube withstand voltage protection according to the present invention.

The present invention will be further described below in conjunction with the accompanying drawings and embodiments.

Detailed ways

Example of a MOS bias circuit for boosting circuit withstand voltage:

As shown in FIG. 1, in this embodiment, the MOS bias circuit for boosting circuit withstand voltage includes a start-up branch 1, a PMOS bias voltage generation branch 2, and an NMOS bias voltage generation branch 3. The start-up branch 1, the PMOS bias voltage generation branch 2, and the NMOS bias voltage generation branch 3 are connected in parallel to the power supply terminal VDD and the ground terminal GND.

The PMOS bias voltage generation branch 2 includes a first controlled switch circuit 21, a first bias generation module 22 with at least two PMOS transistors connected in series, and a PMOS bias voltage output terminal HVBP. The PMOS transistors are arranged in a diode connection mode. The first end of the first bias generation module 22 is electrically connected to the power supply terminal VDD, and the second end of the first bias generation module 22 is electrically connected to the ground terminal GND through the first controlled switch circuit 21. electrical connection. The number of PMOS transistors in the first bias generating module 22 can be set according to actual needs. In this embodiment, the number of PMOS transistors in the first bias generating module 22 is four.

The NMOS bias voltage generation branch 3 includes a second controlled switch circuit 31, a second bias generation module 32 with at least two NMOS transistors connected in series, and an NMOS bias voltage output terminal HVBN. The NMOS transistors are arranged in a diode connection mode. The first end of the second bias generation module 32 is electrically connected to the power supply terminal VDD through the second controlled switch circuit 31. The second end of the second bias generation module 32 is electrically connected to the ground terminal GND. The first end of the second bias generation module 32 is also connected to the NMOS bias voltage. The output terminal HVBN is electrically connected. The number of NMOS transistors in the second bias generating module 32 can be set according to actual needs. In this embodiment, the number of NMOS transistors in the first bias generating module 22 is four.

The start-up branch 1 provides a start-up voltage to the first controlled switch circuit 21 and/or the second controlled switch circuit 31 to make the PMOS bias voltage generation branch 2 and the NMOS bias voltage generation branch 3 work.

In this embodiment, the starting branch 1 includes a first resistor R1, a second resistor R2, a first PMOS transistor P1, and a first NMOS transistor N1. The first end of the first resistor R1 is electrically connected to the power supply terminal VDD, the second end of the first resistor R1 is electrically connected to the first end of the second resistor R2, the second end of the second resistor R2 is electrically connected to the source of the first PMOS transistor P1, the gate of the first PMOS transistor P1 is electrically connected to the gate of the first NMOS transistor N1, and the drain of the first PMOS transistor P1 is electrically connected to the first NMOS transistor P1. The drain of the OS transistor N1 is electrically connected, the gate of the first PMOS transistor P1 is electrically connected to the drain of the first PMOS transistor P1 , and the source of the first NMOS transistor N1 is electrically connected to the ground terminal GND.

The first controlled switch circuit 21 includes a second NMOS transistor N2 and a third NMOS transistor N3, the drain of the second NMOS transistor N2 is electrically connected to the second end of the first bias generating module 22, the gate of the second NMOS transistor N2 is electrically connected to the first end of the second resistor R2, the source of the second NMOS transistor N2 is electrically connected to the drain of the third NMOS transistor N3, the gate of the third NMOS transistor N3 is electrically connected to the source of the first PMOS transistor P1, and the gate of the third NMOS transistor N3 is electrically connected to the drain of the third NMOS transistor N3. The source is electrically connected to the ground terminal GND.

The second controlled switch circuit 31 includes a second PMOS transistor P2 and a third PMOS transistor P3, the source of the second PMOS transistor P2 is electrically connected to the power supply terminal VDD, the gate of the second PMOS transistor P2 is electrically connected to the power supply terminal VDD through the first capacitor C1, the drain of the second PMOS transistor P2 is electrically connected to the source of the third PMOS transistor P3, the drain of the third PMOS is electrically connected to the first end of the second bias generating module 32, and the gate of the third PMOS is electrically connected to the power supply terminal VDD through the second capacitor C2.

The first bias generating module 22 is also provided with a first voltage output terminal and a second voltage output terminal, the first voltage output terminal is electrically connected to the gate of the second PMOS transistor P2, the second voltage output terminal is electrically connected to the gate of the third PMOS, and the voltage output by the first voltage output terminal is greater than the voltage output by the second voltage output terminal. The first voltage output terminal and the second voltage output terminal can be set as required, and it is only necessary to ensure that the output voltage of the first voltage output terminal is greater than the output voltage of the second voltage output terminal, and the difference is at least set to twice the threshold voltage Vth of the second PMOS transistor P2 or the third PMOS transistor P3. In this embodiment, in order to simplify the circuit, in the first bias generation module 22, the drain of the second PMOS transistor along the direction from the first end to the second end is electrically connected to the first voltage output end, and the second voltage output end is the PMOS bias voltage output end HVBP.

In this embodiment, a resistor R3 is also provided between the first terminal of the first bias generating module 22 and the power supply terminal VDD. A resistor R4 is also provided between the second controlled switch circuit 31 and the power supply terminal VDD. By setting the resistors R3 and R4, current limiting and voltage division can be performed to reduce the risk of breakdown and reduce power consumption.

In this embodiment, when the power supply terminal VDD is not powered, the MOS bias circuit for boosting the withstand voltage of the circuit does not work. When the power supply terminal VDD starts to supply power, the drain output voltage V2 of the first PMOS transistor P1 in the start-up branch 1 is Vtp+Vtn, where Vtp is the threshold voltage at which the first PMOS transistor P1 is turned on, and Vtn is the threshold voltage at which the first NMOS transistor N1 is turned on. The current of the starting branch 1 is (VDD-Vtp-Vtn)/(R1+R2), then the first terminal of the second resistor R2 outputs a voltage V1=V2+I×R2, thereby generating two relatively stable voltages V1 and V2, which provide voltage bias for the second NMOS transistor N2 and the third NMOS transistor N3 in the first controlled switch circuit 21. The second NMOS transistor N2 and the third NMOS transistor N3 start conducting after receiving V2 and V1, and form a balance with the four PMOSs in the first bias generating module 22, so that the first voltage output terminal generates a relatively fixed voltage V3=VDD-2×Vgs1, wherein Vgs1 is the voltage between the gate and source of the PMOS transistor in the first bias generating module 22 (also equal to the threshold voltage of the PMOS transistor in the diode connection method), and the PMOS bias voltage output terminal HVBP The generated voltage is HVBP=VDD-4×Vgs1, thereby establishing the voltage of the PMOS bias voltage output terminal HVBP. After obtaining the voltage V3 and the voltage HVBP, a voltage bias is provided for the second PMOS transistor P2 and the third PMOS transistor P3 in the second controlled switch circuit 31, so that the second PMOS transistor P2 and the third PMOS transistor P3 are turned on, so that the NMOS bias voltage output terminal HVBN outputs the voltage HVBN=4×Vgs2, wherein, Vgs2 is the voltage between the gate and the source of the NMOS transistor in the second bias generation module 32 (also equal to N in the diode connection method. MOS tube threshold voltage). Due to the settings of the first bias generation module 22 and the second bias generation module 32, the voltage range generated by the PMOS bias voltage output terminal HVBP is 0 to VDD-N×Vgs1 (N is the number of PMOS transistors in the first bias generation module 22), and the voltage range generated by the NMOS bias voltage output terminal HVBN is N×Vgs2 to VDD (N is the number of NMOS transistors in the second bias generation module 32), so that within a certain fluctuating power supply voltage VDD range, relatively stable bias voltage.

It should be noted that, in the first bias generation module 22, at least one of the series-connected PMOS transistors is connected in parallel with at least one PMOS transistor and/or at least one resistor, and in the second bias generation module 32, at least one of the series-connected NMOS transistors is connected in parallel with at least one NMOS transistor and/or at least one resistor. On the basis of the first bias generating module 22 or the second bias generating module 32 being connected in series, individual MOS transistors can be connected in series or in parallel with resistors or MOS transistors in various combinations. This method is only an implementation method derived from the present invention and belongs to the scope of the invention statement. However, this added method does not significantly improve the voltage division effect, and can only increase the establishment speed of the output terminals HVBP and HVBN.

Embodiment of analog circuit based on MOS tube withstand voltage protection:

In this embodiment, the analog circuit based on the withstand voltage protection of the MOS transistor includes a PMOS transistor to be protected, an NMOS transistor to be protected, a PMOS transistor used for protection, an NMOS transistor used for protection, and a MOS transistor bias circuit.

The MOS transistor bias circuit adopts the MOS transistor bias circuit in the above embodiment, the PMOS bias voltage output end is electrically connected to the gate of the PMOS transistor for protection, and the NMOS bias voltage output end is electrically connected to the gate of the NMOS transistor for protection.

In order to better illustrate the analog circuit based on the withstand voltage protection of the MOS tube of the present invention, an example is given below.

In one embodiment, the analog circuit based on the withstand voltage protection of the MOS tube is a fully symmetrical operational amplifier circuit. The fully symmetrical operational amplifier circuit is improved by using a fully symmetrical operational amplifier circuit known to those skilled in the art, and a voltage-resistant MOS transistor of the same type is inserted at the circuit node of the PMOS transistor to be protected and the NMOS transistor to be protected for voltage-resistant protection. As shown in Figure 2, except for the three PMOS transistors in the PMOS transistor group 4 used for protection and the two NMOS transistors in the NMOS transistor group 5 used for protection, the remaining part is a well-known fully symmetrical operational amplifier circuit, which is used to amplify the input Vp, Vn, and output through EA_OUT. In this embodiment, the gate of each PMOS transistor in the PMOS transistor group 4 used for protection is electrically connected to the PMOS bias voltage output terminal in the MOS bias circuit for boosting the withstand voltage of the circuit, and the gate of each NMOS transistor in the NMOS transistor group 5 used for protection is electrically connected to the NMOS bias voltage output terminal of the MOS bias circuit for boosting the withstand voltage of the circuit. By inserting the PMOS transistor group 4 for protection and the NMOS transistor group 5 for protection, voltage division can be performed on a string of MOS transistors (including one or more PMOS and NMOS) that originally bear the VDD voltage, reducing the breakdown probability of the original MOS transistors and improving the withstand voltage of the overall circuit.

In another embodiment, the analog circuit based on the withstand voltage protection of the MOS transistor is a comparator circuit, and the comparator circuit is improved by using a comparator circuit known to those skilled in the art, and the same type of withstand voltage MOS transistor is inserted into the circuit node of the PMOS transistor to be protected and the NMOS transistor to be protected for withstand voltage protection. As shown in Figure 3, except for the two PMOS transistors in the PMOS transistor group 6 used for protection and the four NMOS transistors in the NMOS transistor group 7 used for protection, the remaining part is a known comparator circuit, which is used to compare the input Vp and Vn, and output a high level or a low level through CMPO-H and CMPO-L. In this embodiment, the gate of each PMOS transistor in the PMOS transistor group 6 for protection is electrically connected to the PMOS bias voltage output terminal in the MOS transistor bias circuit, and the gate of each NMOS transistor in the NMOS transistor group 7 for protection is electrically connected to the NMOS bias voltage output terminal in the MOS transistor bias circuit. By inserting the PMOS transistor group 6 for protection and the NMOS transistor group 7 for protection, voltage division can be performed again on the MOS transistors that withstand the VDD voltage, reducing the probability of breakdown and improving the withstand voltage of the overall circuit.

It should be noted that this embodiment is put into the comparator circuit. Due to the insertion of PMOS tube group 6 and NMOS tube group 7, the original CMPO output stage is split into two high and low levels, CMPO-H and CMPO-L, but CMPO-H and CMPO-L still have the same unified logic 1 or 0 expression, and can be used as the input of the subsequent dual-level INV (inverter) module at the same time.

Digital circuit embodiment based on MOS tube withstand voltage protection:

In this embodiment, the digital circuit based on the withstand voltage protection of the MOS transistor includes a PMOS transistor to be protected, an NMOS transistor to be protected, a PMOS transistor used for protection, an NMOS transistor used for protection, and a MOS transistor bias circuit.

The MOS transistor bias circuit adopts the MOS transistor bias circuit in the above embodiment, the PMOS bias voltage output end is electrically connected to the gate of the PMOS transistor for protection, and the NMOS bias voltage output end is electrically connected to the gate of the NMOS transistor for protection.

The digital circuit based on MOS tube withstand voltage protection of the present invention may be digital units such as NOR, NAND, DFF, and inverter. In order to better illustrate the digital circuit based on MOS tube withstand voltage protection of the present invention, an example is given below.

In one embodiment, referring to FIG. 4 , the digital circuit in FIG. 4 is a schematic circuit diagram of an inverter with dual inputs of high and low levels. The high and low level double-input inverter includes PMOS transistor P4, PMOS transistor P5, NMOS transistor N4 and NMOS transistor N5. The source of PMOS transistor P4 is electrically connected to the power supply terminal VDD, the gate of PMOS transistor P4 is electrically connected to the level input terminal INH, the drain of PMOS transistor P4 is electrically connected to the output terminal OUT-H, the drain of PMOS transistor P4 is also electrically connected to the source of PMOS transistor P5, and the gate of PMOS transistor P5 is electrically connected to the MOS voltage boosting circuit. The PMOS bias voltage output terminal in the bias circuit is electrically connected, the drain of the PMOS transistor P5 is electrically connected to the drain of the NMOS transistor N4, the source of the NMOS transistor N4 is electrically connected to the output terminal OUT-L, the source of the NMOS transistor N4 is also electrically connected to the drain of the NMOS transistor N5, the gate of the NMOS transistor N5 is electrically connected to the NMOS bias voltage output terminal in the MOS bias circuit for boosting the withstand voltage of the circuit, and the source of the NMOS transistor N5 is grounded.

When the inverter is working, if the input INH is a logic 0 with a slightly high level and INL is a logic 0 with a low level (actually GND), then the output OUT-H is VDD and OUT-L is a logic 1 with a slightly low level. The withstand voltage tube and the double-level technology of the present invention not only protect the VDS withstand voltage of the MOS tube, but also reduce the VGS voltage due to the characteristic of the digital circuit, which is either VDD or 0, and prevent the gate of the MOS tube from being broken down by overvoltage.

In another embodiment, referring to FIG. 5 , the digital circuit in FIG. 5 is a schematic circuit diagram of a NAND gate circuit. The NAND gate circuit includes PMOS transistor P6, PMOS transistor P7, PMOS transistor P8, NMOS transistor N6, NMOS transistor N7 and NMOS transistor N8, the source of the PMOS transistor P7 and the source of the PMOS transistor P8 are electrically connected to the power supply terminal VDD, the gate of the PMOS transistor P7 is electrically connected to the first level input terminal AH, the gate of the PMOS transistor P8 is electrically connected to the second level input terminal BH, the drain of the PMOS transistor P7 is electrically connected to the drain of the PMOS transistor P8 Both are electrically connected to the source of the PMOS transistor P6, the source of the PMOS transistor P6 is also electrically connected to the output terminal OUT-H, the gate of the PMOS transistor P6 is electrically connected to the PMOS bias voltage output terminal HVBP in the MOS bias circuit of the boost circuit withstand voltage, the drain of the PMOS transistor P6 is electrically connected to the drain of the NMOS transistor N6, the gate of the NMOS transistor N6 is electrically connected to the NMOS bias voltage output terminal HVBN in the MOS bias circuit of the boost circuit withstand voltage, NM The source of the OS transistor N6 is electrically connected to the output terminal OUT-L, the source of the NMOS transistor N6 is also electrically connected to the drain of the NMOS transistor N7, the gate of the NMOS transistor N7 is electrically connected to the third level input terminal AL, the source of the NMOS transistor N7 is electrically connected to the drain of the NMOS transistor N8, the gate of the NMOS transistor N8 is electrically connected to the fourth level input terminal BL, and the source of the NMOS transistor N8 is grounded.

For the NAND gate circuit in Figure 5, if PMOS transistor P6 and NMOS transistor N6 are omitted, it is a standard NAND gate structure, AH and AL are unified into one input A, BH and BL are unified into one input B, OUT-H and OUT-L are unified into one output OUT, and its logic is According to the above, after adding the PMOS transistor P6 and NMOS transistor N6 for withstand voltage protection and the corresponding bias voltages HVBP and HVBN, the input A is split into AH and AL (the logic of AH and AL is the same, only the level is different), the input B is split into BH and BL (the logic of BH and BL is the same, only the level is different), and the output OUT is split into output OUT-H and output OUT-L (the logic of OUT-H and OUT-L is the same, only the level is different), and the logic of OUT-H and OUT-L still for All split input and output digital signals need to be used with high and low level double-input inverters or other similar digital units in the aforementioned examples, or with analog circuits such as dual-level comparator circuits in the aforementioned examples. Based on the standard NAND gate structure, it further improves the withstand voltage between source-drain and gate-source/drain/body, so that digital circuits can work at several times the original VDD voltage.

In another embodiment, referring to FIG. 6 , the digital circuit in FIG. 6 is a schematic circuit diagram of an NOR gate circuit. The NOR gate circuit includes PMOS transistor P9, PMOS transistor P10, PMOS transistor P11, NMOS transistor N9, NMOS transistor N10 and NMOS transistor N11. The source of the PMOS transistor P11 is electrically connected to the power supply terminal VDD, the gate of the PMOS transistor P11 is electrically connected to the first level input terminal AH, the drain of the PMOS transistor P11 is electrically connected to the source of the PMOS transistor P10, and the gate of the PMOS transistor P10 is electrically connected to the second level input terminal BH. connection, the drain of the PMOS transistor P10 is electrically connected to the source of the PMOS transistor P9, the drain of the PMOS transistor P10 is also electrically connected to the output terminal OUT-H, the gate of the PMOS transistor P10 is electrically connected to the PMOS bias voltage output terminal HVBP in the MOS bias circuit for boosting the withstand voltage of the circuit, the drain of the PMOS transistor P10 is electrically connected to the drain of the NMOS transistor N9, and the gate of the NMOS transistor N9 is electrically connected to the NMOS bias in the MOS bias circuit for boosting the withstand voltage of the circuit. The voltage output terminal HVBN is electrically connected, the source of the NMOS transistor N9 is electrically connected to the output terminal OUT-L, the drain of the NMOS transistor N9 and the drain of the NMOS transistor N10 are electrically connected to the source of the NMOS transistor N9, the gate of the NMOS transistor N9 is electrically connected to the third level input terminal AL, the gate of the NMOS transistor N10 is electrically connected to the fourth level input terminal BL, the source of the NMOS transistor N9 and the source of the NMOS transistor N10 are both grounded.

For Figure 6, if PMOS transistor P9 and NMOS transistor N9 are omitted, it is a standard NOR gate structure, AH and AL are unified into one input A, BH and BL are unified into one input B, OUT-H and OUT-L are unified into one output OUT, and its logic is According to the above, after adding the PMOS transistor P9 and NMOS transistor N9 for withstand voltage protection and the corresponding bias voltages HVBP and HVBN, the input A is split into AH and AL (the logic of AH and AL is the same, only the level is different), the input B is split into BH and BL (the logic of BH and BL is the same, only the level is different), the output OUT is split into OUT-H and OUT-L output (the logic of OUT-H and OUT-L is the same, only the level is different), and the logic of OUT-H and OUT-L remains the same. for /> All split input and output digital signals need to be used with high and low level double-input inverters or other similar digital units in the aforementioned examples, or with analog circuits such as dual-level comparator circuits in the aforementioned examples. Based on the standard NOR gate structure, it further improves the withstand voltage between source-drain and gate-source/drain/body, so that digital circuits can work at several times the original VDD voltage.

Chip embodiment:

In this embodiment, the chip is provided with an analog circuit based on MOS tube withstand voltage protection or a digital circuit based on MOS tube withstand voltage protection, and the analog circuit based on MOS tube withstand voltage protection applies the analog circuit in the above embodiment; the digital circuit based on MOS tube withstand voltage protection applies the digital circuit in the above embodiment.

It should be noted that the above are only preferred embodiments of the present invention, but the design concept of the invention is not limited thereto, and any insubstantial modifications made to the present invention using this concept also fall within the scope of protection of the present invention.

Claims (10)

1. A MOS bias circuit for improving circuit withstand voltage is characterized in that: the power supply device comprises a starting branch, a PMOS bias voltage generating branch and an NMOS bias voltage generating branch, wherein the starting branch, the PMOS bias voltage generating branch and the NMOS bias voltage generating branch are connected in parallel with a power supply end and a grounding end;

the PMOS bias voltage generation branch circuit comprises a first controlled switch circuit, a first bias generation module and a PMOS bias voltage output end, wherein the first bias generation module is provided with at least two PMOS tubes which are connected in series, the PMOS tubes are arranged in a diode connection mode, a first end of the first bias generation module is electrically connected with the power supply end, a second end of the first bias generation module is electrically connected with the grounding end through the first controlled switch circuit, and a second end of the first bias generation module is also electrically connected with the PMOS bias voltage output end;

the NMOS bias voltage generation branch circuit comprises a second controlled switch circuit, a second bias generation module and an NMOS bias voltage output end, wherein the second bias generation module is provided with at least two NMOS tubes which are connected in series, the NMOS tubes are arranged in a diode connection mode, a first end of the second bias generation module is electrically connected with the power supply end through the second controlled switch circuit, a second end of the second bias generation module is electrically connected with the grounding end, and a first end of the second bias generation module is also electrically connected with the NMOS bias voltage output end;

the start-up branch provides a start-up voltage to the first controlled switching circuit and/or the second controlled switching circuit.

2. The MOS bias circuit of claim 1 wherein the circuit withstand voltage is raised by:

the starting branch circuit comprises a first resistor, a second resistor, a first PMOS tube and a first NMOS tube, wherein the first end of the first resistor is electrically connected with the power supply end, the second end of the first resistor is electrically connected with the first end of the second resistor, the second end of the second resistor is electrically connected with the source electrode of the first PMOS tube, the grid electrode of the first PMOS tube is electrically connected with the grid electrode of the first NMOS tube, the drain electrode of the first PMOS tube is electrically connected with the drain electrode of the first NMOS tube, the grid electrode of the first PMOS tube is electrically connected with the drain electrode of the first PMOS tube, and the source electrode of the first NMOS tube is electrically connected with the ground end;

the first controlled switch circuit comprises a second NMOS tube and a third NMOS tube, wherein the drain electrode of the second NMOS tube is electrically connected with the second end of the first bias generation module, the grid electrode of the second NMOS tube is electrically connected with the first end of the second resistor, the source electrode of the second NMOS tube is electrically connected with the drain electrode of the third NMOS tube, the grid electrode of the third NMOS tube is electrically connected with the source electrode of the first PMOS tube, and the source electrode of the third NMOS tube is electrically connected with the grounding end.

3. The MOS bias circuit of claim 2 wherein the voltage withstand of the circuit is raised by:

the second controlled switch circuit comprises a second PMOS tube and a third PMOS tube, the source electrode of the second PMOS tube is electrically connected with the power supply end, the drain electrode of the second PMOS tube is electrically connected with the source electrode of the third PMOS tube, and the drain electrode of the third PMOS tube is electrically connected with the first end of the second bias generation module;

the first bias generation module is further provided with a first voltage output end and a second voltage output end, the first voltage output end is electrically connected with the grid electrode of the second PMOS tube, the second voltage output end is electrically connected with the grid electrode of the third PMOS tube, and the voltage output by the first voltage output end is larger than the voltage output by the second voltage output end.

4. A MOS bias circuit for boosting a withstand voltage of a circuit according to any one of claims 1 to 3, wherein:

in the first bias generation module, at least one PMOS tube and/or at least one resistor is connected in parallel with at least one of the PMOS tubes connected in series.

5. A MOS bias circuit for boosting a withstand voltage of a circuit according to any one of claims 1 to 3, wherein:

in the second bias generation module, at least one of the NMOS tubes connected in series is connected with at least one NMOS tube and/or at least one resistor in parallel.

6. A MOS bias circuit for boosting a withstand voltage of a circuit according to any one of claims 1 to 3, wherein:

a resistor is further arranged between the first end of the first bias generation module and the power end.

7. A MOS bias circuit for boosting a withstand voltage of a circuit according to any one of claims 1 to 3, wherein:

and a resistor is arranged between the second controlled switching circuit and the power supply end.

8. An analog circuit based on MOS pipe withstand voltage protection, its characterized in that: the MOS bias circuit comprises a PMOS tube to be protected, an NMOS tube for protection and a MOS bias circuit for improving the withstand voltage of the circuit, wherein the PMOS tube for protection is connected in series with the drain electrode of the PMOS tube to be protected, and the NMOS tube for protection is connected in series with the drain electrode of the NMOS tube to be protected;

the MOS bias circuit for improving circuit voltage resistance adopts the MOS bias circuit for improving circuit voltage resistance according to any one of claims 1 to 7, wherein the PMOS bias voltage output end is electrically connected with the grid electrode of the PMOS tube for protection, and the NMOS bias voltage output end is electrically connected with the grid electrode of the NMOS tube for protection.

9. A digital circuit based on MOS tube voltage-resistant protection is characterized in that: the MOS bias circuit comprises a PMOS tube to be protected, an NMOS tube for protection and a MOS bias circuit for improving circuit withstand voltage, wherein the PMOS tube for protection is connected in series with the drain electrode of the PMOS tube to be protected, and the NMOS tube for protection is connected in series with the drain electrode of the NMOS tube to be protected;

the MOS bias circuit for improving circuit voltage resistance adopts the MOS bias circuit for improving circuit voltage resistance according to any one of claims 1 to 7, wherein the PMOS bias voltage output end is electrically connected with the grid electrode of the PMOS tube for protection, and the NMOS bias voltage output end is electrically connected with the grid electrode of the NMOS tube for protection.

10. The utility model provides a chip is provided with the analog circuit based on MOS pipe withstand voltage protection or the digital circuit based on MOS pipe withstand voltage protection, its characterized in that: the analog circuit based on MOS tube voltage-resistant protection is applied to the analog circuit of claim 8;

the digital circuit based on MOS tube voltage-resistant protection applies the digital circuit of claim 9.