CN116466784A

CN116466784A - MOS bias circuit, analog circuit, digital circuit and chip for improving circuit withstand voltage

Info

Publication number: CN116466784A
Application number: CN202310303497.3A
Authority: CN
Inventors: 叶滢
Original assignee: X Powers Co ltd
Current assignee: X Powers Co ltd
Priority date: 2023-03-13
Filing date: 2023-03-13
Publication date: 2023-07-21

Abstract

The invention provides a MOS bias circuit, an analog circuit, a digital circuit and a chip for improving circuit withstand voltage, wherein the MOS bias circuit for improving circuit withstand voltage comprises a starting branch, a PMOS bias voltage generating branch and an NMOS bias voltage generating branch, and the starting branch, the PMOS bias voltage generating branch and the NMOS bias voltage generating branch are connected in parallel with a power end and a grounding end; the PMOS bias voltage generation branch circuit comprises a first bias generation module which is provided with at least two PMOS tubes connected in series, and the PMOS tubes are arranged in a diode connection mode; the NMOS bias voltage generation branch circuit comprises a second bias generation module with at least two NMOS tubes connected in series, and the NMOS tubes are arranged in a diode connection mode. The analog circuit applies the MOS bias circuit. The digital circuit applies the MOS bias circuit. The chip applies the analog circuit or the digital circuit. The MOS bias circuit can generate stable output voltage in a certain fluctuation power supply voltage range, and improves the voltage-resistant performance of the circuit.

Description

MOS bias circuit, analog circuit, digital circuit and chip for improving circuit withstand voltage

Technical Field

The invention relates to the technical field of analog and digital hybrid circuit design, in particular to a MOS bias circuit for improving circuit voltage resistance, an analog circuit based on MOS tube voltage resistance protection of the MOS bias circuit for improving circuit voltage resistance, a digital circuit based on MOS tube voltage resistance protection of the MOS bias circuit for improving circuit voltage resistance, and a chip applying the analog circuit or the digital circuit.

Background

Currently, the improvement of power and energy efficiency ratio of SoC (System on Chip) is required to promote the advanced process to use more low-voltage devices such as 0.8V and 1.8V. The IO, ADC and other modules designed by the device are difficult to directly meet the application of the high-voltage power domain of 3.3V and the like. In addition, the power supply chip is often damaged due to EOS caused by front-stage surge or high-voltage misplug, so that the reliability of the IC needs to be improved, or a part of protection modules have similar high-voltage working risks. Therefore, it is necessary to raise the overall withstand voltage of the circuit, and in particular, to solve various withstand voltage problems including MOS transistors, such as Source-Drain withstand voltage, gate-to-Source/Drain/Body withstand voltage, and the like.

In the prior art, the architecture replacement of a part of circuits is mainly relied on, such as a Cascade circuit module is used for an operational amplifier, or a higher withstand voltage LDMOS is used in a process, such as high-voltage tubes of 6V, 12V, 30V, 40V and the like. However, the Casecode architecture is adopted to improve the operational amplifier withstand voltage, so that the problems of limited working voltage and limited output swing are caused, the circuit performance is affected, and if a high-voltage device is adopted, the chip area and Mask are excessively increased, and the cost is increased.

Therefore, more economical and reliable withstand voltage circuit designs need to be considered.

Disclosure of Invention

A first object of the present invention is to provide a voltage-boosting MOS bias circuit capable of generating a stable output voltage in a range of a power supply voltage that fluctuates.

The second purpose of the invention is to provide an analog circuit based on MOS tube voltage-resistant protection, which improves the voltage-resistant performance of the circuit.

A third object of the present invention is to provide a digital circuit that improves the voltage withstand performance of the circuit.

A fourth object of the present invention is to provide a chip that improves the voltage withstand performance of a circuit.

In order to achieve the first object, the MOS bias circuit for improving the withstand voltage of the circuit provided by the invention comprises a starting branch, a PMOS bias voltage generating branch and an NMOS bias voltage generating branch, wherein the starting branch, the PMOS bias voltage generating branch and the NMOS bias voltage generating branch are connected in parallel with a power end and a grounding end; the PMOS bias voltage generation branch circuit comprises a first controlled switch circuit, a first bias generation module and a PMOS bias voltage output end, wherein the first bias generation module is provided with at least two PMOS tubes which are connected in series, the PMOS tubes are arranged in a diode connection mode, a first end of the first bias generation module is electrically connected with a power supply end, a second end of the first bias generation module is electrically connected with a grounding end through the first controlled switch circuit, and a second end of the first bias generation module is also electrically connected with the PMOS bias voltage output end; the NMOS bias voltage generation branch circuit comprises a second controlled switch circuit, a second bias generation module and an NMOS bias voltage output end, wherein the second bias generation module is provided with at least two NMOS tubes which are connected in series, the NMOS tubes are arranged in a diode connection mode, the first end of the second bias generation module is electrically connected with the power supply end through the second controlled switch circuit, the second end of the second bias generation module is electrically connected with the grounding end, and the first end of the second bias generation module is also electrically connected with the NMOS bias voltage output end; the start-up branch provides a start-up voltage to the first controlled switching circuit and/or the second controlled switching circuit.

According to the scheme, the MOS bias circuit for improving the withstand voltage of the circuit can output the bias voltage changing according to the power supply voltage by arranging the PMOS bias voltage generation branch circuit and the NMOS bias voltage generation branch circuit, and provide the bias voltage for the PMOS tube and the NMOS tube with the protection function. Meanwhile, the PMOS bias voltage generating branch circuit and the NMOS bias voltage generating branch circuit are connected in series by adopting a PMOS tube and an NMOS tube which are connected by a diode, so that voltage division can be performed when the power supply voltage is high, and voltage stabilization can be performed when the power supply voltage is low, and therefore, relatively stable output voltage is generated in a certain fluctuation power supply voltage range.

In a further scheme, the starting branch circuit comprises a first resistor, a second resistor, a first PMOS tube and a first NMOS tube, wherein the first end of the first resistor is electrically connected with the power supply end, the second end of the first resistor is electrically connected with the first end of the second resistor, the second end of the second resistor is electrically connected with the source electrode of the first PMOS tube, the grid electrode of the first PMOS tube is electrically connected with the grid electrode of the first NMOS tube, the drain electrode of the first PMOS tube is electrically connected with the drain electrode of the first NMOS tube, the grid electrode of the first PMOS tube is electrically connected with the drain electrode of the first PMOS tube, and the source electrode of the first NMOS tube is electrically connected with the ground end; the first controlled switching circuit comprises a second NMOS tube and a third NMOS tube, the drain electrode of the second NMOS tube is electrically connected with the second end of the first bias generation module, the grid electrode of the second NMOS tube is electrically connected with the first end of the second resistor, the source electrode of the second NMOS tube is electrically connected with the drain electrode of the third NMOS tube, the grid electrode of the third NMOS tube is electrically connected with the source electrode of the first PMOS tube, and the source electrode of the third NMOS tube is electrically connected with the grounding end.

Therefore, the starting branch circuit is connected in series through the first PMOS tube and the first NMOS tube which are connected by the diode connection method, and relatively stable starting voltage can be generated when the power supply voltage is low or high and is used for starting the PMOS bias voltage generating branch circuit and the NMOS bias voltage generating branch circuit to work. Meanwhile, the first controlled switching circuit is provided with the second NMOS tube and the third NMOS tube, so that a certain voltage reduction effect can be achieved, and the voltage resistance of the circuit is improved.

In a further scheme, the second controlled switch circuit comprises a second PMOS tube and a third PMOS tube, the source electrode of the second PMOS tube is electrically connected with the power supply end, the drain electrode of the second PMOS tube is electrically connected with the source electrode of the third PMOS tube, and the drain electrode of the third PMOS tube is electrically connected with the first end of the second bias generation module; the first bias generation module is further provided with a first voltage output end and a second voltage output end, the first voltage output end is electrically connected with the grid electrode of the second PMOS tube, the second voltage output end is electrically connected with the grid electrode of the third PMOS tube, and the voltage output by the first voltage output end is larger than the voltage output by the second voltage output end.

It can be seen that the first bias generating module is further provided with a first voltage output terminal and a second voltage output terminal for providing the start-up voltage to the second controlled switching circuit, which can simplify the circuit configuration.

In a further scheme, in the first bias generation module, at least one of the PMOS tubes connected in series is connected in parallel with at least one PMOS tube and/or at least one resistor.

Therefore, at least one of the PMOS tubes connected in series is connected with a PMOS tube or a resistor in parallel, so that the shunting effect of the first bias generation module can be further improved, and the output is stable.

In a further scheme, in the second bias generation module, at least one of the NMOS tubes connected in series is connected with at least one NMOS tube and/or at least one resistor in parallel.

Therefore, at least one of the NMOS tubes connected in series is connected with an NMOS tube or a resistor in parallel, so that the shunt effect of the second bias generation module can be further improved, and the output is stable.

In a further scheme, a resistor is further arranged between the first end of the first bias generation module and the power supply end.

In a further scheme, a resistor is further arranged between the second controlled switch circuit and the power supply end.

Therefore, a resistor is further arranged between the first end of the first bias generation module and the power end, and a resistor is further arranged between the second controlled switching circuit and the power end, so that current limiting and voltage dividing can be performed, breakdown risk is reduced, and power consumption is reduced.

In order to achieve the second objective, the analog circuit based on MOS tube voltage-resistant protection provided by the invention comprises a PMOS tube to be protected, an NMOS tube to be protected, a PMOS tube for protection, an NMOS tube for protection, and an MOS tube bias circuit, wherein the PMOS tube for protection is connected in series with the drain electrode of the PMOS tube to be protected, and the NMOS tube for protection is connected in series with the drain electrode of the NMOS tube to be protected; the MOS tube bias circuit adopts the MOS tube bias circuit, the PMOS bias voltage output end is electrically connected with the grid electrode of the PMOS tube for protection, and the NMOS bias voltage output end is electrically connected with the grid electrode of the NMOS tube for protection.

According to the scheme, the analog circuit based on the MOS tube voltage-resistant protection has the advantages that the voltage-resistant MOS tubes of the same type are inserted into the circuit nodes provided with the PMOS tube to be protected and the NMOS tube to be protected, so that the analog circuit plays a role in protecting surrounding devices at high voltage; meanwhile, by combining with the MOS bias circuit for improving the voltage resistance of the circuit, two bias voltages which can be changed according to the power supply voltage are generated, the inserted voltage-resistant PMOS tube and NMOS tube are placed in different working states, the functions of low-voltage through connection and high-voltage protection on peripheral devices are realized, the voltage resistance of the MOS tube is comprehensively improved, and the purpose of improving the overall voltage resistance of the circuit module is achieved.

In order to achieve the third objective, the digital circuit based on MOS tube voltage withstand protection provided by the invention comprises a PMOS tube to be protected, an NMOS tube to be protected, a PMOS tube for protection, an NMOS tube for protection, and an MOS tube bias circuit, wherein the PMOS tube for protection is connected in series with the drain electrode of the PMOS tube to be protected, and the NMOS tube for protection is connected in series with the drain electrode of the NMOS tube to be protected; the MOS tube bias circuit adopts the MOS tube bias circuit, the PMOS bias voltage output end is electrically connected with the grid electrode of the PMOS tube for protection, and the NMOS bias voltage output end is electrically connected with the grid electrode of the NMOS tube for protection.

Therefore, the digital circuit based on the MOS tube voltage-resistant protection has the advantages that the voltage-resistant MOS tubes of the same type are inserted into the circuit nodes provided with the PMOS tube to be protected and the NMOS tube to be protected, so that the digital circuit plays a role in protecting surrounding devices at high voltage; meanwhile, by combining with the MOS bias circuit for improving the voltage resistance of the circuit, two bias voltages which can be changed according to the power supply voltage are generated, the inserted voltage-resistant PMOS tube and NMOS tube are placed in different working states, the functions of low-voltage through connection and high-voltage protection on peripheral devices are realized, the voltage resistance of the MOS tube is comprehensively improved, and the purpose of improving the overall voltage resistance of the circuit module is achieved. In addition, when the MOS bias circuit for improving the voltage resistance of the circuit and the voltage-resistant MOS tube are combined and applied to the digital circuit, the voltage resistance of VDS (source end-drain end) of the MOS tube is protected, and because of the characteristic that the digital circuit is not VDD, namely 0, the voltage of VGS (gate end-source end) is reduced by double level, and the grid electrode of the MOS tube is prevented from being broken down by overvoltage.

In order to achieve the fourth object, the chip provided by the invention is provided with an analog circuit based on MOS tube voltage withstand protection or a digital circuit based on MOS tube voltage withstand protection, and the analog circuit based on MOS tube voltage withstand protection is applied to the analog circuit; the digital circuit based on MOS tube voltage-resistant protection is applied to the digital circuit.

Drawings

Fig. 1 is a schematic circuit diagram of an embodiment of a MOS bias circuit of the present invention that boosts the withstand voltage of the circuit.

Fig. 2 is a schematic circuit diagram of an analog circuit embodiment based on voltage protection of a MOS transistor applied to a fully symmetrical operational amplifier circuit according to the present invention.

Fig. 3 is a schematic circuit diagram of an analog circuit embodiment based on voltage protection of a MOS transistor applied to a comparator circuit according to the present invention.

Fig. 4 is a schematic circuit diagram of an inverter applied in an embodiment of a digital circuit based on voltage protection of a MOS transistor according to the present invention.

Fig. 5 is a schematic circuit diagram of a digital circuit embodiment based on voltage protection of a MOS transistor applied to a nand gate circuit according to the present invention.

Fig. 6 is a schematic circuit diagram of a nor gate circuit applied to an embodiment of a digital circuit based on voltage protection of a MOS transistor according to the present invention.

The invention is further described below with reference to the drawings and examples.

Detailed Description

MOS bias circuit embodiment to boost circuit withstand voltage:

as shown in fig. 1, in the present embodiment, the MOS bias circuit for improving the withstand voltage of the circuit includes a start-up branch 1, a PMOS bias voltage generating branch 2, and an NMOS bias voltage generating branch 3, where the start-up branch 1, the PMOS bias voltage generating branch 2, and the NMOS bias voltage generating branch 3 are connected in parallel to a power supply terminal VDD and a ground terminal GND.

The PMOS bias voltage generating branch 2 includes a first controlled switch circuit 21, a first bias generating module 22 having at least two PMOS transistors connected in series, and a PMOS bias voltage output end HVBP, where the PMOS transistors are arranged in a diode connection manner, a first end of the first bias generating module 22 is electrically connected to the power supply end VDD, a second end of the first bias generating module 22 is electrically connected to the ground end GND through the first controlled switch circuit 21, and a second end of the first bias generating module 22 is also electrically connected to the PMOS bias voltage output end HVBP. The number of PMOS transistors in the first bias generation module 22 may be set according to actual needs, and in this embodiment, the number of PMOS transistors in the first bias generation module 22 is four.

The NMOS bias voltage generating branch 3 includes a second controlled switch circuit 31, a second bias generating module 32 having at least two NMOS transistors connected in series, and an NMOS bias voltage output HVBN, where the NMOS transistors are arranged in a diode connection manner, a first end of the second bias generating module 32 is electrically connected to the power supply terminal VDD through the second controlled switch circuit 31, a second end of the second bias generating module 32 is electrically connected to the ground terminal GND, and a first end of the second bias generating module 32 is also electrically connected to the NMOS bias voltage output HVBN. The number of NMOS transistors in the second bias generation module 32 may be set according to practical needs, and in this embodiment, the number of NMOS transistors in the first bias generation module 22 is four.

The start-up branch 1 supplies a start-up voltage to the first controlled switching circuit 21 and/or the second controlled switching circuit 31 to operate the PMOS bias voltage generating branch 2 and the NMOS bias voltage generating branch 3.

In this embodiment, the starting branch 1 includes a first resistor R1, a second resistor R2, a first PMOS transistor P1 and a first NMOS transistor N1, where a first end of the first resistor R1 is electrically connected to the power supply terminal VDD, a second end of the first resistor R1 is electrically connected to a first end of the second resistor R2, a second end of the second resistor R2 is electrically connected to a source of the first PMOS transistor P1, a gate of the first PMOS transistor P1 is electrically connected to a gate of the first NMOS transistor N1, a drain of the first PMOS transistor P1 is electrically connected to a drain of the first NMOS transistor N1, a gate of the first PMOS transistor P1 is electrically connected to a drain of the first PMOS transistor P1, and a source of the first NMOS transistor N1 is electrically connected to the ground terminal GND.

The first controlled switch circuit 21 includes a second NMOS transistor N2 and a third NMOS transistor N3, where a drain of the second NMOS transistor N2 is electrically connected to the second end of the first bias generating module 22, a gate of the second NMOS transistor N2 is electrically connected to the first end of the second resistor R2, a source of the second NMOS transistor N2 is electrically connected to a drain of the third NMOS transistor N3, a gate of the third NMOS transistor N3 is electrically connected to a source of the first PMOS transistor P1, and a source of the third NMOS transistor N3 is electrically connected to the ground GND.

The second controlled switch circuit 31 includes a second PMOS transistor P2 and a third PMOS transistor P3, where a source of the second PMOS transistor P2 is electrically connected to the power supply terminal VDD, a gate of the second PMOS transistor P2 is electrically connected to the power supply terminal VDD through the first capacitor C1, a drain of the second PMOS transistor P2 is electrically connected to a source of the third PMOS transistor P3, a drain of the third PMOS transistor is electrically connected to the first terminal of the second bias generation module 32, and a gate of the third PMOS transistor is electrically connected to the power supply terminal VDD through the second capacitor C2.

The first bias generating module 22 is further provided with a first voltage output end and a second voltage output end, the first voltage output end is electrically connected with the gate of the second PMOS transistor P2, the second voltage output end is electrically connected with the gate of the third PMOS transistor, and the voltage output by the first voltage output end is greater than the voltage output by the second voltage output end. The first voltage output end and the second voltage output end can be set according to the needs, and only the voltage output by the first voltage output end is ensured to be larger than the voltage output by the second voltage output end, and the difference value is at least set to be one time of threshold voltage Vth of the second PMOS tube P2 or the third PMOS tube P3. In this embodiment, in order to simplify the circuit, in the first bias generating module 22, the drain electrode of the second PMOS transistor along the direction from the first end to the second end is electrically connected to the first voltage output end, and the second voltage output end is the PMOS bias voltage output end HVBP.

In this embodiment, a resistor R3 is further disposed between the first end of the first bias generating module 22 and the power supply terminal VDD. A resistor R4 is also provided between the second controlled switching circuit 31 and the power supply terminal VDD. By setting the resistor R3 and the resistor R4, current limiting and voltage dividing can be performed, so that breakdown risk is reduced, and power consumption is reduced.

In this embodiment, when the power supply terminal VDD is not powered, the MOS bias circuit for raising the withstand voltage of the circuit does not work, and when the power supply terminal VDD starts to supply power, the drain output voltage V2 of the first PMOS transistor P1 in the startup branch 1 is vtp+vtn, vtp is the threshold voltage of the first PMOS transistor P1 being turned on, and Vtn is the threshold voltage of the first NMOS transistor N1 being turned on. The current of the starting branch 1 is (VDD-Vtp-Vtn)/(r1+r2), and the first terminal of the second resistor R2 outputs a voltage v1=v2+i×r2, thereby generating two relatively stable voltages V1 and V2, which provide voltage bias for the second NMOS transistor N2 and the third NMOS transistor N3 in the first controlled switching circuit 21. The second NMOS transistor N2 and the third NMOS transistor N3 begin to turn on after receiving V2 and V1, and form a balance with 4 PMOS in the first bias generation module 22, so that the first voltage output terminal generates a relatively fixed voltage v3=vdd-2×vgs1, where Vgs1 is a voltage between the gate and the source of the PMOS transistor in the first bias generation module 22 (which is also equal to the threshold voltage of the PMOS transistor in the diode connection), and the PMOS bias voltage output terminal HVBP generates a voltage hvbp=vdd-4×vgs1, thereby establishing a voltage of the PMOS bias voltage output terminal HVBP. After the voltage V3 and the voltage HVBP are obtained, a voltage bias is provided for the second PMOS transistor P2 and the third PMOS transistor P3 in the second controlled switching circuit 31, so that the second PMOS transistor P2 and the third PMOS transistor P3 are turned on, and the NMOS bias voltage output terminal HVBN outputs a voltage hvbn=4×vgs2, where Vgs2 is a voltage between the gate and the source of the NMOS transistor in the second bias generating module 32 (which is also equal to the threshold voltage of the NMOS transistor in the diode connection). Due to the arrangement of the first bias generation module 22 and the second bias generation module 32, the voltage range generated by the PMOS bias voltage output terminal HVBP is 0 to VDD-n×vgs1 (N is the number of PMOS transistors in the first bias generation module 22), and the voltage range generated by the NMOS bias voltage output terminal HVBN is n×vgs2 to VDD (N is the number of NMOS transistors in the second bias generation module 32), so that a relatively stable bias voltage can be generated within a certain fluctuating power supply voltage VDD range.

It should be noted that, in the first bias generation module 22, at least one PMOS tube and/or at least one resistor is connected in parallel to at least one PMOS tube in series, and in the second bias generation module 32, at least one NMOS tube and/or at least one resistor is connected in parallel to at least one NMOS tube in series. On the basis that the first bias generation module 22 or the second bias generation module 32 are connected in series, the individual MOS tubes can be connected in series, in parallel with resistors or MOS tubes in various combinations, and the mode is only an implementation mode derived by the invention and belongs to the statement scope of the invention, but the voltage division effect is not obviously improved by the mode of adding, and only the establishment speed of the output ends HVBP and HVBN can be improved.

Analog circuit embodiment based on MOS pipe withstand voltage protection:

in this embodiment, the analog circuit based on the voltage-withstanding protection of the MOS transistor includes a PMOS transistor to be protected, an NMOS transistor to be protected, and a MOS transistor bias circuit, where the PMOS transistor to be protected is connected in series to the drain of the PMOS transistor to be protected, and the NMOS transistor to be protected is connected in series to the drain of the NMOS transistor to be protected.

The MOS tube bias circuit adopts the MOS tube bias circuit in the embodiment, the PMOS bias voltage output end is electrically connected with the grid electrode of the PMOS tube for protection, and the NMOS bias voltage output end is electrically connected with the grid electrode of the NMOS tube for protection.

In order to better illustrate the analog circuit based on the voltage-resistant protection of the MOS transistor, the following description is given by way of example.

In one embodiment, the analog circuit based on MOS tube voltage withstand protection is a fully symmetrical operational amplifier circuit. The full-symmetrical operational amplifier circuit is improved by adopting a full-symmetrical operational amplifier circuit known by a person skilled in the art, and the circuit nodes of the PMOS tube to be protected and the NMOS tube to be protected are inserted into the same type of voltage-resistant MOS tube to be voltage-resistant protected. As shown in fig. 2, the three PMOS transistors in the PMOS transistor group for protection 4 and the two NMOS transistors in the NMOS transistor group for protection 5 are removed, and the remaining portion is a well-known symmetrical op-amp circuit for amplifying the inputs Vp, vn and outputting through ea_out. In this embodiment, the gate of each PMOS transistor in the PMOS transistor group 4 for protection is electrically connected to the PMOS bias voltage output terminal in the voltage-resistant MOS bias circuit of the boost circuit, and the gate of each NMOS transistor in the NMOS transistor group 5 for protection is electrically connected to the NMOS bias voltage output terminal in the voltage-resistant MOS bias circuit of the boost circuit. By inserting the PMOS tube group 4 for protection and the NMOS tube group 5 for protection, a series of MOS tubes (comprising one or more PMOS and NMOS) which are originally subjected to VDD voltage can be subjected to voltage division again, so that the breakdown probability of the original MOS tubes is reduced, and the withstand voltage of the whole circuit is improved.

In another embodiment, the analog circuit based on the voltage-withstanding protection of the MOS tube is a comparator circuit, the comparator circuit is improved by adopting a comparator circuit known by a person skilled in the art, and voltage-withstanding protection is performed by inserting the same type of voltage-withstanding MOS tube into circuit nodes of the PMOS tube to be protected and the NMOS tube to be protected. As shown in fig. 3, two PMOS transistors in the PMOS transistor group for protection 6 and four NMOS transistors in the NMOS transistor group for protection 7 are removed, and the remaining portion is a well-known comparator circuit for comparing inputs Vp, vn and outputting a high level or a low level through CMPO-H and CMPO-L. In this embodiment, the gate of each PMOS transistor in the PMOS transistor group 6 for protection is electrically connected to the PMOS bias voltage output terminal in the MOS transistor bias circuit, and the gate of each NMOS transistor in the NMOS transistor group 7 for protection is electrically connected to the NMOS bias voltage output terminal in the MOS transistor bias circuit. By inserting the PMOS tube group 6 for protection and the NMOS tube group 7 for protection, the MOS tube bearing the VDD voltage can be divided again, the breakdown probability is reduced, and the withstand voltage of the whole circuit is improved.

It should be noted that, in this embodiment, the input of the two-level INV (inverter) module at the same time can be realized by inserting the PMOS transistor group 6 and the NMOS transistor group 7 into the comparator circuit so that the original CMPO output stage is split into two CMPO-H, CMPO-L with different levels, but CMPO-H, CMPO-L still has the same unified logic 1 or 0 expression.

Digital circuit embodiments based on MOS tube voltage withstand protection:

in this embodiment, the digital circuit based on the voltage-withstanding protection of the MOS transistor includes a PMOS transistor to be protected, an NMOS transistor to be protected, a MOS transistor bias circuit, where the PMOS transistor to be protected is connected in series to the drain of the PMOS transistor to be protected, and the NMOS transistor to be protected is connected in series to the drain of the NMOS transistor to be protected.

The digital circuit based on MOS tube voltage-resistant protection can be a NOR, NAND, DFF digital unit, an inverter and other digital units. In order to better illustrate the digital circuit based on MOS transistor voltage-withstand protection of the invention, the following is exemplified.

In one embodiment, referring to fig. 4, the digital circuit of fig. 4 is a schematic circuit diagram of a high-low level dual-input inverter. The high-low level dual-input inverter comprises a PMOS tube P4, a PMOS tube P5, an NMOS tube N4 and an NMOS tube N5, wherein the source electrode of the PMOS tube P4 is electrically connected with a power supply end VDD, the grid electrode of the PMOS tube P4 is electrically connected with a level input end INH, the drain electrode of the PMOS tube P4 is electrically connected with an output end OUT-H, the drain electrode of the PMOS tube P4 is also electrically connected with the source electrode of the PMOS tube P5, the grid electrode of the PMOS tube P5 is electrically connected with a PMOS bias voltage output end in a MOS bias circuit with a voltage withstanding lifting circuit, the drain electrode of the PMOS tube P5 is electrically connected with the drain electrode of the NMOS tube N4, the source electrode of the NMOS tube N4 is electrically connected with an output end OUT-L, the source electrode of the NMOS tube N4 is also electrically connected with the drain electrode of the NMOS tube N5, the grid electrode of the NMOS tube N5 is electrically connected with an NMOS bias voltage output end in the MOS bias circuit with a voltage withstanding circuit lifting circuit, and the source electrode of the NMOS tube N5 is grounded.

When the inverter is in operation, if the input INH is a logic 0 with a slightly high level and the input INL is a logic 0 with a low level (actually GND), the output OUT-H is VDD and OUT-L is a logic 1 with a slightly low level, if the input INH is a logic 1 with a slightly high level or VDD and INL is a logic 1 with a slightly low level, the output OUT-H is a logic 0 with a slightly high level and OUT-L is 0 (actually GND). Through the voltage-resistant tube and the double-level technology, the VDS voltage resistance of the MOS tube is protected, and because of the characteristic that a digital circuit is not VDD, namely 0, the double-level voltage reduces VGS voltage, and the grid electrode of the MOS tube is prevented from being broken down by overvoltage.

In another embodiment, referring to fig. 5, the digital circuit of fig. 5 is a circuit schematic of a nand gate. The NAND gate circuit comprises a PMOS tube P6, a PMOS tube P7, a PMOS tube P8, an NMOS tube N6, an NMOS tube N7 and an NMOS tube N8, wherein the source electrode of the PMOS tube P7 and the source electrode of the PMOS tube P8 are electrically connected with a power supply end VDD, the grid electrode of the PMOS tube P7 is electrically connected with a first level input end AH, the grid electrode of the PMOS tube P8 is electrically connected with a second level input end BH, the drain electrode of the PMOS tube P7 and the drain electrode of the PMOS tube P8 are electrically connected with the source electrode of the PMOS tube P6, the source electrode of the PMOS tube P6 is also electrically connected with an output end OUT-H, the grid electrode of the PMOS tube P6 is electrically connected with a PMOS bias voltage output end HVBP in a MOS bias circuit of a lifting circuit, the drain electrode of the PMOS tube P6 is electrically connected with the drain electrode of the NMOS tube N6, the source electrode of the NMOS tube N6 is electrically connected with an NMOS bias voltage output end HVBN in the MOS bias circuit of the lifting circuit, the source electrode of the NMOS tube N6 is also electrically connected with the drain electrode of the NMOS tube N7, the grid electrode of the NMOS tube N7 is electrically connected with the drain electrode of the NMOS tube N8, and the drain electrode of the NMOS tube N7 is electrically connected with the drain electrode of the NMOS tube N8.

For the NAND gate circuit of FIG. 5, if the PMOS transistor P6 and the NMOS transistor N6 are omitted, the structure is a standard NAND gate structure, AH and AL are unified as one input A, BH and BL are unified as one input B, OUT-H and OUT-L are unified as one output OUT, and the logic isAccording to the above, after adding the voltage-resistant protection PMOS transistor P6, NMOS transistor N6 and the corresponding bias voltages HVBP, HVBN, the input A is split into AH and AL (the logic of AH and AL is the same, only the level is different), the input B is split into BH and BL (the logic of BH and BL is the same, only the level is different), the output OUT is split into the output OUT-H and the output OUT-L (the logic of OUT-H and OUT-L is the same, only the level is different), the logic of OUT-H and OUT-L is stillAll split input and output digital signals are used with the high-low level double-input inverter or other similar digital units in the previous examples or with the analog circuits such as the double-level comparator circuits in the previous examples. The standard NAND gate structure further improves the voltage resistance between the source and drain and the gate and source/drain/body, so that the digital circuit can work under the voltage of several times of original VDD.

In another embodiment, referring to fig. 6, the digital circuit of fig. 6 is a circuit schematic of a nor gate circuit. The NOR gate circuit comprises a PMOS tube P9, a PMOS tube P10, a PMOS tube P11, an NMOS tube N9, an NMOS tube N10 and an NMOS tube N11, wherein the source electrode of the PMOS tube P11 is electrically connected with a power supply end VDD, the grid electrode of the PMOS tube P11 is electrically connected with a first level input end AH, the drain electrode of the PMOS tube P11 is electrically connected with the source electrode of the PMOS tube P10, the grid electrode of the PMOS tube P10 is electrically connected with a second level input end BH, the drain electrode of the PMOS tube P10 is electrically connected with the source electrode of the PMOS tube P9, the drain electrode of the PMOS tube P10 is also electrically connected with an output end OUT-H, the grid electrode of the PMOS tube P10 is electrically connected with a PMOS bias voltage output end HVBP in a MOS bias circuit of a lifting circuit, the drain electrode of the NMOS tube P10 is electrically connected with a NMOS bias voltage output end HVBN in a MOS bias circuit of the lifting circuit, the source electrode of the NMOS tube N9 is electrically connected with the output end OUT-L, the drain electrode of the NMOS tube N9 and the drain electrode of the NMOS tube N10 are electrically connected with the drain electrode of the NMOS tube N9, the drain electrode of the NMOS tube N10 is electrically connected with the drain electrode of the NMOS tube N9 and the drain electrode of the NMOS tube N10 is electrically connected with the drain electrode of the NMOS tube N10, and the drain electrode of the NMOS tube is electrically connected with the drain electrode of the NMOS tube N10 is electrically connected with the drain electrode of the drain input tube.

For FIG. 6, if the PMOS transistor P9 and the NMOS transistor N9 are omitted, the structure is a standard NOR gate structure, AH and AL are unified as one input A, BH and BL are unified as one input B, OUT-H and OUT-L are unified as one output OUT, and the logic is thatAccording to the above, after adding the voltage-resistant protection PMOS transistor P9, NMOS transistor N9 and the corresponding bias voltages HVBP, HVBN, input A is split into AH and AL (the logic of AH and AL is the same, only the level is different), input B is split into BH and BL (the logic of BH and BL is the same, only the level is different), output OUT is split into OUT-H and OUT-L outputs (the logic of OUT-H and OUT-L is the same, only the level is different), and the logic of OUT-H and OUT-L is still>All split input and output digital signals are used with the high-low level double-input inverter or other similar digital units in the previous examples or with the analog circuits such as the double-level comparator circuits in the previous examples. The voltage withstanding between the source-drain and the gate-source/drain/body is further improved on the basis of a standard NOR gate structure, so that the digital circuit can work under the voltage of a plurality of times of original VDD.

Chip embodiment:

in this embodiment, the chip is provided with an analog circuit based on MOS transistor voltage withstand protection or a digital circuit based on MOS transistor voltage withstand protection, and the analog circuit based on MOS transistor voltage withstand protection is applied to the analog circuit in the above embodiment; the digital circuit based on MOS tube voltage-withstand protection is applied to the digital circuit in the above embodiment.

It should be noted that the foregoing is only a preferred embodiment of the present invention, but the design concept of the present invention is not limited thereto, and any insubstantial modifications made to the present invention by using the concept fall within the scope of the present invention.

Claims

1. A MOS bias circuit for improving circuit withstand voltage is characterized in that: the power supply device comprises a starting branch, a PMOS bias voltage generating branch and an NMOS bias voltage generating branch, wherein the starting branch, the PMOS bias voltage generating branch and the NMOS bias voltage generating branch are connected in parallel with a power supply end and a grounding end;

the PMOS bias voltage generation branch circuit comprises a first controlled switch circuit, a first bias generation module and a PMOS bias voltage output end, wherein the first bias generation module is provided with at least two PMOS tubes which are connected in series, the PMOS tubes are arranged in a diode connection mode, a first end of the first bias generation module is electrically connected with the power supply end, a second end of the first bias generation module is electrically connected with the grounding end through the first controlled switch circuit, and a second end of the first bias generation module is also electrically connected with the PMOS bias voltage output end;

the NMOS bias voltage generation branch circuit comprises a second controlled switch circuit, a second bias generation module and an NMOS bias voltage output end, wherein the second bias generation module is provided with at least two NMOS tubes which are connected in series, the NMOS tubes are arranged in a diode connection mode, a first end of the second bias generation module is electrically connected with the power supply end through the second controlled switch circuit, a second end of the second bias generation module is electrically connected with the grounding end, and a first end of the second bias generation module is also electrically connected with the NMOS bias voltage output end;

the start-up branch provides a start-up voltage to the first controlled switching circuit and/or the second controlled switching circuit.

2. The MOS bias circuit of claim 1 wherein the circuit withstand voltage is raised by:

the starting branch circuit comprises a first resistor, a second resistor, a first PMOS tube and a first NMOS tube, wherein the first end of the first resistor is electrically connected with the power supply end, the second end of the first resistor is electrically connected with the first end of the second resistor, the second end of the second resistor is electrically connected with the source electrode of the first PMOS tube, the grid electrode of the first PMOS tube is electrically connected with the grid electrode of the first NMOS tube, the drain electrode of the first PMOS tube is electrically connected with the drain electrode of the first NMOS tube, the grid electrode of the first PMOS tube is electrically connected with the drain electrode of the first PMOS tube, and the source electrode of the first NMOS tube is electrically connected with the ground end;

the first controlled switch circuit comprises a second NMOS tube and a third NMOS tube, wherein the drain electrode of the second NMOS tube is electrically connected with the second end of the first bias generation module, the grid electrode of the second NMOS tube is electrically connected with the first end of the second resistor, the source electrode of the second NMOS tube is electrically connected with the drain electrode of the third NMOS tube, the grid electrode of the third NMOS tube is electrically connected with the source electrode of the first PMOS tube, and the source electrode of the third NMOS tube is electrically connected with the grounding end.

3. The MOS bias circuit of claim 2 wherein the voltage withstand of the circuit is raised by:

the second controlled switch circuit comprises a second PMOS tube and a third PMOS tube, the source electrode of the second PMOS tube is electrically connected with the power supply end, the drain electrode of the second PMOS tube is electrically connected with the source electrode of the third PMOS tube, and the drain electrode of the third PMOS tube is electrically connected with the first end of the second bias generation module;

the first bias generation module is further provided with a first voltage output end and a second voltage output end, the first voltage output end is electrically connected with the grid electrode of the second PMOS tube, the second voltage output end is electrically connected with the grid electrode of the third PMOS tube, and the voltage output by the first voltage output end is larger than the voltage output by the second voltage output end.

4. A MOS bias circuit for boosting a withstand voltage of a circuit according to any one of claims 1 to 3, wherein:

in the first bias generation module, at least one PMOS tube and/or at least one resistor is connected in parallel with at least one of the PMOS tubes connected in series.

5. A MOS bias circuit for boosting a withstand voltage of a circuit according to any one of claims 1 to 3, wherein:

in the second bias generation module, at least one of the NMOS tubes connected in series is connected with at least one NMOS tube and/or at least one resistor in parallel.

6. A MOS bias circuit for boosting a withstand voltage of a circuit according to any one of claims 1 to 3, wherein:

a resistor is further arranged between the first end of the first bias generation module and the power end.

7. A MOS bias circuit for boosting a withstand voltage of a circuit according to any one of claims 1 to 3, wherein:

and a resistor is arranged between the second controlled switching circuit and the power supply end.

8. An analog circuit based on MOS pipe withstand voltage protection, its characterized in that: the MOS bias circuit comprises a PMOS tube to be protected, an NMOS tube for protection and a MOS bias circuit for improving the withstand voltage of the circuit, wherein the PMOS tube for protection is connected in series with the drain electrode of the PMOS tube to be protected, and the NMOS tube for protection is connected in series with the drain electrode of the NMOS tube to be protected;

the MOS bias circuit for improving circuit voltage resistance adopts the MOS bias circuit for improving circuit voltage resistance according to any one of claims 1 to 7, wherein the PMOS bias voltage output end is electrically connected with the grid electrode of the PMOS tube for protection, and the NMOS bias voltage output end is electrically connected with the grid electrode of the NMOS tube for protection.

9. A digital circuit based on MOS tube voltage-resistant protection is characterized in that: the MOS bias circuit comprises a PMOS tube to be protected, an NMOS tube for protection and a MOS bias circuit for improving circuit withstand voltage, wherein the PMOS tube for protection is connected in series with the drain electrode of the PMOS tube to be protected, and the NMOS tube for protection is connected in series with the drain electrode of the NMOS tube to be protected;

10. The utility model provides a chip is provided with the analog circuit based on MOS pipe withstand voltage protection or the digital circuit based on MOS pipe withstand voltage protection, its characterized in that: the analog circuit based on MOS tube voltage-resistant protection is applied to the analog circuit of claim 8;

the digital circuit based on MOS tube voltage-resistant protection applies the digital circuit of claim 9.