CN116455337A - Amplifier system and power converter - Google Patents

Amplifier system and power converter Download PDF

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Publication number
CN116455337A
CN116455337A CN202310037097.2A CN202310037097A CN116455337A CN 116455337 A CN116455337 A CN 116455337A CN 202310037097 A CN202310037097 A CN 202310037097A CN 116455337 A CN116455337 A CN 116455337A
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CN
China
Prior art keywords
switch
inductor
supply voltage
period
voltage
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CN202310037097.2A
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Chinese (zh)
Inventor
黄奕玮
温松翰
陈冠达
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MediaTek Inc
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MediaTek Inc
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Priority claimed from US18/085,579 external-priority patent/US20230231523A1/en
Application filed by MediaTek Inc filed Critical MediaTek Inc
Publication of CN116455337A publication Critical patent/CN116455337A/en
Pending legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/181—Low-frequency amplifiers, e.g. audio preamplifiers
    • H03F3/183—Low-frequency amplifiers, e.g. audio preamplifiers with semiconductor devices only
    • H03F3/187—Low-frequency amplifiers, e.g. audio preamplifiers with semiconductor devices only in integrated circuits
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/156—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/03—Indexing scheme relating to amplifiers the amplifier being designed for audio applications

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Multimedia (AREA)
  • Amplifiers (AREA)

Abstract

The invention provides an amplifier system comprising an audio amplifier and a power converter. The audio amplifier is powered by at least a first power supply voltage and a second power supply voltage, the audio amplifier being configured to receive an audio signal to generate an output signal. The power converter includes only one inductor and is configured to generate a first power voltage and a second power voltage according to an input voltage. The invention can reduce the outline dimension and the manufacturing cost of the power converter.

Description

Amplifier system and power converter
Technical Field
Embodiments of the present disclosure relate generally to amplification (e.g., audio amplification) technology, and more particularly, to an amplifier system and power converter.
Background
In conventional audio amplifiers, the audio amplifier requires two or more supply voltages to process a digital input audio signal to produce an analog output audio signal. In order to generate two or more power supply voltages, power converters are typically designed with two or more inductors, which increases the overall size and manufacturing costs.
Disclosure of Invention
It is therefore an object of the present invention to provide an amplifier system and a related power converter, wherein the power converter can use only one inductor to generate two or three power voltages for the amplifier, thus having smaller overall dimensions and manufacturing costs.
According to one embodiment of the present invention, an amplifier system including an amplifier and a power converter is disclosed. An amplifier is powered by at least a first supply voltage and a second supply voltage, the amplifier being configured to receive an input signal (e.g., an audio signal) to generate an output signal. The power converter includes only one inductor and is configured to generate a first power voltage and a second power voltage according to an input voltage.
In some embodiments, the first power supply voltage and the second power supply voltage are power supply voltages that are variable according to the input signal or a derivative of the input signal.
In some embodiments, the power converter includes: an inductor having a first end selectively coupled to the input voltage or the first supply voltage and a second end selectively coupled to the second supply voltage.
In some embodiments, the input voltage is input to the inductor during a first period of time, and an inductor current increases; in a second period after the first period, the input voltage is disconnected from the inductor and the second supply voltage is coupled to the first supply voltage through the inductor, the inductor current decreasing; and in a third period subsequent to the second period, the input voltage, the first supply voltage, and the second supply voltage are all disconnected from the inductor.
In some embodiments, the power converter further comprises: a first switch for selectively connecting the input voltage to the first end of the inductor; a second switch for selectively connecting the second end of the inductor to ground voltage; a third switch for selectively connecting the second end of the inductor to the second supply voltage; a fourth switch for selectively connecting the first end of the inductor to the first supply voltage; and a fifth switch for selectively connecting the first end of the inductor to the ground voltage.
In some embodiments, in a first period, the first switch and the second switch are on, the third switch, the fourth switch, and the fifth switch are off, the input voltage is input to the inductor, and an inductor current increases; in a second period after the first period, the third switch and the fourth switch are on, the first switch, the second switch and the fifth switch are off, the second supply voltage is coupled to the first supply voltage through the inductor, and inductor current decreases; and in a third period subsequent to the second period, the second switch and the fifth switch are on, and the first switch, the third switch and the fourth switch are off.
In some embodiments, the second switch comprises a large switch and a small switch, wherein the large switch and the small switch are implemented by a transistor and a width of a channel of the large switch is greater than a width of a channel of the small switch, the large switch configured to selectively connect the second end of the inductor to the ground voltage, the small switch configured to selectively connect the second end of the inductor to the ground voltage; and in the third period after the second period, only the small switch of the second switches is turned on and the large switch is turned off.
In some embodiments, the fifth switch comprises a large switch and a small switch, wherein the large switch and the small switch are implemented by a transistor and a width of a channel of the large switch is greater than a width of a channel of the small switch, the large switch configured to selectively connect the first end of the inductor to the ground voltage, the small switch configured to selectively connect the first end of the inductor to the ground voltage; and in the third period after the second period, only the small switch of the fifth switch is turned on and the large switch is turned off.
In some embodiments, the amplifier is powered by the first power supply voltage, the second power supply voltage, and a negative power supply voltage, the power converter being configured to generate the first power supply voltage, the second power supply voltage, and the negative power supply voltage based on the input voltage, wherein the first power supply voltage and the second power supply voltage are power supply voltages that are variable based on the input signal or derived signals of the input signal, the negative power supply voltage being desired to have a fixed voltage level.
In some embodiments, the power converter includes: an inductor having a first end and a second end;
a first switch for selectively connecting the input voltage to the first end of the inductor; a second switch for selectively connecting the second end of the inductor to ground voltage; a third switch for selectively connecting the first end of the inductor to the first supply voltage; a fourth switch for selectively connecting the second end of the inductor to the second supply voltage; a fifth switch for selectively connecting the first end of the inductor to the negative supply voltage; and a sixth switch for selectively connecting the first end of the inductor to the ground voltage.
In some embodiments, in a first period, the first switch and the second switch are on, the third switch, the fourth switch, the fifth switch, and the sixth switch are off, the input voltage is input to the inductor, and an inductor current increases; in a second period after the first period, the third switch and the fourth switch are on, the first switch, the second switch, the fifth switch, and the sixth switch are off, the second supply voltage is coupled to the first supply voltage through the inductor, and the inductor current decreases; in a third period after the second period, the second switch and the sixth switch are on, and the first switch, the third switch, the fourth switch and the fifth switch are off.
In some embodiments, in a first period, the first switch and the second switch are on, the third switch, the fourth switch, the fifth switch, and the sixth switch are off, the input voltage is input to the inductor, and an inductor current increases; in a second period after the first period, the third switch and the fifth switch are on, the first switch, the second switch, the fourth switch, and the sixth switch are off, a third supply voltage is coupled to the first supply voltage through the inductor, and the inductor current decreases; in a third period after the second period, the second switch and the sixth switch are on, and the first switch, the third switch, the fourth switch and the fifth switch are off.
In some embodiments, the on-resistance of the large switch is less than the on-resistance of the small switch.
In some embodiments, the amplifier is an audio amplifier, and the input signal is an audio signal input to the audio amplifier.
According to an embodiment of the invention, a power converter is also disclosed. The power converter is configured to receive an input voltage to generate a first power voltage, a second power voltage, and a third power voltage, and includes an inductor, a first switch, a second switch, a third switch, a fourth switch, a fifth switch, and a sixth switch. The inductor has a first end and a second end. The first switch is configured to selectively connect the input voltage to a first end of the inductor. The second switch is configured to selectively connect the second end of the inductor to ground voltage. The third switch is configured to selectively connect the second end of the inductor to the first supply voltage. The fourth switch is configured to selectively connect the first end of the inductor to the second supply voltage; the fifth switch is configured to selectively connect the first end of the inductor to a third supply voltage; and a sixth switch for selectively connecting the first end of the inductor to the ground voltage.
In some embodiments, in a first period, the first switch and the second switch are on, the third switch, the fourth switch, the fifth switch, and the sixth switch are off, the input voltage is input to the inductor, and an inductor current increases; in a second period after the first period, the third switch and the fourth switch are on, the first switch, the second switch, the fifth switch, and the sixth switch are off, the second supply voltage is coupled to the first supply voltage through the inductor, and the inductor current decreases; in a third period after the second period, the second switch and the sixth switch are on, and the first switch, the third switch, the fourth switch and the fifth switch are off.
In some embodiments, the sixth switch comprises a large switch and a small switch, wherein the large switch and the small switch are implemented by a transistor and a width of a channel of the large switch is greater than a width of a channel of the small switch, the large switch configured to selectively connect the first end of the inductor to the ground voltage, the small switch configured to selectively connect the first end of the inductor to the ground voltage; in a third period after the second period, only the small switch of the sixth switch is on and the large switch is off.
In some embodiments, the second switch comprises a large switch and a small switch, wherein the large switch and the small switch are implemented by a transistor and a width of a channel of the large switch is greater than a width of a channel of the small switch, the large switch configured to selectively connect the second end of the inductor to the ground voltage, the small switch configured to selectively connect the second end of the inductor to the ground voltage; in a third period after the second period, only the small switch of the second switches is on and the large switch is off.
In some embodiments, the first supply voltage, the second supply voltage, and the third supply voltage are used to power an amplifier, the third supply voltage being a negative supply voltage, wherein the first supply voltage and the second supply voltage are supply voltages that are variable according to an input signal of the amplifier or a derivative of the input signal, the negative supply voltage being desired to have a fixed voltage level.
In some embodiments, the on-resistance of the large switch is less than the on-resistance of the small switch.
These and other objects of the present invention will be readily understood by those skilled in the art after reading the following detailed description of the preferred embodiments as illustrated in the accompanying drawings. The detailed description will be given in the following embodiments with reference to the accompanying drawings.
Drawings
The present invention will become more fully understood from the detailed description given herein below and the accompanying drawings, wherein:
fig. 1 shows a schematic diagram of an amplifier system according to an embodiment of the invention.
Fig. 2 shows the supply voltage of the audio amplifier for a class G amplifier and a class H amplifier.
Fig. 3 shows a schematic diagram of a power converter according to an embodiment of the invention.
Fig. 4 illustrates a control method of a power converter according to an embodiment of the present invention.
Fig. 5 shows inductor current in a power converter according to an embodiment of the invention.
Fig. 6 illustrates a control method of a power converter according to an embodiment of the present invention.
Fig. 7 shows a schematic diagram of another power converter according to an embodiment of the invention.
In the following detailed description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of embodiments of the invention. It will be apparent, however, that one or more embodiments may be practiced without these specific details, and that different embodiments may be combined as desired and should not be limited to the embodiments set forth in the drawings.
Detailed Description
The following description is of preferred embodiments of the invention, which are intended to illustrate the technical features of the invention, but not to limit the scope of the invention. Certain terms are used throughout the description and claims to refer to particular elements, and it will be understood by those skilled in the art that manufacturers may refer to a like element by different names. Therefore, the present specification and claims do not take the difference in names as a way of distinguishing elements, but rather take the difference in functions of elements as a basis for distinction. The terms "element," "system," and "apparatus" as used in the present invention may be a computer-related entity, either hardware, software, or a combination of hardware and software. In the following description and in the claims, the terms "include" and "comprise" are used in an open-ended fashion, and thus should be interpreted to mean "include, but not limited to …". Furthermore, the term "coupled" means an indirect or direct electrical connection. Thus, if one device is coupled to another device, that device can be directly electrically connected to the other device or indirectly electrically connected to the other device through other devices or connection means.
Wherein corresponding numerals and symbols in the various drawings generally refer to corresponding parts, unless otherwise indicated. The drawings are clearly illustrative of relevant portions of the embodiments and are not necessarily drawn to scale.
The term "substantially" or "approximately" as used herein means that within an acceptable range, a person skilled in the art can solve the technical problem to be solved, substantially to achieve the technical effect to be achieved. For example, "substantially equal" refers to a manner in which a technician can accept a certain error from "exactly equal" without affecting the accuracy of the result.
Fig. 1 is a schematic diagram of an amplifier system (amplifier system) 100 according to an embodiment of the invention. The embodiment shown in fig. 1 illustrates an audio amplifier system 100, but the embodiments of the present invention are not limited to audio systems, and any amplifier system requiring application to two or three power supply voltages may employ the techniques provided by the embodiments of the present invention, and therefore, the present invention should not be limited to audio applications/systems. Thus, in some variant embodiments, the description of the audio signal, audio amplifier 110 shown in fig. 1, may be replaced with a description of the input signal, amplifier 110, accordingly. As shown in fig. 1, the amplifier system 100 includes an audio amplifier (audio amplifier) 110 and a power converter (power converter) 120, wherein the audio amplifier 110 includes a low dropout regulator (low dropout regulator, LDO) 112, a digital-to-analog converter (DAC) 114, a regulator 116, and a power amplifier (power amplifier) 118.LDO 112 and voltage regulator 116 are configured to provide a supply voltage (also referred to as a "supply voltage") to DAC 114 for DAC 114 to perform a digital-to-analog conversion operation on an audio signal to generate an analog signal, and power amplifier 118 amplifies the analog signal and generates an output signal Vout to drive a speaker (resistor RL is considered as a load or an equivalent resistance of the speaker), that is, the analog signal generated by DAC 114 and the output signal Vout generated by power amplifier 118 (e.g., analog output signal) are related to an input audio signal (e.g., digital audio signal), and it is understood that the analog signal generated by DAC 114 and the output signal Vout generated by power amplifier 118 may be considered as derivative signals of the input audio signal. The desired level of the supply voltages PVDD, PVSS is related to the input signal of the amplifier 110 and/or a derivative signal of the input signal (which may be, for example, in the embodiment shown in fig. 1, the input audio signal, the intermediate generated analog signal and the output signal Vout, as will be appreciated, these 3 signals are related to the signal processed by the amplifier 110). In this embodiment, amplifier system 100 is powered by four different supply voltages (voltage VI, VN, PVDD, PVSS as shown in fig. 1), with input voltage VI being provided to LDO 112, negative supply voltage (negative supply voltage) VN being provided to regulator 116, and supply voltages PVDD and PVSS being provided to power amplifier 118. In addition, the power converter 120 is configured to receive the input voltage VI to generate other power supply voltages PVDD, PVSS, and VN.
In one embodiment, the negative supply voltage VN has a fixed (fixed) voltage level (also referred to as a "voltage level" or "level"), and the supply voltages PVDD and PVSS are signal-dependent supply voltages (signal-dependent supply voltage), e.g., PVDD and PVSS vary according to the audio signal. That is, in the embodiment of the present invention, the power supply voltages PVDD and PVSS are power supply voltages that are variable according to the input signal of the amplifier 110 or the derivative signal of the input signal, and in particular, in an example embodiment, PVDD is a variable positive power supply voltage, PVSS is a variable negative power supply voltage, and VN is desired to be a fixed negative power supply voltage. For example, referring to fig. 2, in the example of fig. 2, the power amplifier 118 is a class-G (class-G) amplifier or a class-H (class-H) amplifier (but the invention is not limited to this example) that supports being powered by a plurality of power rails (power rails) of different voltage levels, and the power supply voltage PVDD/PVSS level of at least one power rail is controlled according to information (information) of the audio signal. For example, in some embodiments, the supply voltage VN is determined to have a fixed desired voltage level, and in addition, the desired level of the supply voltages PVDD, PVSS is determined from any one of the input signal of the amplifier 110 (e.g., an input audio signal) and a derivative signal of the input signal (e.g., an intermediate signal generated by the input signal, the output signal Vout generated by the amplifier 110). For ease of understanding and explanation, fig. 2 illustrates an example of the output signal Vout (i.e., the derivative signal of the input signal of the amplifier 110), and as shown in fig. 2, the desired voltage levels of the power supply voltages PVDD, PVSS vary according to the signal Vout. For example, taking a class G amplifier as an example, the power supply voltages PVDD and PVSS may have two desired voltage levels (may also be described as "voltage levels"), and more particularly, the absolute values of the positive power supply voltage PVDD and the negative power supply voltage PVSS are equal, but the invention is not limited thereto. Further, in the example plot of the class G amplifier of fig. 2, PVDD is expected to be a first voltage level when the absolute value of the signal Vout is within a preset value; when the absolute value of the signal Vout is greater than the preset value, the PVDD is expected to have the second voltage level. As another example, in the example plot of the class H amplifier of fig. 2, PVDD is expected to be a first voltage level when the absolute value of the signal Vout is within a preset value; when the absolute value of the signal Vout is greater than the preset value, the voltage level of the PVDD is expected to track the waveform of the signal Vout (e.g., slightly greater than the voltage value of the signal Vout). As can be seen from fig. 2: the desired level of the supply voltages PVDD, PVSS, determined from the signal processed by the amplifier 110 (e.g., the input signal or a derivative of the input signal), is different. It should be noted that the present invention does not impose any limitation on how the desired level of the power supply voltage PVDD, PVSS, VN is specifically set, but focuses on how the power supply voltage PVDD, PVSS, VN is controlled to be maintained at the corresponding desired level.
Fig. 3 is a schematic diagram of a power converter 120 according to an embodiment of the invention. As shown in fig. 3, the power converter 120 includes an input capacitor (input capacitor) C1, an inductor (inductor) L, three output capacitors C2-C4, and a plurality of switches SW1-SW6. The input capacitor C1 is coupled between the node N1 and a ground voltage (ground voltage), the output capacitor C2 is coupled between the node N4 and the ground voltage, the output capacitor C3 is coupled between the node N5 and the ground voltage, and the output capacitor C4 is coupled between the node N6 and the ground voltage. Switch SW1 is coupled between node N1 and node N2, and switch SW1 is configured to selectively connect the input voltage (i.e., supply voltage VI) to the first end of inductor L. The switch SW6 is coupled between the node N2 and the ground voltage, and the switch SW6 is configured to selectively connect the first terminal of the inductor L to the ground voltage. The switch SW3 is coupled between the node N3 and the node N4, and the switch SW3 is configured to selectively connect the second terminal of the inductor L to the node N4 to adjust the voltage level of the (adjust) power supply voltage PVDD. Switch SW2 is coupled between node N3 and ground voltage, and switch SW2 is configured to selectively connect the second terminal of inductor L to ground voltage. The switch SW4 is coupled between the node N2 and the node N5, and the switch SW4 is configured to selectively connect the first terminal of the inductor L to the node N5 to adjust the voltage level of the power supply voltage PVSS. Switch SW5 is coupled between node N2 and node N6, and switch SW5 is configured to selectively connect the first terminal of inductor L to node N6 to stabilize the voltage level of the (stabilize) negative supply voltage VN.
In the power converter 120 shown in fig. 3, since only one inductor L is used (only one inductor L is used) to generate the power supply voltages PVDD, PVSS and the negative power supply voltage VN, the external dimensions and manufacturing costs of the power converter 120 can be reduced. In addition, the control of the switches SW1-SW6 is based on the desired level of the supply voltage PVDD, PVSS, VN and the actual voltage level of the supply voltage PVDD, PVSS, VN, and the current of the inductor L is controlled by controlling the switches SW1-SW6 to produce the supply voltage PVDD, PVSS, VN having the appropriate voltage level (e.g., which would ideally be the same as the desired voltage level), so that the power converter 120 will have a higher efficiency. Details are described below.
For example, when the load RL shown in fig. 1 is a full-bridge load (full-bridge load), a current path (current path) exists between the power supply voltages PVDD and PVSS through the load RL, so that the level (level may be described as "level") of the positive power supply voltage PVDD will drop (drop), and the level of the negative power supply voltage PVSS will rise (rise); in addition, there is a current path between the negative supply voltage VN and the ground voltage via the voltage regulator and the DAC, so that the voltage level of the negative supply voltage VN will rise. That is, over time, the supply voltage PVDD, PVSS, VN will gradually deviate from a desired voltage level (which may also be described as a "desired level"). In order to have the supply voltages PVDD and PVSS have a desired voltage level for a higher efficiency and to have the negative supply voltage VN regulated at its desired level, fig. 4 shows a control method of the switches SW1-SW6 according to an embodiment of the present invention. Referring to fig. 4 and 5 together, for example, in an example embodiment, when at least one of the supply voltages PVDD, PVSS, VN is below its desired level (e.g., when the supply voltage PVDD is below the desired level), the power converter 120 enters control of a first period of time (e.g., the duration of the first period of time may be set by a timer). During a first period (also referred to as a "phase"), switches SW1 and SW2 are enabled (enabled, also referred to as "on" or "off"), and switches SW3-SW6 are disabled (disabled, also referred to as "off" or "on"). At this time, current flows from node N1 to ground voltage via switch SW1, node N2, inductor L, node N3 and switch SW2, and inductor current I L Increase (i.e., rise). After the first period of time has elapsed,control of the second period is entered when the positive supply voltage PVDD is lower than a desired level of PVDD and the negative supply voltage PVSS is higher than a desired level of PVSS. In a second period after the first period, the switches SW4 and SW3 are enabled, and the switches SW1, SW2, SW5 and SW6 are disabled. At this time, current flows from the node N5 to the node N4 via the switch SW4, the node N2, the inductor L, the node N3, the switch SW3, and the inductor current I L Decreasing (i.e., dropping). In the second period, since the positive supply voltage PVDD is coupled to the negative supply voltage PVSS through the inductor L, the inductor current I L Will decrease due to the voltage difference across the inductor L. For example, the slope of the inductor current drop is equal to
Referring to fig. 5, in the first period and the second period, the on-power loss (conduction power loss) of the switch may be expressed by the following formula:
wherein "P cond "is conduction power loss," I pk "is inductor current I L Peak of (peak), "T ON Pointer to inductor current I L Rise time, "T OFF Pointer to inductor current I L Time of drop, "T SW "is a switching period (switching period), for example, a sum of times embodied for the first period, the second period, and the third period," R on "is the on-resistance of each switch (assuming that the on-resistance of each switch is the same). Since the falling gradient of the inductor current is larger than that of the conventional control method (for example, it turns on only the switches SW6 and SW3 to raise the power supply voltage PVDD level in the second period, or turns on only the switches SW4 and SW2 to lower the power supply voltage PVSS level in the second period), the parameter "T" in the formula (1) OFF The value of "will have a smaller (smaler) value than the conventional control method, thereby turning the power supplyThe switches in the converter 120 have lower (lower) on-power losses.
Further, in the second period, the power supply voltage PVDD rises and the power supply voltage PVSS falls, and therefore, the efficiency of the power converter 120 can be improved.
When the inductor current I L When falling to zero, the power converter 120 switches from the second period to the third period. In a third period after the second period, switches SW6 and SW2 are enabled and switches SW1, SW3-SW5 are disabled. At this time, both ends of the inductor L are connected to the ground voltage, so that the inductor current I L And maintained at zero. After the third period of time, the switches SW1-SW6 may be controlled at the desired level and the actual voltage level of the supply voltages PVDD, PVSS and the negative supply voltage VN. For example, the power converter 120 may perform the operations corresponding to the first to third periods again. It will be appreciated that in another variant embodiment, the power converter 120 may also enter the control of the first, second and third periods as shown in fig. 4 when the positive power supply voltage PVDD is lower than the desired level of PVDD and the negative power supply voltage PVSS is higher than the desired level of PVSS.
In another embodiment, fig. 6 illustrates a control method of the switches SW1-SW6 according to an embodiment of the present invention when the level of the supply voltage PVDD is lower than the desired level of PVDD and the negative supply voltage VN is higher than the desired level of VN. Referring to fig. 6, when at least one of the power supply voltages PVDD, PVSS, VN is below its desired level (e.g., when the power supply voltage PVDD is below the desired level), the power converter 120 enters control of a first period (e.g., the duration of the first period may be set by a timer). In the first period, the switches SW1 and SW2 are enabled/turned on, and the switches SW3 to SW6 are disabled/turned off. At this time, current flows from the node N1 to the ground voltage via the switch SW1, the node N2, the inductor L, the node N3 and the switch SW2, and the inductor current I L Increasing. After the first period, when the level of the power supply voltage PVDD is lower than the desired level of PVDD and the negative power supply voltage VN is higher than the desired level of VN, control for the second period is entered. In a second period after the first period, the switches SW5 and SW3 are turned on/off, and the switches SW1, SW2, SW4 and SW6 is disabled/disconnected. At this time, current flows from the node N6 to the node N4 via the switch SW5, the node N2, the inductor L, the node N3, the switch SW3, and the inductor current I L And (3) reducing. In the second period, since the positive supply voltage PVDD is coupled to the negative supply voltage VN through the inductor L, the inductor current I L Will decrease due to the voltage difference across the inductor L. Referring to equation (1) above, since the slope of the inductor current drop is large in this embodiment, the parameter "T" in equation (1) OFF "will have a smaller value, resulting in lower on-power loss for the switches in the power converter 120.
When the inductor current I L When falling to zero, the power converter 120 switches from the second period to the third period. In a third period after the second period, the switches SW6 and SW2 are enabled/turned on, and the switches Sl, SW3 to SW5 are disabled/turned off. At this time, both ends of the inductor L are connected to the ground voltage so that the inductor current I L Becomes zero. After the third period of time, the switches SW1-SW6 may be controlled based on the desired level and the actual voltage level of the supply voltages PVDD, PVSS and the negative supply voltage VN. For example, the power converter 120 may perform the operations corresponding to the first to third periods again. It will be appreciated that in other embodiments, the power converter 120 may also perform the control of the first, second and third periods as shown in fig. 6 when the positive power supply voltage PVDD is lower than the desired level of PVDD and the negative power supply voltage VN is higher than the desired level of VN.
In another example scenario, when the positive supply voltage PVDD is below the desired level of PVDD and the negative supply voltages PVSS and VN are both above their respective desired levels, the switches SW4 and SW3 may be selected to be on, or the switches SW5 and SW3 may be selected to be on, with the other switches being off, in the second period described above. For example, one of the supply voltages (e.g., VN) may be selected to be coupled with PVDD based on the importance or priority levels of the supply voltages PVSS and VN. In another example scenario, when the negative supply voltage PVSS is higher than the desired level of PVSS but both supply voltages PVDD, VN agree with their desired levels, the negative supply voltage PVSS may be reduced by turning on switches SW4 and SW 2. Accordingly, when the negative supply voltage VN is higher than the desired level of VN but both supply voltages PVDD, PVSS agree with their desired levels, the negative supply voltage VN can be lowered by turning on the switches SW5 and SW 2.
In the above-described embodiments of fig. 4 to 6, the power converter 120 can reduce on-power loss and improve efficiency by connecting the power supply voltage PVSS to the power supply voltage PVDD or connecting the negative power supply voltage VN to the power supply voltage PVDD in the second period. However, since the power converter 120 of the present embodiment has a large number of switching times, for example, 6 periods shown in fig. 4 or 6 have eleven switching times, the power converter 120 may have a high switching power loss (switching power loss). To address this problem, each of the switches SW2 and SW6 may be implemented with a transistor, for example, with a P-channel metal oxide semiconductor (P-channel Metal Oxide Semiconductor, PMOS) transistor or an N-channel metal oxide semiconductor (N-channel Metal Oxide Semiconductor, NMOS) transistor. Further, each of the switches SW2 and SW6 may be designed to have a large-sized switch (which may also be described as a "large switch") and a small-sized switch (which may also be described as a "small switch"), wherein the switching power loss of the small-sized switch is smaller than that of the large-sized switch, and only the small-sized switch of the switches SW2 and SW6 is enabled in the third period to reduce the switching power loss. It should be noted that, in the embodiment of the present invention, the large-size switch refers to a larger width (W) of the channel, and the small-size switch refers to a smaller width (W) of the channel, for example, a channel width-length product (i.e., a channel width-length) of the large-size switch is larger than a channel width-length product of the small-size switch. The applicant has appreciated that: the larger the width of the transistor channel, the larger the gate capacitance Cg of the transistor, and thus the larger the switching power loss of the transistor when acting as a switch; conversely, the smaller the width of the transistor channel, the smaller the switching power loss when the transistor is switched. In an example, the channel lengths (L) of the large-size switch and the small-size switch are the same, and the sizes of the switches are made different by setting different channel widths (W), so that the channel width-to-length ratio (W/L) of the large-size switch is larger than that of the small-size switch, and further, in this example, the on-resistance of the large-size switch is smaller than that of the small-size switch, but the on-resistance relationship of the large-size switch and the small-size switch is not limited to this example. In particular, referring to fig. 7, the switch SW6 shown in fig. 3 can be implemented by using a large switch SW6L and a small switch SW6S, wherein the large switch SW6L is coupled between the node N2 and the ground voltage, and the small switch SW6S is coupled between the node N2 and the ground voltage. In this embodiment, the large switch SW6L is large in size (i.e. width of channel) and optionally small in resistance when on; the small switch SW6S is small in size (i.e., width of channel) and, optionally, large in resistance when on. Similarly, the switch SW2 shown in fig. 3 may be implemented using a large switch SW2L and a small switch SW2S, wherein the large switch SW2L is coupled between the node N2 and the ground voltage and the small switch SW2S is coupled between the node N2 and the ground voltage. In the present embodiment, the large switch SW2L is large in size, and alternatively, small in resistance when on; the small switch SW2S is small in size and, optionally, large in resistance when on.
In the embodiment shown in fig. 7, when the level of the power supply voltage PVDD is lower than the desired level of PVDD and the power supply voltage PVSS is higher than the desired level of PVSS, the switches SW1 and SW2 are enabled (at least the large switch SW2L is enabled in the switch SW 2) and the switches SW3 to SW6 are disabled in the first period (for example, may have a predetermined period of time set by a timer). At this time, current flows from the node N1 to the ground voltage via the switch SW1, the node N2, the inductor L, the node N3 and the switch SW2, and the inductor current I L Increasing. In a second period after the first period, the switches SW4 and SW3 are enabled, and the switches SW1, SW2, SW5 and SW6 are disabled. At this time, current flows from the node N5 to the node N4 via the switch SW4, the node N2, the inductor L, the node N3, the switch SW3, and the inductor current I L And (3) reducing. In a third period after the second period, only the small switches SW6S and SW2S are enabled, and the switches S1, SW3-SW5, the large switches SW6L and SW2L are disabled. At this time, both ends of the inductor L are connected to the ground voltage so that the inductor current I L Becomes zero. After a third period of time, the voltage of the audio signal, the power supply voltages PVDD, PVSS and the negative power supply voltage VN can be electrically calculated The switches SW1-SW6 are controlled in parallel. For example, the power converter 120 may perform the operations corresponding to the first to third periods again.
In another embodiment shown in fig. 7, when the level of the supply voltage PVDD is lower than the desired level of PVDD and the negative supply voltage VN is higher than the desired level of VN, in a first period (for example, which may have a predetermined duration of a timer setting), the switches SW1 and SW2 are enabled (in the switch SW2, at least the large switch SW2L is enabled), and the switches SW3-SW6 are disabled. At this time, current flows from the node N1 to the ground voltage via the switch SW1, the node N2, the inductor L, the node N3 and the switch SW2, and the inductor current I L Increasing. In a second period after the first period, the switches SW5 and SW3 are enabled, and the switches SW1, SW2, SW4 and SW6 are disabled. At this time, current flows from the node N6 to the node N4 via the switch SW5, the node N2, the inductor L, the node N3, the switch SW3, and the inductor current I L And (3) reducing. In a third period after the second period, only the small switches SW6S and SW2S are enabled, and the switches S1, SW3-SW5, the large switches SW6L and SW2L are disabled. At this time, both ends of the inductor L are connected to the ground voltage so that the inductor current I L Becomes zero. After the third period of time, the switches SW1-SW6 may be controlled according to the desired level and the actual voltage level of the supply voltages PVDD, PVSS and the negative supply voltage VN. For example, the power converter 120 may perform the operations corresponding to the first to third periods again.
In both embodiments described above, due to the inductor current I L In the third period described above, zero is present, and therefore, on-power loss is not generated although the on-resistances of the small switches SW6S and SW2S are large. In addition, since the switching power loss of the small switches SW6S and SW2S is low, by enabling only the small switches SW6S and SW2S in the third period, the switching power loss as a whole can be effectively reduced.
In the above-described embodiment, the power converter 120 is configured to receive the input voltage VI to generate three power supply voltages PVDD, PVSS, and VN. In another embodiment, the switch SW5 and the output capacitor C4 may be removed from the power converter 120, i.e. the power converter 120 is configured to receive the input voltage VI to generate the two supply voltages PVDD and PVSS. Such alternative designs are also intended to fall within the scope of the present invention. That is, although the drawings show a structure in which 3 power supply voltages PVDD, PVSS, VN are generated from the input power supply voltage VI using a single inductor, 2 power supply voltages may be generated therein in a modified embodiment, and should not be limited to only the specific example in which 3 power supply voltages are generated in the drawings. Thus, in the modified embodiment, the respective switches and output capacitors are optional (i.e., the switch SW5 and the output capacitor C4 may be removed, for example, to generate 2 power supply voltages PVDD, PVSS), and the description of these modified embodiments will not be repeated since the principle of the modified embodiment is similar to that of the above-described embodiment.
In short, in the power converter of the amplifier system of the present invention, only one inductor is used to generate two or three power supply voltages, and therefore, the manufacturing cost of the power converter can be reduced. In addition, by using the specific switch control method/structure proposed in the embodiment of the present invention, the efficiency of the power converter can be improved, the on-power loss can be reduced, and the switching power loss can be reduced.
In the claims, ordinal terms such as "first," "second," "third," etc., are used to modify a claim element, and do not by itself connote any priority, precedence, or order of one claim element over another or the temporal order in which acts of a method are performed, but are used merely as labels to distinguish one claim element having a same name from another element having a same name using the ordinal term.
Although embodiments of the present invention and their advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit of the invention and the scope of the appended claims, e.g., new embodiments can be derived by combining several of the different embodiments. The described embodiments are to be considered in all respects only as illustrative and not restrictive. The scope of the invention is defined by the appended claims. Those skilled in the art will appreciate that many modifications and variations are possible without departing from the spirit and scope of the invention.
While the invention has been described by way of example and in terms of preferred embodiments, it is to be understood that the invention is not limited to the disclosed embodiments. On the contrary, it is intended to cover various modifications and similar arrangements (as will be apparent to those skilled in the art), e.g., combinations or alternatives of the different features in the different embodiments. The scope of the following claims is, therefore, to be accorded the broadest interpretation so as to encompass all such modifications and similar structures.

Claims (20)

1. An amplifier system, comprising:
an amplifier powered by at least a first power supply voltage and a second power supply voltage, configured to receive an input signal to generate an output signal; the method comprises the steps of,
a power converter having only one inductor is configured to generate the first power voltage and the second power voltage according to an input voltage.
2. The amplifier system of claim 1, wherein the first supply voltage and the second supply voltage are supply voltages that are variable according to the input signal or a derivative of the input signal.
3. The amplifier system of claim 1, wherein the power converter comprises:
An inductor having a first end selectively coupled to the input voltage or the first supply voltage and a second end selectively coupled to the second supply voltage.
4. The amplifier system of claim 3, wherein the input voltage is input to the inductor and an inductor current increases during a first period of time; in a second period after the first period, the input voltage is disconnected from the inductor and the second supply voltage is coupled to the first supply voltage through the inductor, the inductor current decreasing; and in a third period subsequent to the second period, the input voltage, the first supply voltage, and the second supply voltage are all disconnected from the inductor.
5. The amplifier system of claim 3, wherein the power converter further comprises:
a first switch for selectively connecting the input voltage to the first end of the inductor;
a second switch for selectively connecting the second end of the inductor to ground voltage;
a third switch for selectively connecting the second end of the inductor to the second supply voltage;
A fourth switch for selectively connecting the first end of the inductor to the first supply voltage; the method comprises the steps of,
and a fifth switch for selectively connecting the first end of the inductor to the ground voltage.
6. The amplifier system of claim 5, wherein in a first period, the first switch and the second switch are on, the third switch, the fourth switch, and the fifth switch are off, the input voltage is input to the inductor, and an inductor current increases; in a second period after the first period, the third switch and the fourth switch are on, the first switch, the second switch and the fifth switch are off, the second supply voltage is coupled to the first supply voltage through the inductor, and inductor current decreases; and in a third period subsequent to the second period, the second switch and the fifth switch are on, and the first switch, the third switch and the fourth switch are off.
7. The amplifier system of claim 6, wherein the second switch comprises a large switch and a small switch, wherein the large switch and the small switch are implemented by transistors and a width of a channel of the large switch is greater than a width of a channel of the small switch, the large switch configured to selectively connect the second end of the inductor to the ground voltage by 5, the small switch configured to selectively connect the second end of the inductor to the ground voltage; and in the third period after the second period, only the small switch of the second switches is turned on and the large switch is turned off.
8. The amplifier system of claim 6, wherein the fifth switch comprises a large switch and a small switch, wherein the large switch and the small switch are implemented by transistors and a width x length 0 of a channel of the large switch is greater than a width x length of a channel of the small switch, the large switch configured to selectively connect the first end of the inductor to the ground voltage, the small switch configured to selectively connect the first end of the inductor to the ground voltage; and in the third period after the second period, only the small switch of the fifth switch is turned on and the large switch is turned off.
9. The amplifier system of claim 1, wherein the amplifier is powered by the first power supply 5 voltage, the second power supply voltage, and a negative power supply voltage, the power converter configured to generate the first power supply voltage, the second power supply voltage, and the negative power supply voltage based on the input voltage, wherein the first power supply voltage and the second power supply voltage are power supply voltages that are variable based on the input signal or a derivative of the input signal, the negative power supply voltage being desired to have a fixed voltage level.
10. The amplifier system of claim 9, wherein the power converter comprises: an inductor 0 having a first end and a second end;
a first switch for selectively connecting the input voltage to the first end of the inductor;
a second switch for selectively connecting the second end of the inductor to ground voltage;
a third switch for selectively connecting the first end of the inductor to the first supply voltage;
a fourth switch for selectively connecting the second end of the inductor to the second supply voltage; 5 a fifth switch for selectively connecting the first end of the inductor to the negative supply voltage; the method comprises the steps of,
and a sixth switch for selectively connecting the first end of the inductor to the ground voltage.
11. The amplifier system of claim 10, wherein in a first period, the first switch and the second switch are on, the third switch, the fourth switch, the fifth switch, and the sixth switch are off, the input voltage is input to the inductor, and an inductor current increases; in a second period after the first period, the third switch and the fourth switch are on, the first switch, the second switch, the fifth switch, and the sixth switch are off, the second supply voltage is coupled to the first supply voltage through the inductor, and the inductor current decreases; in a third period after the second period, the second switch and the sixth switch are on, and the first switch, the third switch, the fourth switch and the fifth switch are off.
12. The amplifier system of claim 10, wherein in a first period, the first switch and the second switch are on, the third switch, the fourth switch, the fifth switch, and the sixth switch are off, the input voltage is input to the inductor, and an inductor current increases; in a second period after the first period, the third switch and the fifth switch are on, the first switch, the second switch, the fourth switch, and the sixth switch are off, a third supply voltage is coupled to the first supply voltage through the inductor, and the inductor current decreases; in a third period after the second period, the second switch and the sixth switch are on, and the first switch, the third switch, the fourth switch and the fifth switch are off.
13. An amplifier system as claimed in claim 7 or 8, wherein the on-resistance of the large switch is smaller than the on-resistance of the small switch.
14. The amplifier system of claim 1, wherein the amplifier is an audio amplifier and the input signal is an audio signal input to the audio amplifier.
15. A power converter configured to receive an input voltage to generate a first power supply voltage, a second power supply voltage, and a third power supply voltage, the power converter comprising:
an inductor having a first end and a second end;
a first switch for selectively connecting the input voltage to the first end of the inductor;
a second switch for selectively connecting the second end of the inductor to ground voltage;
a third switch for selectively connecting the second end of the inductor to the first supply voltage;
a fourth switch for selectively connecting the first end of the inductor to the second supply voltage;
a fifth switch for selectively connecting the first end of the inductor to the third supply voltage; the method comprises the steps of,
and a sixth switch for selectively connecting the first end of the inductor to the ground voltage.
16. The power converter of claim 15 wherein during a first period the first switch and the second switch are on, the third switch, the fourth switch, the fifth switch, and the sixth switch are off, the input voltage is input to the inductor, and an inductor current increases; in a second period after the first period, the third switch and the fourth switch are on, the first switch, the second switch, the fifth switch, and the sixth switch are off, the second supply voltage is coupled to the first supply voltage through the inductor, and the inductor current decreases; in a third period after the second period, the second switch and the sixth switch are on, and the first switch, the third switch, the fourth switch and the fifth switch are off.
17. The power converter of claim 16, wherein the sixth switch comprises a large switch and a small switch, wherein the large switch and the small switch are implemented by transistors and a width of a channel of the large switch is greater than a width of a channel of the small switch, the large switch configured to selectively connect the first end of the inductor to the ground voltage, the small switch configured to selectively connect the first end of the inductor to the ground voltage; in a third period after the second period, only the small switch of the sixth switch is on and the large switch is off.
18. The power converter of claim 16, wherein the second switch comprises a large switch and a small switch, wherein the large switch and the small switch are implemented by transistors and a width of a channel of the large switch is greater than a width of a channel of the small switch, the large switch configured to selectively connect the second end of the inductor to the ground voltage, the small switch configured to selectively connect the second end of the inductor to the ground voltage; in a third period after the second period, only the small switch of the second switches is on and the large switch is off.
19. The power converter of claim 15, wherein the first power supply voltage, the second power supply voltage, and the third power supply voltage are used to power an amplifier, the third power supply voltage being a negative power supply voltage, wherein the first power supply voltage and the second power supply voltage are power supply voltages that are variable according to an input signal of the amplifier or a derivative of the input signal, the negative power supply voltages being desired to have a fixed voltage level.
20. A power converter according to claim 17 or 18, wherein the on-resistance of the large switch is less than the on-resistance of the small switch.
CN202310037097.2A 2022-01-14 2023-01-10 Amplifier system and power converter Pending CN116455337A (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US63/299,422 2022-01-14
US18/085,579 US20230231523A1 (en) 2022-01-14 2022-12-21 Power converter and associated control method for high-efficiency audio amplifier
US18/085,579 2022-12-21

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