CN116450428A

CN116450428A - Device and method for detecting initial state of radio frequency front-end interface sequence

Info

Publication number: CN116450428A
Application number: CN202310163687.XA
Authority: CN
Inventors: 周分
Original assignee: Shenzhen Enshi Microelectronics Technology Co ltd
Current assignee: Shenzhen Enshi Microelectronics Technology Co ltd
Priority date: 2023-02-24
Filing date: 2023-02-24
Publication date: 2023-07-18

Abstract

The invention discloses a device and a method for detecting the initial state of a radio frequency front end interface sequence, wherein the device comprises the following components: the three input signal lines include a signal line a, a signal line B, and a reset signal line, and the three output signal lines include an identified SCLK clock output signal line, an identified SDATA data output signal line, and an SSC detection indication signal line. The invention can automatically identify the clock line (SCLK) and the data line (SDATA) and complete the detection of the sequence Start State (SSC) under the condition that the functions of the 2 RFFE communication signal lines (A and B) of the main device and the radio frequency front-end device are not clear in advance.

Description

Device and method for detecting initial state of radio frequency front-end interface sequence

Technical Field

The invention relates to the technical field of digital circuit design, in particular to a device and a method for detecting the initial state of a radio frequency front end interface sequence with a clock and data signal automatic identification function based on digital circuit.

Background

In order to provide a general Radio Frequency (RF) front-end equipment control method, a mobile industry processor interface alliance (Mobile Industry Processor Interface Alliance, MIPI alliance) sets a Radio Frequency front-end control interface (Radio Frequency Front-End control interface, RFFE) protocol. The RFFE protocol of the MIPI alliance has the following features: (1) The radio frequency front-end equipment is composed of only 1 clock line (SCLK) and 1 data line (SDATA), so that wiring interconnection requirements of the radio frequency front-end equipment are reduced; (2) The control flow is simple, and the minimum electromagnetic interference (Electro-Magnetic Interference) is generated as much as possible; (3) The antenna is easy to realize, can be designed into a chip independently, and can be integrated with radio frequency front-end equipment into one chip to meet different market demands. RFFEs have been widely used to control various radio frequency front end devices such as power amplifiers, low noise amplifiers, filters, switches, power management modules, antenna tuners, sensors, and the like.

In the RFFE protocol, a plurality of read-write command sequences are defined, and single-byte and multi-byte read-write operation from the main device to various radio frequency front-end devices is realized. These read-write command sequences share a common feature: beginning with a sequence start state (Sequence Start Condition, abbreviated SSC). SSC is a special state: the clock line (SCLK) remains at 0, the data line (SDATA) goes from 0 to 1, and then from 1 to 0. When the radio frequency front end detects the SSC, it indicates that a new read/write command sequence is sent by the master device to the radio frequency front end. Therefore, the SSC is an important state in the RFFE protocol, and the radio frequency front end device needs to continuously detect the clock line (SCLK) and the data line (SDATA) in real time to determine whether the SSC exists.

The prior art generally determines whether an SSC is present by detecting whether the data line (SDATA) changes from 0 to 1 to 0 while the clock line (SCLK) remains 0. At the time of detection, the clock line (SCLK) and the data line (SDATA) need to be known explicitly. In some special applications, the function of the 2 signal lines (called a and B) that the master device connects to the rf front-end device is not known in advance. When a batch of read-write command sequences is transmitted, the master device defines an A signal line as a clock line (SCLK) and a B signal line as a data line (SDATA); when transmitting another batch of read-write command sequences, the master defines the a signal line as the data line (SDATA) and the B signal line as the clock line (SCLK). The prior art is unable to detect SSC in case the clock line (SCLK) and the data line (SDATA) are ambiguous.

Disclosure of Invention

The invention mainly aims to provide a device and a method for detecting the initial state of a sequence of a radio frequency front end interface with automatic identification function of clock and data signals based on a digital circuit, which aim to automatically identify a clock line (SCLK) and a data line (SDATA) and complete the detection of the initial state of the sequence (SSC) under the condition that the functions of two RFFE communication signal lines connected with a main device and the radio frequency front end device are not clear in advance.

In order to achieve the above object, the present invention provides a device for detecting an initial state of a radio frequency front end interface sequence, comprising: a main connection SSC detection circuit, an inverse connection SSC detection circuit, and three input signal lines including a signal line a, a signal line B, and a reset signal line, and three output signal lines including an identified SCLK clock output signal line, an identified SDATA data output signal line, and an SSC detection instruction signal line;

the signal line A and the signal line B have undefined functions before RFFE communication, the circuit structures of the positive SSC detection circuit and the reverse SSC detection circuit are the same, the signal line A is connected to an SCLK clock input port of the positive SSC detection circuit and an SDATA data input port of the reverse SSC detection circuit, and the signal line B is connected to an SDATA data input port of the positive SSC detection circuit and an SCLK clock input port of the reverse SSC detection circuit;

the SCLK clock output signal, the SDATA data output signal, the SSC detection indication signal and the LOCK locking signal generated by the primary connection SSC detection circuit and the reverse connection SSC detection circuit are connected to the SSC selection identification circuit;

the SSC selection and identification circuit is used for generating a GLOBAL LOCK signal of GLOBAL_LOCK according to LOCK LOCK signals transmitted by the positive SSC detection circuit and the reverse SSC detection circuit, feeding back the GLOBAL LOCK signal to the positive SSC detection circuit and the reverse SSC detection circuit, selecting SCLK clock signals and SDATA data signals which are correctly identified, and generating SSC detection indication signals.

The further technical scheme of the invention is that the positive SSC detection circuit and the reverse SSC detection circuit comprise a detection sampling circuit, a detection reset circuit and a detection locking circuit; wherein,,

the detection sampling circuit is used for detecting SSC and generating an SSC detection indication signal, and comprises a register SSC_H, a register SSC_L and a register SSC_L2; wherein,,

the register SSC_H latches the inversion value of the SCLK clock input at the rising edge of the SDATA data input, the register SSC_L latches the output value of the register SSC_H at the falling edge of the SDATA data input, and the register SSC_L2 latches the output value of the SSC_L register at the rising edge of the SCLK clock input.

The detection locking circuit comprises a register SSC_LOCK, and the detection resetting circuit is used for resetting the register SSC_H, the register SSC_L, the register SSC_L2 and the register SSC_LOCK:

the value of the register ssc_h is reset to 0 at the rising edge of the SCLK clock input, and the output value of the register ssc_l2 is reset to 0 after a delay chain.

The detection locking circuit is used for generating a LOCK locking signal:

when the SSC detection indication signal rising edge is generated by the detection sampling circuit, if the GLOBAL LOCK signal of GLOBAL_LOCK is 0, the output value of the register SSC_LOCK is 1, namely, the LOCK LOCK signal is generated and continuously becomes 1, and the GLOBAL LOCK signal of GLOBAL_LOCK is changed into 1 in the SSC selection identification circuit.

When the detection sampling circuit generates the rising edge of the SSC detection indication signal, if the GLOBAL LOCK signal of GLOBAL_LOCK is 1, the circuit is not locked any more.

In order to achieve the above object, the present invention further provides a method for detecting a starting state of a sequence of a radio frequency front end interface, the method being applied to a device for detecting a starting state of a sequence of a radio frequency front end interface as described above, the method comprising the steps of:

when receiving a read-write command sequence sent by a master device, the primary SSC detection circuit and the reverse SSC detection circuit send the generated SCLK clock output signal, SDATA data output signal, SSC detection indication signal and LOCK locking signal to the SSC selection identification circuit;

the SSC selection identification circuit generates a GLOBAL LOCK signal of GLOBAL_LOCK according to LOCK LOCK signals transmitted by the positive SSC detection circuit and the reverse SSC detection circuit, feeds back the GLOBAL LOCK signal to the positive SSC detection circuit and the reverse SSC detection circuit, selects SCLK clock signals and SDATA data signals which are correctly identified, and generates SSC detection indication signals.

The device and the method for detecting the initial state of the radio frequency front end interface sequence have the beneficial effects that:

the invention adopts the mode of a positive SSC detection circuit and a reverse SSC detection circuit, and can automatically identify a clock line (SCLK) and a data line (SDATA) and complete the detection of a sequence Start State (SSC) under the condition that the functions of 2 RFFE communication signal lines (A and B) connected with a main device and a radio frequency front-end device are not clear in advance.

Drawings

FIG. 1 is a schematic diagram showing the overall structure of a device for detecting the initial state of an RF front-end interface sequence according to a preferred embodiment of the present invention;

FIG. 2 is a schematic diagram of circuit structures of a primary SSC detection circuit and a secondary SSC detection circuit;

fig. 3 is a circuit configuration diagram of the SSC selection recognition circuit;

fig. 4 is a waveform diagram of an example of an SSC detection process.

The achievement of the objects, functional features and advantages of the present invention will be further described with reference to the accompanying drawings, in conjunction with the embodiments.

Detailed Description

It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the invention.

Referring to fig. 1 to 4, the present invention provides a device for detecting an initial state of an rf front-end interface sequence.

As shown in fig. 1, a preferred embodiment of the apparatus for detecting an initial state of an rf front-end interface sequence of the present invention includes: the three input signal lines comprise a signal line A, a signal line B and a reset signal line, and the three output signal lines comprise an identified SCLK clock output signal line, an identified SDATA data output signal line and an SSC detection indication signal line.

The function of the signal line A and the function of the signal line B are not clear before RFFE communication, the circuit structures of the forward SSC detection circuit and the reverse SSC detection circuit are the same, and the circuit structures are the same circuit, but the connection modes are not consistent. The signal line A is connected to the SCLK clock input port of the SSC detection circuit and the SDATA data input port of the reverse SSC detection circuit, and the signal line B is connected to the SDATA data input port of the SSC detection circuit and the SCLK clock input port of the reverse SSC detection circuit.

In this embodiment, the apparatus for detecting an initial state of an rf front-end interface sequence mainly includes three parts: a detection circuit for the SSC, a detection circuit for the SSC and a selection and identification circuit for SSC.

The radio frequency front end interface sequence starting state detection device of the embodiment has three input signal lines, wherein the first two signal lines (signal line a and signal line B) have ambiguous functions before RFFE communication, and the signal meaning may be SCLK clock or SDATA data; the 3 rd input line is a reset signal line (RSTN) for resetting the entire device to bring each circuit of the entire device into an initial operating state.

The radio frequency front end interface sequence start state detection device of the embodiment has three output signal lines, including an identified SCLK clock output signal line, an identified SDATA data output signal line, and an SSC detection indication signal line, for outputting automatically identified SCLK clock and SDATA data, and an indication signal (SSC detection indication signal) generated after SSC detection.

The SCLK clock output signal, SDATA data output signal, SSC detection indication signal and LOCK locking signal generated by the detection circuit are connected to the SSC selection recognition circuit.

The SSC selection and identification circuit is used for generating a GLOBAL GLOBAL_LOCK locking signal according to LOCK locking signals transmitted by the positive SSC detection circuit and the negative SSC detection circuit, feeding back the GLOBAL_LOCK GLOBAL locking signal to the positive SSC detection circuit and the negative SSC detection circuit, selecting a correctly identified SCLK clock signal and SDATA data signal and generating an SSC detection indication signal.

Further, as shown in fig. 2, in the present embodiment, the positive SSC detection circuit and the negative SSC detection circuit include a detection sampling circuit, a detection reset circuit, and a detection lock circuit.

The detection sampling circuit is used for detecting SSC and generating SSC detection indication signals, and comprises a register SSC_H, a register SSC_L and a register SSC_L2.

The register ssc_h latches an inverted value of the SCLK clock input at a rising edge of the SDATA data input, the register ssc_l latches an output value of the register ssc_h at a falling edge of the SDATA data input, and the register ssc_l2 latches an output value of the ssc_l register at a rising edge of the SCLK clock input.

Specifically, for register ssc_h, the inverted value of the SCLK clock input is latched on the rising edge of the SDATA data input. The purpose of this is to detect the case where "SDATA rising edge" in SSC and SCLK is 0", and if it is 1, this is described as detecting this case.

For register ssc_l, the output value of ssc_h register is latched on the falling edge of the SDATA data input. The purpose is to detect the case where "SDATA falling edge and SCLK are 0" in SSC when "SDATA rising edge and SCLK are 0" in SSC is detected, and if it is 1, this is described as detecting this case.

For register ssc_l2, the output value of the ssc_l register is latched upon the SCLK clock input rising edge. The purpose of the method is that according to RFFE protocol, the analysis of the read-write command sequence is carried out when SCLK falls, 1 SCLK rising edge is arranged in front of 1 st SCLK falling edge, therefore, the value of SSC_L2 register is latched by using the SCLK rising edge to obtain the output value of SSC_L2 register (namely SSC detection indication signal), and the subsequent RFFE working circuit is provided for use. SSC detection indication signals are register output values, so that sequential optimization of a subsequent RFFE working circuit is facilitated.

The detection LOCK circuit includes a register ssc_lock, and the detection reset circuit is configured to reset the register ssc_h, the register ssc_l, the register ssc_l2, and the register ssc_lock.

The value of the register ssc_h is reset to 0 at the rising edge of the SCLK clock input, and the output value of the register ssc_l2 is reset to 0 after going high through a delay chain.

Specifically, in the present embodiment, three registers (the register ssc_h, the register ssc_l, and the register ssc_l2) of the detection sampling circuit and 1 register (ssc_lock) of the detection LOCK circuit are all reset to the initial state (value 0) by the RSTN reset signal.

On the rising edge of the SCLK clock input, the register SSC_H value is reset to 0. The aim is that: the SCLK is also always 0 "during detection of" SDATA "in SSC as 1. If SCLK transitions 0- >1 during SDATA 1, this indicates that the detected "SDATA rising edge" and SCLK 0 "in the detection sampling circuit does not belong to SSC, and the detection result is cleared (i.e., the register SSC_H is cleared).

After the output value of the register ssc_l2 becomes high, the register ssc_l is reset to 0 through a delay chain. The aim is that:

(I) After the output value of the register ssc_l2 is latched by the register ssc_l2, the register ssc_l2 needs to be cleared, so that the value of the register ssc_l2 latched when the 2 nd SCLK clock inputs the rising edge is 0, so that the state that the output value of the register ssc_l2 (i.e., the SSC detection indication signal) is 1 only maintains 1 SCLK clock beat, and occurrence is avoided: when the SSC detection instruction signal is 1, a plurality of SCLK clock beats are maintained, and the subsequent RFFE operation circuit considers that a plurality of SSCs are detected.

(II) the purpose of using a delay chain is to prevent the following from occurring: when the value of the register ssc_l2 goes high, the register ssc_l2 is also sampling the value of the register ssc_l; if the register SSC_L2 value is immediately passed to the register SSC_L and immediately clears the register SSC_L, the register SSC_L2 value finds a change when the register SSC_L2 is sampling the register SSC_L value, resulting in a metastable state of the register SSC_L2 value, which affects the normal operation of the subsequent RFFE operation circuit.

The detection LOCK circuit is used for generating a LOCK signal.

Specifically, when the detection sampling circuit generates a rising edge of the SSC detection indication signal, if the GLOBAL LOCK signal global_lock is 0 (indicating that the positive SSC detection circuit and the positive SSC detection circuit are not yet locked), the register ssc_lock output value is 1, that is, the LOCK signal is generated and is continued to be 1, and the GLOBAL LOCK signal global_lock is made to be 1 in the SSC selection recognition circuit.

When the detection sampling circuit generates a rising edge of the SSC detection indication signal, if the GLOBAL LOCK signal global_lock is 1 (indicating that one of the positive and negative SSC detection circuits is already locked), this circuit is not locked again.

In this embodiment, as shown in fig. 3, the circuit configuration of the SSC selection recognition circuit mainly functions as:

1. the GLOBAL LOCK signal is generated according to the LOCK signals transmitted by the positive SSC detection circuit and the reverse SSC detection circuit, and the GLOBAL LOCK signal is fed back to the positive SSC detection circuit and the reverse SSC detection circuit.

2. The SCLK clock signal and SDATA data signal which are correctly identified and the SSC detection indication signal generated are selected according to the LOCK locking signal transmitted by the connected SSC detection circuit and the disconnected SSC detection circuit.

The following describes in detail the working principle of the device for detecting the starting state of the sequence of the front end interface of the radio frequency, which is realized based on a digital circuit and has the function of automatically identifying clock and data signals, with reference to fig. 4.

It is assumed that during a certain read/write command sequence transmission, the a signal line function is SCLK clock, and the B signal line function is SDATA data. The working process of the RFFE sequence starting state detection device with the clock and data signal automatic identification function is as follows:

(1) Before power-up, the signals are in an indeterminate state, as shown in FIG. 4.

(2) After power up, the input signals (RSTN reset, A signal, B signal) are in a asserted state. The register values are in an indefinite state before the RSTN reset signal goes into reset (from 1 to 0) and are reset to a definite state after the RSTN reset signal goes into reset, circle 1 of FIG. 4.

(3) After the RSTN reset signal exits reset (from 0 to 1), the device begins to operate waiting for a read-write command sequence. According to the RFFE protocol, the master device issues SSCs. The SSC waveform is as shown in fig. 4, circle 2: the a signal remains at 0, the b signal changes from 0 to 1, and then from 1 to 0.

(4) When the B signal changes from 0 to 1, the positive SSC detection circuit detects a "SDATA rising edge with SCLK being 0", so its register SSC_H value changes from 0 to 1, as shown in circle 3 of FIG. 4. The reverse SSC detection circuit does not detect this and therefore its ssc_h register value is still 0.

(5) When the B signal is changed from 1 to 0, the SSC detection circuit detects the "SDATA falling edge and SCLK is 0" on the basis of the (4) th point, and thus the value of the register ssc_l is changed from 0 to 1, as shown in fig. 4, circle 4. The values of the register ssc_h and ssc_l of the reverse SSC detection circuit remain 0.

(6) After the SSC, the master starts transmitting SCLK clock and SDATA data. At the 1 st signal rising edge:

a) The register ssc_h of the positive SSC detection circuit is cleared 0 as shown in circle 5 of fig. 4;

b) The register ssc_l2 of the SSC detection circuit latches the value of the register ssc_l of the SSC detection circuit from 0 to 1, indicating the generation of a "SSC detection indication signal", as shown in circle 6 of fig. 4;

c) The inverse SSC detection circuit considers the A signal as SDATA data and the B signal as SCLK clock. Thus, it is considered that this moment is the "SDATA rising edge and SCLK is 0" case, its register ssc_h changes from 0 to 1, as in turn 11 of fig. 4.

(7) When the rising edge (i.e., from 0 to 1) of the register ssc_l2 (i.e., SSC detection indication signal) of the positive SSC detection circuit changes the GLOBAL LOCK signal of global_lock to 0, the register ssc_lock value of the positive SSC detection circuit changes from 0 to 1 (e.g., circle 8 of fig. 4), and the GLOBAL LOCK signal of global_lock also changes from 0 to 1 (e.g., circle 10 of fig. 4).

(8) After a delay, the value of the register ssc_l2 (0 to 1) of the SSC detection circuit resets the ssc_l register of the SSC detection circuit to 0, as shown in turn 7 of fig. 4.

(9) At the rising edge of the 2 nd a signal, the value of the register ssc_l2 of the SSC detection circuit changes from 1 to 0 as shown in turn 16 of fig. 4. Therefore, the state of generating the SSC detection indication signal of 1 only maintains 1 SCLK clock beat, and occurrence is avoided: when the SSC detection instruction signal is 1, a plurality of SCLK clock beats are maintained, and the subsequent RFFE operation circuit considers that a plurality of SSCs are detected.

(10) Although there may be a "SDATA rising edge and SCLK being 0" condition during the master device transmitting SCLK clock and SDATA data, such that the register ssc_h value of the SSC detection circuit changes from 0 to 1, the immediately following SCLK clock rising edge changes the register ssc_h value from 1 to 0 again, as shown in turn 9 of fig. 4, so that the register ssc_l and the register ssc_l2 of the SSC detection circuit will not change to 1 again, thereby avoiding SSC false detection.

(11) The inverse is for the SSC detection circuit, the a signal is considered to be SDATA data, and the B signal is considered to be SCLK clock. Therefore, at the 1 st falling edge of the a signal, the register ssc_l of the inverted SSC detection circuit latches the value of the register ssc_h of the inverted SSC detection circuit, changing from 0 to 1 as shown in turn 12 of fig. 4. Immediately after that, on the rising edge of the B signal, the ssc_l2 register value of the inverse SSC detection circuit is changed from 0 to 1, as shown by circle 13 in fig. 4, and after a delay, the ssc_l register of the inverse SSC detection circuit is reset to 0. Although the reverse SSC detection circuit will have these variations, they are all after the GLOBAL LOCK signal 1, and therefore the ssc_lock register of the reverse SSC detection circuit will not change from 0 to 1. That is, the reverse SSC detection circuit is not considered to detect the "SSC detection indication" signal.

(12) The positive connection passes LOCK signals according to the SSC detection circuit and the inverse SSC detection circuit, and the SSC selection recognition circuit selects SCLK clock, SDATA data, and SSC detection indication signals of the positive connection SSC detection circuit as recognized SLCK clock, SDATA data, and SSC detection indication signals, as shown in turn 15 of fig. 4. Thus, the whole device completes the automatic identification of SCLK clock and SDATA data signals and SSC detection.

The RF front-end interface sequence initial state detection device has the beneficial effects that:

The foregoing description is only of the preferred embodiments of the present invention and is not intended to limit the scope of the invention, and all equivalent structures or equivalent processes using the descriptions and drawings of the present invention or directly or indirectly applied to other related technical fields are included in the scope of the invention.

Claims

1. A radio frequency front end interface sequence initiation state detection apparatus, comprising: a main connection SSC detection circuit, an inverse connection SSC detection circuit, and three input signal lines including a signal line a, a signal line B, and a reset signal line, and three output signal lines including an identified SCLK clock output signal line, an identified SDATA data output signal line, and an SSC detection instruction signal line;

2. The apparatus according to claim 1, wherein the positive SSC detection circuit and the negative SSC detection circuit include a detection sampling circuit, a detection reset circuit, and a detection lock circuit; wherein,,

3. The apparatus according to claim 2, wherein the detection LOCK circuit includes a register ssc_lock, and the detection reset circuit is configured to reset the register ssc_h, the register ssc_l, the register ssc_l2, and the register ssc_lock:

4. The apparatus of claim 3, wherein the detection LOCK circuit is configured to generate a LOCK signal:

5. A method for detecting the starting state of a sequence of radio-frequency front-end interfaces, wherein the method is applied to the device for detecting the starting state of a sequence of radio-frequency front-end interfaces according to claim 1, and comprises the following steps: