CN116427033A - Silicon carbide heterogeneous wafer and manufacturing method thereof - Google Patents
Silicon carbide heterogeneous wafer and manufacturing method thereof Download PDFInfo
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Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
-
- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
- C23C16/44—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
-
- C—CHEMISTRY; METALLURGY
- C30—CRYSTAL GROWTH
- C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
- C30B25/00—Single-crystal growth by chemical reaction of reactive gases, e.g. chemical vapour-deposition growth
- C30B25/02—Epitaxial-layer growth
-
- C—CHEMISTRY; METALLURGY
- C30—CRYSTAL GROWTH
- C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
- C30B29/00—Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
- C30B29/10—Inorganic compounds or compositions
- C30B29/36—Carbides
Abstract
The invention discloses a silicon carbide heterogeneous wafer and a manufacturing method thereof. The silicon carbide heterogeneous wafer comprises a silicon carbide monocrystalline layer, a silicon carbide supporting layer and an intermediate layer positioned between the monocrystalline layer and the supporting layer; the material of the intermediate layer is high temperature resistant oxide and contains one of silicon oxycarbide, aluminum oxide and hafnium oxide. Meanwhile, the invention also provides a manufacturing method of the silicon carbide heterogeneous wafer, wherein films are respectively formed on the surfaces to be bonded of the silicon carbide single crystal wafer and the silicon carbide supporting sheet, and then the silicon carbide heterogeneous wafer is formed by in-situ direct bonding after oxygen plasma treatment. The SiC heterogeneous wafer provided by the invention improves the utilization rate of SiC single crystals, and has the advantages of high bonding strength, stable structure at high temperature, compatibility with the existing power device process and the like; the manufacturing process has low requirements on bonding equipment and bonding technology and high bonding yield, thereby reducing the manufacturing cost of the SiC wafer.
Description
Technical Field
The invention relates to the field of semiconductor materials, in particular to a silicon carbide heterogeneous wafer and a manufacturing method thereof.
Background
Silicon carbide (SiC) wafers can be manufactured into SiC power devices through links such as epitaxial growth, device technology and the like, and are basic materials of third-generation semiconductor devices. Considering the problems of warpage during SiC wafer processing, stress introduced during epitaxy, and equipment clamping during device processing, commercial SiC wafers are typically 350um or more thick. Taking a MOSFET of vertical structure as an example, as shown in fig. 1, in order to improve the longitudinal thermal conductivity of the MOSFET 1-7 and to reduce the on-resistance between the source 1-6 and the drain 1-4, the smaller the thickness of the SiC wafer layer 1-1 is, the better. Therefore, as shown in fig. 2, after depositing the epitaxial layer 2-2 on the upper surface of the SiC wafer 2-1 and completing the planar pattern layer 2-3, it is necessary to thin the SiC wafer from the back surface and then to make a metal ohmic contact electrode on the back surface as the drain electrode of the MOSFET. The thinning process requires removal of 200-300um thick backside thinned layers 2-4 from the entire wafer layer 2-1. That is, a SiC single crystal with a thickness of 350um, and only 50-150 um is used in SiC MOSFET devices, and the utilization rate is lower than 43%. Such low utilization is a significant waste for expensive SiC wafers.
Patent CN109478495B and patent CN115662881a disclose a composite silicon carbide substrate formed by bonding a thin SiC single crystal layer and a polycrystalline SiC layer (or a single crystal layer with more defects), with a doped layer between the two layers for reducing interfacial resistance. In order to reduce interface resistance and avoid forming impurities with high resistivity such as silicon oxide at the interface, the process needs to pretreat the bonding surface by high-energy argon ions, clean oxygen atoms remained on the surface, activate the atoms on the surface, and then finish bonding in situ under high vacuum or even ultra-high vacuum environment. This greatly increases the complexity of the bonding apparatus, as well as the difficulty of the bonding process. Patent CN114447095a discloses a composite carbonized substrate composed of a silicon carbide single crystal layer and a ceramic layer. The method comprises the steps of placing SiC powder between a monocrystalline layer and a ceramic layer, then applying high temperature and high pressure, and recrystallizing the SiC powder to bond the monocrystalline layer and the ceramic layer together. However, in order to improve the interfacial bonding force, it is necessary to control the states of the crystal forms and grains at the interface. In the process, the crystallization condition is not completely accurate and controllable, so that the manufacturing difficulty is high and the yield is low. Patent CN114075699a discloses a technique for directly growing a polycrystalline layer on a silicon carbide single crystal layer to obtain a single crystal-polycrystalline composite wafer. In order to improve the interfacial bonding force, the crystal form, the grain size, etc. during the growth process need to be controlled. On one hand, the control of the grain size increases the complexity of the process and reduces the yield; on the other hand, the SiC polycrystalline layer with the thickness of about 200um is directly grown by a high-temperature CVD process, and the manufacturing cost is high.
In summary, the technology of the composite SiC wafer disclosed at present has the problems of high manufacturing process difficulty, high requirement on bonding equipment, severe bonding conditions, high energy consumption and the like.
Disclosure of Invention
In order to solve the defects in the prior art, the application provides a silicon carbide heterogeneous wafer which has the characteristics of stable structure at high temperature, low warpage, compatibility with the prior art and the like. The wafer is manufactured by using a film containing oxide as a bonding transition layer and bonding a SiC single crystal layer and a SiC supporting layer together through a conventional low-temperature bonding process. The manufacturing process has low requirements on bonding equipment and bonding technology and high bonding yield, thereby reducing the manufacturing cost of the SiC wafer.
In this patent, a silicon carbide heterogeneous wafer refers to a wafer formed by stacking SiC materials (such as SiC single crystals, siC polycrystal, siC ceramics with different defect densities) of different crystal qualities in layers with other materials.
The technical scheme adopted by the invention is as follows:
a silicon carbide hetero-wafer, the SiC hetero-wafer comprising:
a SiC single crystal layer;
a SiC support layer; the ratio of the thickness of the SiC support layer to the thickness of the SiC monocrystalline layer is greater than 1:1, less than 14:1, a step of;
an intermediate layer between the SiC single crystal layer and the SiC support layer; the intermediate layer contains an oxide; the melting point or decomposition temperature of the intermediate layer is greater than 1760 ℃.
Further, the intermediate layer contains SiOC, and the molar content of C in the SiOC is 9.8% -20%.
Further, the thickness of the intermediate layer is 10-100 nm.
Further, the intermediate layer contains one of aluminum oxide or hafnium oxide.
Further, the thickness of the intermediate layer is less than 30nm.
Further, the intermediate layer has a resistivity greater than 10 5 Ω·cm；
Further, the SiC single crystal layer is 4H-SiC or 6H-SiC.
Further, the SiC supporting layer is any one of silicon carbide single crystal, silicon carbide polycrystal or silicon carbide ceramic.
A preparation method of a silicon carbide heterogeneous wafer comprises the following steps:
1) Respectively preprocessing a silicon carbide single crystal wafer and a silicon carbide supporting wafer to obtain a SiC single crystal layer and a SiC supporting layer;
2) Depositing an intermediate layer film on the surfaces to be bonded of the SiC monocrystalline layer and the SiC supporting layer respectively; the film contains one of silicon oxycarbide, aluminum oxide and hafnium oxide; for silicon oxycarbide, the molar content of carbon is controlled between 9.8 and 20 percent; for aluminum oxide or hafnium oxide, the film thickness is controlled within 15 nm;
3) And cleaning the SiC monocrystalline layer and the SiC supporting layer deposited with the intermediate layer film, putting the cleaned SiC monocrystalline layer and the cleaned SiC supporting layer into a wafer bonding machine, performing in-situ direct bonding on the two films which are opposite to each other after oxygen plasma treatment, and obtaining the SiC heterogeneous wafer at the bonding temperature of 300-400 ℃.
Further, the method of forming the interlayer film is either PECVD, LPCVD, PVD or ALD.
Further, in the direct bonding, the vacuum in the cavity is 0.1 Pa-10 Pa, the bonding pressure is 10-40 kN, and the pressure holding time is 20-60 min.
The invention has the beneficial effects that:
(1) Since SiC polycrystal and ceramics contain crystal grains of various forms such as 6H, 3C and 4H, even amorphous SiC particles and the like, micro gaps exist between part of the particles. This results in the presence of microcracks on the surface of the SiC polycrystalline or ceramic, with a crack feature width of between 1 and 10 nm. These surface cracks can adsorb residual cleaning liquid or gas, and if bonded directly, tiny "bubbling" defects can correspondingly occur at the cracks. Therefore, a film is deposited on the surface of the polycrystalline or ceramic layer in advance, and the microcracks can be filled and then sealed, so that the bonding bubbling defect is effectively avoided, and the bonding yield is improved.
(2) SiOC is SiO 2 And SiC, wherein SiO 2 The ratio is more than 60 percent, and with Al 2 O 3 And HfO 2 As such, all belong to the oxides. For oxides, the bonding process may be performed in an aerobic environment, such as an atmospheric environment or a low vacuum condition, without the need for high vacuum or even ultra-high vacuum conditions, and without the need to purge the surface to be bonded of oxygen atoms with argon ions. With mature SiO 2 The bonding process is similar, and the bonding of the oxide is only performed at a temperature below 400 ℃, which is compatible with the conventional bonding machines of most silicon processes, and a special high-temperature bonding machine is not needed. After bonding, O ions can diffuse and migrate at the interface to form a new covalent bond, so that the interface bonding strength is remarkably improved. Thus, siOC and Al are used in the present invention 2 O 3 And HfO 2 The requirements on bonding equipment and bonding conditions are greatly reduced for the bonding process of the transition layer.
(3) The SiC wafers are subjected to a number of high temperature processes including CVD homoepitaxy, activation by annealing after ion implantation, and thermal oxidation of the gate layer, among others, where the highest temperature may reach 1760 ℃. SiO (SiO) 2 The melting point of (2) is between 1640 and 1723 ℃, depending on the preparation method and the crystal morphology. If SiO is used 2 As an intermediate layer, there is a possibility that the intermediate layer melts in a subsequent high temperature process to cause separation of the single crystal layer from the ceramic layer. Therefore, in order to raise the melting point of the intermediate layer, the invention adopts a material consisting of SiO 2 SiOC composited with SiC as an intermediate layer can significantly raise the melting point, and the higher the SiC content (corresponding to the molar concentration of C), the higher the SiOC melting point, as shown in FIG. 5. When the molar concentration of C in SiOC is greater than 9.8%, the melting point of SiOC may exceed 1760 ℃. Therefore, siOC is used as an intermediate layer, so that the heterogeneous wafer can withstand the subsequent high-temperature process, a stable wafer structure is maintained, and the phenomenon of interlayer separation is avoided.
(4) When the heterogeneous wafer is used for manufacturing a vertical SiC MOSFET, and a back thinning process is implemented, as shown in fig. 6, a diamond grinding wheel thinning machine can be used for completely removing the supporting layer 6-1 and the intermediate layer 6-2, and only the monocrystalline layer 6-3, the epitaxial layer 6-4 and the pattern layer 6-5 are left; the structural characteristics that the intermediate layer 6-2 is not conductive (high in resistivity) and the supporting layer 6-1 is conductive can be fully utilized, and the intermediate layer 6-2 is selectively and completely etched by adopting an electrochemical method, so that the supporting layer 6-1 is rapidly stripped. For example, for a support layer thickness to monocrystalline layer thickness ratio of 6:1, a heterogeneous wafer with a total thickness of 350um, after complete removal of the support layer and the intermediate layer, leaves behind a monocrystalline layer 50um thick, i.e. the SiC monocrystalline fraction is 100% used in the final device. Therefore, in the vertical SiC MOSFET manufactured by using the hetero wafer, there is no support layer crystal with poor crystal quality, there is no defect density higher, and only a SiC single crystal with high crystal quality remains in the conductively doped intermediate layer. The material structure of the MOSFET is kept identical with that of the MOSFET manufactured by adopting the high-quality SiC wafer at present while the utilization rate of the SiC monocrystal is greatly improved.
(5) The SiC heterogeneous wafer provided by the invention improves the utilization rate of SiC single crystals, and has the advantages of high bonding strength, stable structure at high temperature, compatibility with the existing power device process and the like; the manufacturing process has low requirements on bonding equipment and bonding technology and high bonding yield, thereby reducing the manufacturing cost of the SiC wafer.
Drawings
Fig. 1 is a schematic structural diagram of a vertical SiC MOSFET.
Fig. 2 is a schematic explanatory diagram of a thinning process for manufacturing a vertical SiC MOSFET by the current conventional process.
FIG. 3 is a schematic view of a silicon carbide heterogeneous wafer according to the present invention.
FIG. 4 is a schematic diagram of a process flow for fabricating a silicon carbide hetero-wafer according to the present invention.
FIG. 5 is a graph of carbon content versus melting point for SiOC.
Fig. 6 is a schematic illustration of a backside thinning process when a MOSFET is fabricated using a heterogeneous wafer.
FIG. 7 is a comparison of data for thermal expansion of SiC ceramic and SiC single crystal at different temperatures in an example.
Fig. 8 is a physical photograph of a heterogeneous wafer of an embodiment.
Fig. 9 is a cross-sectional TEM image of an intermediate layer of a silicon carbide hetero wafer, and a distribution diagram of the elemental composition obtained with an electron energy loss spectrum.
Fig. 10 is a schematic diagram of a back-end-of-line device process using SiC heterogeneous wafers.
Detailed Description
The present invention will be described in further detail with reference to the drawings and examples, in order to make the objects, technical solutions and advantages of the present invention more apparent. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the invention.
Example 1
A silicon carbide hetero-wafer as shown in fig. 3, comprising:
1.SiC single crystal layer 3-1;
in example 1, the SiC single crystal layer 3-1 was 4H-SiC or 6H-SiC. The average roughness of the surface of the SiC single crystal layer 3-1 is less than 0.1nm.
The SiC single crystal layer 3-1 can be prepared by ultrathin linear cutting, ion implantation, laser undercut or other methods, and is preferably a SiC single crystal thin layer prepared by laser undercut.
The thickness of the SiC single crystal layer 3-1 is 35 to 175. Mu.m, preferably 50 to 100. Mu.m.
2. A SiC supporting layer 3-2;
the ratio of the thickness of the SiC support layer 3-2 to the thickness of the SiC single crystal layer 3-1 is greater than 1:1, less than 14:1 as the thickness ratio is 5:2;
the SiC supporting layer 3-2 is SiC single crystal, siC polycrystal or SiC ceramic, wherein the crystal defect density of the SiC single crystal is higher than that of the SiC single crystal layer 3-1. The average roughness of the surface of the SiC supporting layer 3-2 is less than 5nm;
the thickness of the SiC support layer 3-2 is 175 to 315um, preferably 200, 250 or 300um.
The density of the SiC supporting layer 3-2 is 3.10-3.22 g/cm 3 Such as 3.2g/cm 3 The closer the density of the support layer is to 3.22g/cm 3 The closer the thermal expansion coefficient is to that of the SiC single crystal, the smaller the warpage of the obtained heterogeneous wafer at high temperature, and the more stable the structure.
The SiC supporting layer sheet can be made ofThe SiC ceramic is obtained by isostatic pressing sintering, high-pressure sintering, vapor transport growth and other methods, and is preferably obtained by a high-pressure sintering method. In example 1, the SiC supporting layer 3-2 was a SiC ceramic obtained by high pressure sintering and had a density of 3.19g/cm 3 。
3. Intermediate layer 3-3
Intermediate layer 3-3 is located between SiC single crystal layer 3-1 and SiC support layer 3-2, and in example 1, intermediate layer 3-3 contains SiOC having a carbon content of 19.8% by mole.
The SiOC interlayer 3-3 has a thickness of between 10 and 100nm, such as 18nm.
The resistivity of the SiOC interlayer 3-3 is greater than 10 5 Ω·cm。
Wherein, in the SiC supporting layer 3-2 and the intermediate layer 3-3, the total mass content of metal elements which are soluble in concentrated sulfuric acid is lower than 1ppm. The method can avoid the reaction of the impurities of the metal elements with the developing solution (concentrated sulfuric acid) of the photoresist when the wafer is used for carrying out the graphic process, thereby causing the metal ion pollution of the wafer.
The SiC heterogeneous wafer thickness is 300-450 um, preferably 330, 350um.
Wherein the diameter of the SiC heterogeneous wafer is 50 mm-200 mm, preferably 100mm, 150mm and 200mm.
The flatness of the whole SiC heterogeneous wafer is smaller than 10um, and the total thickness change is smaller than 2um.
The thermal expansion of the SiC ceramic and 4H-SiC single crystal wafers with the dimensions of 5X 40mm were measured at different temperatures, and the obtained data are shown in FIG. 7, wherein 7-1 corresponds to the 4H-SiC single crystal wafer and 7-2 corresponds to the SiC ceramic wafer. It can be seen from the figure that at the highest temperature, the expansion difference of the two materials is less than 1%.
A method for preparing a silicon carbide heterogeneous wafer as shown in fig. 4 is described as follows:
(1) The surface to be bonded of the silicon carbide single crystal wafer 1 and the silicon carbide supporting wafer 2 is respectively pretreated, and the surface to be bonded is polished to have average roughness of 0.5nm and flatness of 8um;
(2) SiOC film is deposited on the surface to be bonded of the silicon carbide single crystal wafer 1 and the silicon carbide supporting wafer 2 by PECVD, and SiOC film is depositedAr gas flow rate was 500sccm, CH 4 The flow rate was 15sccm and the TEOS temperature was set at 55deg.C. The growth time was 3min, and the thickness of the obtained SiOC film was about 6nm, wherein the molar content of the C element was 19.8%. In this embodiment, LPCVD, PVD, ALD, or the like may be used in addition to PECVD for SiOC film deposition.
(3) Placing silicon carbide single crystal wafer 1 and silicon carbide supporting sheet 2 in acetone, alcohol and deionized water, respectively ultrasonically cleaning for 2min, and then placing in H 2 O、H 2 O 2 And NH 4 Soaking in OH mixed solution for 30min; taking out, cleaning with ionized water in an ultrasonic manner, and drying with high-purity nitrogen. The single chip and the ceramic chip are put into a wafer bonding machine with model AML-AWB-04, and two SiOC films are opposite to each other for in-situ oxygen plasma treatment. The plasma radio frequency power is 200W, and the treatment time is 3min. After surface treatment, direct bonding is carried out, the bonding temperature is 400 ℃, the vacuum in the cavity is 0.5Pa, the bonding pressure is 40kN, and the pressure holding time is 25min. A silicon carbide hetero-wafer was obtained as shown in fig. 8.
After bonding, the wafer is cut into 5X 5mm 2 4 pieces of samples positioned in the middle and at the periphery of the wafer are taken, and the bonding strength is tested by a universal tensile machine, so that the average bonding strength of the samples is 9.6MPa.
A slice was taken, and the intermediate layer cross section was cut out using FIB, and subjected to Transmission Electron Microscopy (TEM) and Electron Energy Loss Spectroscopy (EELS) analysis, the results of which are shown as 9a-9d in FIG. 9. As can be seen from fig. 9a, the intermediate layer SiOC is in an amorphous state, with a thickness of about 12nm. By quantitative analysis of EELS, as shown in fig. 9b-9d, in the SiOC interlayer, the molar content of Si was 46%, the molar content of C was 19.8%, and the molar content of O was 34.2%.
In this embodiment, the thickness of the SiC single crystal layer 3-1 is 35 to 175um; the ratio of the thickness of the SiC support layer 3-2 to the thickness of the SiC single crystal layer 3-1 is greater than 1:1, less than 14:1, a step of; the molar content of C in the SiOC in the middle layer is 9.8-20%, and the same technical effects as those of the embodiment can be obtained;
example 2
A silicon carbide hetero-wafer as shown in fig. 3, comprising:
silicon carbide heterogeneous wafer
1.SiC single crystal layer 3-1;
in example 2, the SiC single crystal layer 3-1 was 6H-SiC. The average roughness of the surface of the SiC single crystal layer 3-1 is less than 0.1nm.
The SiC single crystal layer 3-1 is a thin SiC single crystal layer obtained by cutting with a mortar wire and then thinning.
The thickness of the SiC single crystal layer 3-1 was 150. Mu.m.
2. A SiC supporting layer 3-2;
the ratio of the thickness of the SiC support layer 3-2 to the thickness of the SiC single crystal layer 3-1 is 3:2;
the SiC supporting layer 3-2 is a SiC single crystal, wherein the crystal defect density of the SiC single crystal in the supporting layer 3-2 is higher than that of the SiC single crystal layer 3-1. The average roughness of the surface of the SiC supporting layer 3-2 is less than 5nm;
the thickness of the SiC support layer 3-2 is 200um.
The density in the SiC support layer 3-2 was 3.19g/cm 3 。
The SiC single crystal wafer of the support layer 3-2 is obtained by a vapor transport growth method.
3. Intermediate layer 3-3
Intermediate layer 3-3 is located between SiC single crystal layer 3-1 and SiC support layer 3-2, in example 2, the intermediate layer is Al 2 O 3 。
The SiOC interlayer 3-3 has a thickness of 14nm.
The resistivity of the SiOC interlayer 3-3 is greater than 10 5 Ω·cm。
Wherein, in the SiC supporting layer 3-2 and the intermediate layer 3-3, the total mass content of metal elements which are soluble in concentrated sulfuric acid is lower than 1ppm. The method can avoid the reaction of the impurities of the metal elements with the developing solution (concentrated sulfuric acid) of the photoresist when the wafer is used for carrying out the graphic process, thereby causing the metal ion pollution of the wafer.
The SiC hetero-wafer thickness is 350um.
The diameter of the SiC heterogeneous wafer is 100mm.
The flatness of the whole SiC heterogeneous wafer is smaller than 10um, and the total thickness change is smaller than 2um.
A preparation method of silicon carbide heterogeneous wafers is described as follows:
(1) The surface to be bonded of the silicon carbide single crystal wafer 1 and the silicon carbide supporting wafer 2 is respectively pretreated, and the surface to be bonded is polished to have average roughness of 1nm and flatness of 10um;
(2) Al is deposited on the surface to be bonded of the silicon carbide single crystal wafer 1 and the silicon carbide support wafer 2 by ALD 2 O 3 Film, ar gas flow is 100sccm, O 3 The flow rate was 20sccm and the temperature of TMA was set at 70 ℃. Growing for 50 cycles, the Al is obtained 2 O 3 The thickness of the film is about 7nm; similarly, hafnium oxide films may also be deposited by ALD.
(3) Placing silicon carbide single crystal wafer 1 and silicon carbide supporting sheet 2 in acetone, alcohol and deionized water, respectively ultrasonically cleaning for 2min, and then placing in H 2 O、H 2 O 2 And NH 4 Soaking in OH mixed solution for 30min; taking out, cleaning with ionized water in an ultrasonic manner, and drying with high-purity nitrogen. Placing the single chip and the ceramic wafer into a wafer bonding machine with the model of EVG510, and two Al 2 O 3 The films were opposed and subjected to an in situ oxygen plasma treatment. The plasma radio frequency power is 200W, and the treatment time is 2min. After surface treatment, direct bonding is carried out, the bonding temperature is 400 ℃, the vacuum in the cavity is 0.5Pa, the bonding pressure is 40kN, and the pressure holding time is 30min. After the silicon carbide heterogeneous wafer is bonded, the wafer is cut into 5X 5mm 2 4 pieces of samples positioned in the middle and at the periphery of the wafer are taken, and the bonding strength is tested by a universal tensile machine, so that the average bonding strength of the samples is 6.3MPa.
The bonding process of example 1 or 2, the formation method of the interlayer film was one of PECVD, LPCVD, PVD or ALD; for depositing SiOC thin films, PECVD is preferred; for depositing Al 2 O 3 And HfO 2 ALD is preferred.
The films deposited on both surfaces in examples 1 and 2 may be the same or different in thickness. But the thickness of the deposited film on the SiC polycrystalline or ceramic surface should be such that the microcracks of the coated surface are completely filled.
In the bonding process of the embodiment 1 or 2, when the bonding is directly performed, the vacuum in the cavity is 0.1 Pa-10 Pa, the bonding pressure is 10-40 kN, and the pressure holding time is 20-60 min.
The bonding process of examples 1 or 2 can be performed by those skilled in the art using conventional bonding machines used in silicon processes such as AML-AWB-04, SUSS SB6e, EVG510, and the like.
As shown in fig. 10, after preparing the epitaxial layer 10-5 and the front pattern layer 10-6 according to the SiC hetero wafer prepared in the above embodiment, a 10-1 structure is obtained; then thinning the back surface, and completely removing the supporting layer and the middle layer 10-4 to obtain a 10-2 structure; then, the ohmic contact metal layer 10-8 is prepared on the back surface of the single crystal layer 10-7 to obtain the structure of 10-3.
The above embodiments are merely for illustrating the design concept and features of the present invention, and are intended to enable those skilled in the art to understand the content of the present invention and implement the same, the scope of the present invention is not limited to the above embodiments. Therefore, all equivalent changes or modifications according to the principles and design ideas of the present invention are within the scope of the present invention.
Claims (11)
1. A silicon carbide heterogeneous wafer, comprising:
a SiC single crystal layer (3-1);
a SiC support layer (3-2); the ratio of the thickness of the SiC support layer (3-2) to the thickness of the SiC single crystal layer (3-1) is greater than 1:1, less than 14:1, a step of;
an intermediate layer (3-3) located between the SiC single crystal layer (3-1) and the SiC support layer (3-2); the intermediate layer (3-3) contains an oxide; the melting point or decomposition temperature of the intermediate layer (3-3) is more than 1760 ℃.
2. A silicon carbide heterostructure wafer according to claim 1, characterized in that the intermediate layer (3-3) contains SiOC, the molar content of C in the SiOC being 9.8% to 20%.
3. A silicon carbide heterostructure wafer according to claim 2, characterized in that the thickness of the intermediate layer (3-3) is 10-100 nm.
4. A silicon carbide heterostructure wafer according to claim 1, characterized in that the intermediate layer (3-3) contains one of aluminium oxide or hafnium oxide.
5. A silicon carbide heterostructure according to claim 4, wherein the thickness of the intermediate layer is less than 30nm.
6. A silicon carbide heterostructure according to claim 1, characterized in that the resistivity of the intermediate layer (3-3) is greater than 10 5 Ω·cm。
7. A silicon carbide heterostructure wafer according to any one of claims 1 to 6, characterized in that the single crystal SiC layer (3-1) is 4H-SiC or 6H-SiC.
8. A silicon carbide hetero-wafer as claimed in claim 6 wherein the SiC support layer (3-2) is any one of single crystal silicon carbide, polycrystalline silicon carbide or ceramic silicon carbide.
9. The preparation method of the silicon carbide heterogeneous wafer is characterized by comprising the following steps of:
1) Respectively preprocessing a silicon carbide single crystal wafer (01 a) and a silicon carbide supporting wafer (01 b) to obtain a SiC single crystal layer (3-1) and a SiC supporting layer (3-2);
2) Depositing an interlayer film (02 a) on the surfaces to be bonded of the SiC single crystal layer (3-1) and the SiC supporting layer (3-2) respectively; the film contains one of silicon oxycarbide, aluminum oxide and hafnium oxide; for silicon oxycarbide, the molar content of carbon is controlled between 9.8 and 20 percent; for aluminum oxide or hafnium oxide, the film thickness is controlled within 15 nm;
3) Cleaning the SiC monocrystalline layer (3-1) and the SiC supporting layer (3-2) deposited with the interlayer film, putting the cleaned SiC monocrystalline layer and the cleaned SiC supporting layer into a wafer bonding machine, and directly bonding the two films in situ after oxygen plasma treatment at the bonding temperature of 300-400 ℃ to obtain the SiC heterogeneous wafer.
10. The method for producing a silicon carbide hetero-wafer according to claim 8, wherein the method for forming the intermediate layer thin film is either PECVD, LPCVD, PVD or ALD.
11. The method for preparing a silicon carbide heterogeneous wafer according to claim 8, wherein the vacuum in the cavity is 0.1Pa to 10Pa, the bonding pressure is 10 kN to 40kN, and the pressure holding time is 20 min to 60min during direct bonding.
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