CN116417404A - Double gate structure, field oxide structure and manufacturing method of semiconductor device - Google Patents
Double gate structure, field oxide structure and manufacturing method of semiconductor device Download PDFInfo
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 39
- 239000004065 semiconductor Substances 0.000 title claims abstract description 12
- 238000005530 etching Methods 0.000 claims abstract description 49
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 47
- 239000000463 material Substances 0.000 claims abstract description 46
- 238000001259 photo etching Methods 0.000 claims abstract description 40
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 27
- 229920005591 polysilicon Polymers 0.000 claims abstract description 27
- 238000001312 dry etching Methods 0.000 claims abstract description 23
- 230000004888 barrier function Effects 0.000 claims abstract description 9
- 239000011248 coating agent Substances 0.000 claims abstract description 5
- 238000000576 coating method Methods 0.000 claims abstract description 5
- 238000000034 method Methods 0.000 claims description 55
- 239000000758 substrate Substances 0.000 claims description 43
- 230000008569 process Effects 0.000 claims description 30
- 238000002513 implantation Methods 0.000 claims description 13
- 230000009977 dual effect Effects 0.000 claims description 10
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 8
- 229910052710 silicon Inorganic materials 0.000 claims description 8
- 239000010703 silicon Substances 0.000 claims description 8
- 239000007772 electrode material Substances 0.000 claims description 5
- 230000000903 blocking effect Effects 0.000 abstract description 2
- 239000007789 gas Substances 0.000 description 10
- 239000012212 insulator Substances 0.000 description 10
- 238000005229 chemical vapour deposition Methods 0.000 description 8
- 238000000206 photolithography Methods 0.000 description 8
- 230000003667 anti-reflective effect Effects 0.000 description 7
- 238000002347 injection Methods 0.000 description 7
- 239000007924 injection Substances 0.000 description 7
- 239000003989 dielectric material Substances 0.000 description 6
- 230000007246 mechanism Effects 0.000 description 6
- 229910052751 metal Inorganic materials 0.000 description 6
- 239000002184 metal Substances 0.000 description 6
- 238000012544 monitoring process Methods 0.000 description 6
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 6
- 230000008859 change Effects 0.000 description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 150000001875 compounds Chemical class 0.000 description 4
- 239000007943 implant Substances 0.000 description 4
- 230000010354 integration Effects 0.000 description 4
- 238000002955 isolation Methods 0.000 description 4
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 4
- 150000004767 nitrides Chemical class 0.000 description 4
- 230000003647 oxidation Effects 0.000 description 4
- 238000007254 oxidation reaction Methods 0.000 description 4
- 238000005240 physical vapour deposition Methods 0.000 description 4
- 229910052814 silicon oxide Inorganic materials 0.000 description 4
- 239000000243 solution Substances 0.000 description 4
- 239000012535 impurity Substances 0.000 description 3
- BPQQTUXANYXVAA-UHFFFAOYSA-N Orthosilicate Chemical compound [O-][Si]([O-])([O-])[O-] BPQQTUXANYXVAA-UHFFFAOYSA-N 0.000 description 2
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 description 2
- 229910052454 barium strontium titanate Inorganic materials 0.000 description 2
- 238000013461 design Methods 0.000 description 2
- 238000011161 development Methods 0.000 description 2
- 229910052735 hafnium Inorganic materials 0.000 description 2
- VBJZVLUMGGDVMO-UHFFFAOYSA-N hafnium atom Chemical compound [Hf] VBJZVLUMGGDVMO-UHFFFAOYSA-N 0.000 description 2
- 229910000449 hafnium oxide Inorganic materials 0.000 description 2
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 description 2
- HFGPZNIAWCZYJU-UHFFFAOYSA-N lead zirconate titanate Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ti+4].[Zr+4].[Pb+2] HFGPZNIAWCZYJU-UHFFFAOYSA-N 0.000 description 2
- 229910052451 lead zirconate titanate Inorganic materials 0.000 description 2
- 238000001459 lithography Methods 0.000 description 2
- 238000002156 mixing Methods 0.000 description 2
- 238000001289 rapid thermal chemical vapour deposition Methods 0.000 description 2
- 229910021332 silicide Inorganic materials 0.000 description 2
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- OGIDPMRJRNCKJF-UHFFFAOYSA-N titanium oxide Inorganic materials [Ti]=O OGIDPMRJRNCKJF-UHFFFAOYSA-N 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000004886 process control Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823462—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
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Abstract
The invention relates to a double-gate structure, a field oxide structure and a manufacturing method of a semiconductor device, wherein the manufacturing method of the double-gate structure comprises the following steps: acquiring a wafer formed with a first gate dielectric layer and a second gate dielectric layer; forming a gate material layer on the first gate dielectric layer and the second gate dielectric layer; forming a photoetching anti-reflection layer on the grid material layer; coating photoresist on the photoetching anti-reflection layer, exposing the photoresist by using a polysilicon gate photoetching plate, developing the photoresist, etching the photoetching anti-reflection layer and the grid material layer, forming a first grid on the first grid dielectric layer, forming a second grid on the second grid dielectric layer, and extending both sides of the first grid dielectric layer from the bottom of the first grid; and removing photoresist, and then dry etching the first gate dielectric layer extending from the bottom of the first gate electrode, wherein the photoetching anti-reflection layer is used as a blocking layer of the dry etching. The invention uses the photoetching anti-reflection layer as an etching barrier layer, and removes the redundant first gate dielectric layer extending out of the first gate electrode by dry etching, thereby ensuring that the device does not have broken grooves.
Description
Technical Field
The present invention relates to the field of semiconductor manufacturing, and more particularly, to a method for manufacturing a dual gate structure, a method for manufacturing a field oxide structure, and a method for manufacturing a semiconductor device.
Background
With the continuous development of integrated circuit technology, the integration level of a process platform is higher and higher, and the integration of a high-voltage process on a low-voltage process platform is more and more common. In the Dual Gate process, an exemplary fabrication method is to grow thick Gate oxide first, then lithographically etch out thin Gate regions, then grow thin Gate oxide, and deposit polysilicon. The thick gate oxide is required to extend beyond the polysilicon by a certain size to ensure that the polysilicon does not exceed the edge of the thick gate oxide, under the influence of overlay errors (overlay) during the thick gate lithography and polysilicon lithography operations. And when the source and drain implantation is performed later, the thick gate oxide extending out of the polysilicon can block the source and drain implantation. If the thick gate oxide is thinner, the effect of the source-drain implantation is smaller and can be almost ignored. However, if the thick gate oxide is too thick, the source and drain implants are mostly blocked, which can cause device trench breaks.
Disclosure of Invention
Based on this, it is necessary to provide a method for manufacturing a dual gate structure in which the source and drain implants of the device are not blocked by the excess implant blocking layer.
A method of fabricating a dual gate structure, comprising: obtaining a wafer, wherein a first gate dielectric layer and a second gate dielectric layer are formed on a substrate by the wafer, and the thickness of the second gate dielectric layer is smaller than that of the first gate dielectric layer; forming a gate material layer on the first gate dielectric layer and the second gate dielectric layer; forming a photoetching anti-reflection layer on the grid material layer; coating photoresist on the photoetching anti-reflection layer, exposing by using a polysilicon gate photoetching plate, developing the photoresist, etching the photoetching anti-reflection layer and the grid electrode material layer, and forming a first grid electrode on the first grid dielectric layer and a second grid electrode on the second grid dielectric layer; the width of the first gate dielectric layer is larger than that of the first gate, and both sides of the first gate dielectric layer extend out from the bottom of the first gate; removing the photoresist, and then dry etching a first gate dielectric layer extending from the bottom of the first gate, wherein the photoetching anti-reflection layer is used as a barrier layer of the dry etching; controlling etching conditions to ensure that the photoetching anti-reflection layer is not etched before the extended first gate dielectric layer is etched; and performing source-drain implantation on two sides of the first grid electrode.
According to the manufacturing method of the double-gate structure, the photoetching anti-reflection layer is used as the etching barrier layer, and the redundant first gate dielectric layer extending out of the first gate electrode is removed through dry etching, so that the source drain injection is prevented from being blocked by the redundant first gate dielectric layer, and the phenomenon of broken grooves of a device is prevented.
In one embodiment, the material of the photoresist anti-reflection layer includes silicon oxynitride.
In one embodiment, the first gate dielectric layer and the second gate dielectric layer are both gate oxide layers.
In one embodiment, the gate material layer includes polysilicon.
In one embodiment, the step of obtaining the wafer includes: forming a first dielectric layer in a first area on the substrate; forming a second dielectric layer on the substrate and the first dielectric layer; the first dielectric layer of the first region and the second dielectric layer of the first region are used together as the first gate dielectric layer, and the second dielectric layer outside the first region is used as the second gate dielectric layer.
In one embodiment, the dry etch employs a mechanism for etch endpoint monitoring.
In one embodiment, the dry etch monitors the etch endpoint by monitoring the change in the etch rate profile.
In one embodiment, the first gate is a gate of a high voltage device and the second gate is a gate of a low voltage device.
It is also desirable to provide a method of fabricating a field oxide structure.
A method of fabricating a field oxide structure, comprising: obtaining a wafer, wherein a field oxide layer and a gate dielectric layer are formed on a substrate of the wafer, and the thickness of the gate dielectric layer is smaller than that of the field oxide layer; forming a grid electrode material layer on the field oxide layer and the grid dielectric layer; forming a photoetching anti-reflection layer on the grid material layer; coating photoresist on the photoetching anti-reflection layer, exposing the photoresist by using a polysilicon gate photoetching plate, developing the photoresist, and then etching the photoetching anti-reflection layer and a gate material layer to obtain a gate layer, wherein one side of the gate layer extends out of the edge of the field oxide layer onto the gate dielectric layer, and the other side of the gate layer is shorter than the field oxide layer, so that the field oxide layer extends out of the bottom of the other side of the gate layer; removing the photoresist, and then dry etching a field oxide layer extending from the bottom of the other side of the gate layer, wherein the photoetching anti-reflection layer is used as a barrier layer of the dry etching; controlling etching conditions to ensure that the photoetching anti-reflection layer is not etched before the extended field oxide layer is etched; and performing source-drain implantation into the substrate.
According to the manufacturing method of the field oxide structure, the photoetching anti-reflection layer is used as the etching barrier layer, and the redundant field oxide layer extending out of the grid layer is removed through dry etching, so that the source drain injection is prevented from being blocked by the redundant field oxide layer, and the phenomenon that the device is broken is avoided.
In one embodiment, the step of obtaining the wafer includes: forming a first oxide layer on the substrate; removing the first oxide layer of the second region; and forming a gate dielectric layer in the second region, wherein the gate dielectric layer and the first oxide layer which are simultaneously formed on the first oxide layer are used as the field oxide layer together.
In one embodiment, the material of the photoresist anti-reflection layer includes silicon oxynitride.
In one embodiment, the gate material layer includes polysilicon.
In one embodiment, the dry etch employs a mechanism for etch endpoint monitoring.
In one embodiment, the dry etch monitors the etch endpoint by monitoring the change in the etch rate profile.
It is also necessary to provide a method for manufacturing a semiconductor device, which is applied to the BCD process, including the method for manufacturing a dual gate structure according to any of the foregoing embodiments, and/or the method for manufacturing a field oxide structure according to any of the foregoing embodiments.
Drawings
For a better description and illustration of embodiments and/or examples of those inventions disclosed herein, reference may be made to one or more of the accompanying drawings. Additional details or examples used to describe the drawings should not be construed as limiting the scope of the disclosed invention, the presently described embodiments and/or examples, and any of the presently understood modes of carrying out the invention.
FIG. 1 is a flow chart of a method of fabricating a dual gate structure in one embodiment;
FIGS. 2 a-2 e are schematic cross-sectional views of a wafer at various steps in one embodiment of a dual gate structure fabricated by the method of FIG. 1;
FIG. 3 is a flow chart of a method of forming the structure of FIG. 2a in one embodiment;
FIG. 4 is a flow chart of a method of fabricating a field oxide structure in one embodiment;
FIGS. 5 a-5 e are schematic cross-sectional views of a wafer at various steps in one embodiment of the fabrication of a field oxide structure using the method of FIG. 4;
FIG. 6 is a flow chart of a method of forming the structure of FIG. 5a in one embodiment.
Detailed Description
In order that the invention may be readily understood, a more complete description of the invention will be rendered by reference to the appended drawings. Preferred embodiments of the present invention are shown in the drawings. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used herein in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "and/or" as used herein includes any and all combinations of one or more of the associated listed items.
It will be understood that when an element or layer is referred to as being "on," "adjacent," "connected to," or "coupled to" another element or layer, it can be directly on, adjacent, connected, or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.
Spatially relative terms, such as "under," "below," "beneath," "under," "above," "over," and the like, may be used herein for ease of description to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements or features described as "under" or "beneath" other elements would then be oriented "on" the other elements or features. Thus, the exemplary terms "below" and "under" may include both an upper and a lower orientation. The device may be otherwise oriented (rotated 90 degrees or other orientations) and the spatially relative descriptors used herein interpreted accordingly.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.
Embodiments of the invention are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the invention. In this way, variations from the illustrated shape due to, for example, manufacturing techniques and/or tolerances, are to be expected. Thus, embodiments of the present invention should not be limited to the particular shapes of the regions illustrated herein, but rather include deviations in shapes that result, for example, from manufacturing. For example, an implanted region shown as a rectangle typically has rounded or curved features and/or implant concentration gradients at its edges rather than a binary change from implanted to non-implanted regions. Also, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface over which the implantation is performed. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the present invention.
The term "semiconductor" used herein is a technical term commonly used by those skilled in the art, for example, for P-type and N-type impurities, p+ type represents P type with heavy doping concentration, P type with medium doping concentration, P-type represents P type with light doping concentration, n+ type represents N type with heavy doping concentration, N type represents N type with medium doping concentration, and N type represents N type with light doping concentration.
In BCD (Bipolar CMOS DMOS) processes with a Critical Dimension (CD) of 0.18 microns, thicker field oxide or thick gate oxide is added to the process in order to achieve higher device breakdown voltages and lower on-resistance, or to provide devices with different gate voltages. After the polysilicon is etched, the introduction of the thick field oxide and the thick gate oxide can cause that part of the field oxide and the thick gate oxide extend out of the polysilicon to influence the source drain injection, and the problem of broken grooves of devices can be caused. In view of the above problems, two exemplary solutions are described herein, namely, adding a photolithography mask to etch the thick gate oxide or the thick field oxide extending from the polysilicon, that is, adding an additional photolithography after the polysilicon etching is completed, exposing the gate oxide or the field oxide region extending from the polysilicon, and etching to remove the redundant oxide layer. And secondly, accurately controlling the overlay error (overlay) of the thick gate oxide or the field oxide and the polysilicon, clamping and controlling the size of the thick gate oxide or the thick field oxide extending out of the polysilicon within a certain process tolerance, and increasing the source drain injection energy at the same time, thereby ensuring the normal communication. In the two solutions, the photolithography scheme can obviously increase the process cost; the overlay error control scheme can obviously increase the process difficulty, the process fluctuation of the production line can obviously react on the device, the window of the device is small, meanwhile, the integration of the high-voltage process on the original low-voltage process can be limited due to the adjustment of the source drain injection scheme, and the process ductility is reduced.
Fig. 1 is a flowchart of a method for manufacturing a dual gate structure according to an embodiment of the present application, including the following steps:
s110, obtaining a wafer with a first gate dielectric layer and a second gate dielectric layer formed on a substrate.
Referring to fig. 2a, a first gate dielectric layer 222 is formed on a partial region of the substrate 210, and a second gate dielectric layer 224 is formed on a partial region. The thickness of the first gate dielectric layer 222 is greater than the thickness of the second gate dielectric layer 224, and in one embodiment of the present application, the first gate dielectric layer 222 is thick gate oxide and the second gate dielectric layer 224 is thin gate oxide.
In one embodiment of the present application, the substrate 210 is a semiconductor substrate, and the material may be undoped monocrystalline silicon, monocrystalline silicon doped with impurities, silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-germanium-on-insulator (S-SiGeOI), silicon-germanium-on-insulator (SiGeOI), germanium-on-insulator (GeOI), or the like, and may be at least one of the following materials: si, ge, siGe, siC, siGeC, inAs, gaAs, inP or other III/V compound semiconductors. In the embodiment shown in fig. 2a, the substrate 210 is formed from monocrystalline silicon. An isolation structure such as STI (shallow trench isolation) may also be formed on the substrate 210.
In one embodiment of the present application, the first gate dielectric layer 222 and the second gate dielectric layer 224 may comprise conventional dielectric materials such as oxides, nitrides, and oxynitrides of silicon having a dielectric constant from about 4 to about 20 (measured in vacuum), or the first gate dielectric layer 222 and the second gate dielectric layer 224 may comprise generally higher dielectric constant dielectric materials having a dielectric constant from about 20 to at least about 100. Such higher dielectric constant dielectric materials may include, but are not limited to: hafnium oxide, hafnium silicate, titanium oxide, barium Strontium Titanate (BSTs), and lead zirconate titanate (PZTs).
And S120, forming a gate material layer on the first gate dielectric layer and the second gate dielectric layer.
Referring to fig. 2b, in one embodiment of the present application, the gate material layer 230 is made of polysilicon; in other embodiments, a metal, metal nitride, metal silicide, or similar compound may be used as the material of the gate material layer 230.
In one embodiment of the present application, the gate material layer 230 may be formed by Chemical Vapor Deposition (CVD), such as Low Temperature Chemical Vapor Deposition (LTCVD), low Pressure Chemical Vapor Deposition (LPCVD), rapid thermal chemical vapor deposition (LTCVD), plasma chemical vapor deposition (PECVD), sputtering, physical Vapor Deposition (PVD), and the like. The thickness of the gate material layer 230 may be appropriately used according to the size of the device, and is not particularly limited herein.
And S130, forming a photoetching anti-reflection layer on the grid material layer.
In one embodiment of the present application, the material of the photolithographic anti-reflective layer 232 is silicon oxynitride.
And S140, photoetching and etching the photoetching anti-reflection layer and the grid electrode material layer.
A photoresist is coated on the photoresist anti-reflection layer 232, the photoresist is exposed by using a polysilicon gate mask, the photoresist is developed by using a developing solution, the developed photoresist pattern is as shown in fig. 2c, then the photoresist anti-reflection layer 232 and the gate material layer 230 are etched, a first gate 231 is formed on the first gate dielectric layer 222, and a second gate is formed on the second gate dielectric layer 224, which is not depicted in fig. 2d and 2 e. In one embodiment of the present application, the first gate is the gate of a high voltage device and the second gate is the gate of a low voltage device. In order to avoid that the overlay error causes the two sides of the first gate 231 to extend out of the first gate dielectric layer 222, the design of the polysilicon gate photolithography pattern is to make the width of the first gate 231 smaller than the width of the first gate dielectric layer 222, and the photolithography pattern of the first gate 231 is located on the inner side of the first gate dielectric layer 222 on both sides during photolithography alignment. Referring to fig. 2d, in the embodiment shown in fig. 2d, the width of the first gate dielectric layer 222 is greater than the width of the first gate 231, and both sides of the first gate dielectric layer 222 protrude from the bottom of the first gate 231.
And S150, removing the photoresist, and then removing the first gate dielectric layer extending from the bottom of the first gate electrode by dry etching.
In one embodiment of the present application, the etching of the redundant first gate dielectric layer 222 is accomplished using the difference in the etch selectivity of the material of the photolithographic anti-reflective layer 232 to the first gate dielectric layer 222 and the substrate 210. To ensure that this step is not too excessive to the first gate electrode 231 and the substrate 210, the process is specifically tailored for the thickness of the photoresist layer 232 formed at step S130, as well as the dry etching process at step S150. Adjustment of the etching process may include adjustment of factors such as gas source, plasma, etching tool capability, and etching mechanism. The adjustment of the etching gas may include adjustment of the kind, concentration, mixing ratio, use time, and the like of the gas. The tuning of the plasma may include tuning of the coil, radio frequency Power (RF Power), and temperature. The machine capability adjustment may include adjustment of viscosity coefficient, machine environment, and the like.
In one embodiment of the present application, the etching selectivity ratio of SiON of the photoresist anti-reflection layer 232 to silicon dioxide of the first gate dielectric layer 222 is between 1:1 and 1:2 during the dry etching in step S150, so as to finally ensure that the first gate dielectric layer 222 is etched cleanly without etching SiON. The proportion of the gases used is critical in adjusting the etching selectivity. In one embodiment of the present application, the gas source for the dry etching of step S150 comprises O 2 、CF 4 、C 4 F 8 、CHF 3 And the like, performing step etching for 10 to 90 seconds.
In one embodiment of the present application, the etching is monitored by using an etching END POINT (END POINT) monitoring mechanism, and the change of the etching rate curve is monitored to monitor the etching END POINT, so as to ensure that the first gate dielectric layer 222 uncovered by the first gate 231 and the second gate dielectric layer 224 uncovered by the first gate 231 are etched cleanly, and the photoresist anti-reflection layer 232 is etched cleanly, and the substrate 210, the first gate 231 and the second gate are not over etched. Referring to fig. 2d and fig. 2e, the present application can complete the self-aligned etching of the first gate dielectric layer 222 only by common etching without the need of the high-difficulty and high-precision alignment of the additional first gate electrode 231 and the first gate dielectric layer 222, and the boundary of the etched first gate dielectric layer 222 is automatically aligned with the boundary of the first gate electrode 231.
S160, performing source and drain injection on two sides of the first grid electrode.
Dopant ions are implanted on both sides of the first gate electrode 231 to form a source region and a drain region. Because the portion of the first gate dielectric layer 222 extending out of the bottom of the first gate 231 is removed in step S150, the source-drain implantation is not blocked by the redundant first gate dielectric layer 222, and the source-drain implantation can be fully implanted into the substrate 210, so that the device is ensured not to be broken.
Referring to fig. 3, in one embodiment of the present application, the structure shown in fig. 2a may be formed by:
s102, forming a first dielectric layer in a first area on the substrate.
In one embodiment of the present application, the first dielectric layer may be grown on the substrate 210 through a thermal oxidation process, and the first dielectric layer outside the first region of the substrate may be removed through photolithography and etching, leaving only the first dielectric layer of the first region.
In another embodiment of the present application, a mask layer is formed on the substrate 210, the mask layer is etched and lithographically etched to expose the substrate of the first region, and the mask layer is removed after growing a first dielectric layer on the exposed substrate of the first region.
S104, forming a second dielectric layer on the substrate and the first dielectric layer.
The first dielectric layer of the first region and the second dielectric layer of the first region together serve as a first gate dielectric layer 222, and the second dielectric layer outside the first region serves as a second gate dielectric layer 224.
A second dielectric layer may be grown on the substrate 210 and the first dielectric layer by a thermal oxidation process.
Based on the same inventive concept, the present application further provides a method for manufacturing a field oxide structure, and fig. 4 is a flowchart of a method for manufacturing a field oxide structure according to an embodiment, including the following steps:
s410, a wafer with a field oxide layer and a gate dielectric layer formed on a substrate is obtained.
Referring to fig. 5a, a field oxide layer 522 is formed in a partial region on a substrate 510, and a gate dielectric layer 524 is formed in a partial region. The thickness of the field oxide layer 522 is greater than the thickness of the gate dielectric layer 524, and in one embodiment of the present application, the gate dielectric layer 524 is a gate oxide layer.
In one embodiment of the present application, the substrate 510 is a semiconductor substrate, and the material may be undoped monocrystalline silicon, monocrystalline silicon doped with impurities, silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-germanium-on-insulator (S-SiGeOI), silicon-germanium-on-insulator (SiGeOI), germanium-on-insulator (GeOI), or the like, and may be at least one of the following materials: si, ge, siGe, siC, siGeC, inAs, gaAs, inP or other III/V compound semiconductors. In the embodiment shown in fig. 5a, the substrate 510 is formed from monocrystalline silicon. An isolation structure such as STI (shallow trench isolation) may also be formed on the substrate 510.
In one embodiment of the present application, field oxide layer 522 and gate dielectric layer 524 may comprise conventional dielectric materials such as oxides, nitrides, and oxynitrides of silicon having a dielectric constant from about 4 to about 20 (measured in vacuum), or field oxide layer 522 and gate dielectric layer 524 may comprise generally higher dielectric constant dielectric materials having a dielectric constant from about 20 to at least about 100. Such higher dielectric constant dielectric materials may include, but are not limited to: hafnium oxide, hafnium silicate, titanium oxide, barium Strontium Titanate (BSTs), and lead zirconate titanate (PZTs).
And S420, forming a gate material layer on the field oxide layer and the gate dielectric layer.
Referring to fig. 5b, in one embodiment of the present application, the gate material layer 530 is a polysilicon material; in other embodiments, a metal, metal nitride, metal silicide, or similar compound may be used as the material of the gate material layer 530.
In one embodiment of the present application, the gate material layer 530 may be formed by Chemical Vapor Deposition (CVD), such as Low Temperature Chemical Vapor Deposition (LTCVD), low Pressure Chemical Vapor Deposition (LPCVD), rapid thermal chemical vapor deposition (LTCVD), plasma chemical vapor deposition (PECVD), sputtering, physical Vapor Deposition (PVD), and the like. The thickness of the gate material layer 530 may be appropriately used according to the size of the device, and is not particularly limited herein.
And S430, forming a photoetching anti-reflection layer on the grid material layer.
In one embodiment of the present application, the material of the photolithographic anti-reflective layer 532 is silicon oxynitride.
S440, photoetching and etching the photoetching anti-reflection layer and the grid material layer.
Photoresist is coated on the photoresist anti-reflection layer 532, the photoresist is exposed by using a polysilicon gate photoetching plate, the photoresist is developed by using a developing solution, a photoresist pattern obtained after the development is shown in fig. 5c, and then the photoresist anti-reflection layer 532 and the gate material layer 530 are etched to obtain a gate layer 531. The first side of gate layer 531 (i.e., the left side in fig. 5 d) extends from the edge of field oxide layer 522 onto gate dielectric layer 524, so as to avoid overlay errors that cause the second side of gate layer 531 (i.e., the right side in fig. 5 d) to extend beyond field oxide layer 522, and thus the design of the polysilicon gate photo pattern is such that the second side of gate layer 531 is inside field oxide layer 522 when the photo is aligned. Referring to fig. 5d, in the embodiment shown in fig. 5d, the field oxide layer 522 protrudes from the bottom of the second side of the gate layer 531.
And S450, removing the photoresist, and then removing the field oxide layer extending from the bottom of the second side of the gate layer by dry etching.
In one embodiment of the present application, the etching of the excess gate dielectric layer 522 is accomplished using the difference in etch selectivity of the material of the photolithographic anti-reflective layer 532 to the gate dielectric layer 522 and the substrate 510. To ensure that this step is not too severe to the gate layer 531 and the substrate 510, the process is specifically tailored for the thickness of the photoresist layer 532 formed at step S430, as well as for the dry etching process at step S450. Adjustment of the etching process may include adjustment of factors such as gas source, plasma, etching tool capability, and etching mechanism. The adjustment of the etching gas may include adjustment of the kind, concentration, mixing ratio, use time, and the like of the gas. The tuning of the plasma may include tuning of the coil, rf power, and temperature. The machine capability adjustment may include adjustment of viscosity coefficient, machine environment, and the like.
In one embodiment of the present application, the etching selectivity of SiON of the photoresist anti-reflective layer 532 to silicon dioxide of the field oxide layer 522 is between 1:1 and 1:2 during the dry etching in step S450, so as to finally ensure that the field oxide layer 522 is etched cleanly without etching SiON. In which the ratio of gases usedExamples are key to the modulation selection ratio. In one embodiment of the present application, the gas source for the dry etching of step S450 includes O 2 、CF 4 、C 4 F 8 、CHF 3 And the like, performing step etching for 10 to 90 seconds.
In one embodiment of the present application, the etching is monitored by using an etching END POINT (END POINT) monitoring mechanism, and the change of the etching rate curve is monitored to monitor the etching END POINT, so as to ensure that the field oxide layer 522 uncovered by the gate layer 531 and the gate dielectric layer 524 uncovered by the gate layer 531 are etched completely, and simultaneously, the photoresist anti-reflection layer 532 is etched completely, and the substrate 510 and the gate layer 531 are not over etched. Referring to fig. 5d and fig. 5e, the self-aligned etching of the field oxide layer 522 can be completed only by common etching without the need of high-difficulty and high-precision alignment of the additional gate layer 531 and the field oxide layer 522, and the boundary of the etched field oxide layer 522 is automatically aligned with the boundary of the gate layer 531.
S460, performing source drain injection into the substrate.
Since the portion of the field oxide layer 522 extending out of the bottom of the gate layer 531 is removed in step S450, the source drain implantation is not blocked by the excess field oxide layer 522, so that the device is ensured not to be broken.
Referring to fig. 6, in one embodiment of the present application, the structure shown in fig. 5a may be formed by:
s402, forming a first oxide layer on a substrate.
In one embodiment of the present application, a first oxide layer may be grown on the substrate 510 by a thermal oxidation process.
S404, removing the first oxide layer of the second area.
And removing the redundant first oxide layer by photoetching and etching, and only keeping the first oxide layer in the required area.
And S406, forming a gate dielectric layer in the second region.
The gate dielectric layer 524 may be grown in the second region on the substrate 510 by a thermal oxidation process, and the gate dielectric layer 524 may also be grown on the first oxide layer, where the first oxide layer and the gate dielectric layer 524 on the first oxide layer together serve as the field oxide layer 522.
The above-described method of manufacturing a double gate structure and the method of manufacturing a field oxide structure may be applied to a BCD process, i.e., the BCD process may include steps in the above-described method of manufacturing a double gate structure and/or steps in the method of manufacturing a field oxide structure. Compared with the two exemplary schemes, the manufacturing method of the double-gate structure and the manufacturing method of the field oxide structure can reduce cost and process control difficulty, provide effective compatibility and ductility for process integration of low pressure and high pressure in the BCD process, and provide overall competitiveness of a process platform.
It should be understood that, although the steps in the flowcharts of this application are shown in order as indicated by the arrows, these steps are not necessarily performed in order as indicated by the arrows. The steps are not strictly limited to the order of execution unless explicitly recited herein, and the steps may be executed in other orders. Moreover, at least a portion of the steps in the flowcharts of this application may include a plurality of steps or a plurality of stages, which are not necessarily performed at the same time, but may be performed at different times, and the order of the execution of the steps or stages is not necessarily sequential, but may be performed in turn or alternately with at least a portion of the steps or stages in other steps or others.
In the description of the present specification, reference to the terms "some embodiments," "other embodiments," "desired embodiments," and the like, means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, schematic descriptions of the above terms do not necessarily refer to the same embodiment or example.
The technical features of the above-described embodiments may be arbitrarily combined, and all possible combinations of the technical features in the above-described embodiments are not described for brevity of description, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.
The above examples illustrate only a few embodiments of the invention, which are described in detail and are not to be construed as limiting the scope of the invention. It should be noted that it will be apparent to those skilled in the art that several variations and modifications can be made without departing from the spirit of the invention, which are all within the scope of the invention. Accordingly, the scope of protection of the present invention is to be determined by the appended claims.
Claims (10)
1. A method of fabricating a dual gate structure, comprising:
obtaining a wafer, wherein a first gate dielectric layer and a second gate dielectric layer are formed on a substrate by the wafer, and the thickness of the second gate dielectric layer is smaller than that of the first gate dielectric layer;
forming a gate material layer on the first gate dielectric layer and the second gate dielectric layer;
forming a photoetching anti-reflection layer on the grid material layer;
coating photoresist on the photoetching anti-reflection layer, exposing by using a polysilicon gate photoetching plate, developing the photoresist, etching the photoetching anti-reflection layer and the grid electrode material layer, and forming a first grid electrode on the first grid dielectric layer and a second grid electrode on the second grid dielectric layer; the width of the first gate dielectric layer is larger than that of the first gate, and both sides of the first gate dielectric layer extend out from the bottom of the first gate;
removing the photoresist, and then dry etching a first gate dielectric layer extending from the bottom of the first gate, wherein the photoetching anti-reflection layer is used as a barrier layer of the dry etching; controlling etching conditions to ensure that the photoetching anti-reflection layer is not etched before the extended first gate dielectric layer is etched;
and performing source-drain implantation on two sides of the first grid electrode.
2. The method of claim 1, wherein the material of the photoresist layer comprises silicon oxynitride.
3. The method of claim 1, wherein the first gate dielectric layer and the second gate dielectric layer are both gate oxide layers.
4. The method of claim 1, wherein the gate material layer comprises polysilicon.
5. The method of manufacturing a dual gate structure of claim 1, wherein the step of obtaining a wafer comprises:
forming a first dielectric layer in a first area on the substrate;
forming a second dielectric layer on the substrate and the first dielectric layer;
the first dielectric layer of the first region and the second dielectric layer of the first region are used together as the first gate dielectric layer, and the second dielectric layer outside the first region is used as the second gate dielectric layer.
6. A method of fabricating a field oxide structure, comprising:
obtaining a wafer, wherein a field oxide layer and a gate dielectric layer are formed on a substrate of the wafer, and the thickness of the gate dielectric layer is smaller than that of the field oxide layer;
forming a grid electrode material layer on the field oxide layer and the grid dielectric layer;
forming a photoetching anti-reflection layer on the grid material layer;
coating photoresist on the photoetching anti-reflection layer, exposing the photoresist by using a polysilicon gate photoetching plate, developing the photoresist, and then etching the photoetching anti-reflection layer and a gate material layer to obtain a gate layer, wherein one side of the gate layer extends out of the edge of the field oxide layer onto the gate dielectric layer, and the other side of the gate layer is shorter than the field oxide layer, so that the field oxide layer extends out of the bottom of the other side of the gate layer;
removing the photoresist, and then dry etching a field oxide layer extending from the bottom of the other side of the gate layer, wherein the photoetching anti-reflection layer is used as a barrier layer of the dry etching; controlling etching conditions to ensure that the photoetching anti-reflection layer is not etched before the extended field oxide layer is etched;
and performing source-drain implantation into the substrate.
7. The method of claim 6, wherein the step of obtaining a wafer comprises:
forming a first oxide layer on the substrate;
removing the first oxide layer of the second region;
and forming a gate dielectric layer in the second region, wherein the gate dielectric layer and the first oxide layer which are simultaneously formed on the first oxide layer are used as the field oxide layer together.
8. The method of claim 6, wherein the material of the photoresist layer comprises silicon oxynitride.
9. The method of claim 6, wherein the gate material layer comprises polysilicon.
10. A method for manufacturing a semiconductor device, applied to a BCD process, comprising the steps of the method for manufacturing a double gate structure according to any one of claims 1 to 5 and/or the steps of the method for manufacturing a field oxide structure according to any one of claims 6 to 9.
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