CN116414448A - Microcontroller and control method thereof - Google Patents

Microcontroller and control method thereof Download PDF

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Publication number
CN116414448A
CN116414448A CN202211088331.6A CN202211088331A CN116414448A CN 116414448 A CN116414448 A CN 116414448A CN 202211088331 A CN202211088331 A CN 202211088331A CN 116414448 A CN116414448 A CN 116414448A
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CN
China
Prior art keywords
volatile memory
memory
data
microcontroller
nonvolatile memory
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Application number
CN202211088331.6A
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Chinese (zh)
Inventor
张佑任
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Nuvoton Technology Corp
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Nuvoton Technology Corp
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Publication of CN116414448A publication Critical patent/CN116414448A/en
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/22—Microcontrol or microprogram arrangements
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3206—Monitoring of events, devices or parameters that trigger a change in power modality
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G06F1/329—Power saving characterised by the action undertaken by task scheduling
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

The invention discloses a microcontroller and a control method thereof, wherein the microcontroller comprises: a CPU, a timer, a volatile memory, a non-volatile memory, a peripheral direct memory access device, and a power management unit. The timer may monitor the central processor. If the CPU enters a sleep mode, the timer will start to calculate a predetermined time. When the predetermined time expires, the timer notifies the peripheral DMA device, and the peripheral DMA device performs a move procedure to move a data from the volatile memory to the nonvolatile memory. After the transfer process is performed, the peripheral DMA device notifies the power management unit, which will stop supplying power to the volatile memory and the nonvolatile memory. The invention has the advantages of low power consumption, low complexity, low manufacturing cost and the like.

Description

Microcontroller and control method thereof
Technical Field
The present invention relates to a microcontroller (Microcontroller Unit, MCU), and more particularly to a microcontroller capable of reducing power consumption (Power Consumption).
Background
In conventional microcontrollers, even if the central processing unit (Central Processing Unit, CPU) is operating in sleep mode, many of the relevant components continue to consume power, resulting in overall power consumption that is high. In view of this, a completely new solution is needed to overcome the problems faced by the conventional techniques.
Disclosure of Invention
In a preferred embodiment, the present invention provides a microcontroller comprising: a central processing unit; a timer for monitoring the CPU, wherein if the CPU enters a sleep mode, the timer starts to calculate a set time; a volatile memory storing a data; a nonvolatile memory; a peripheral direct memory access device, wherein when the predetermined time expires, the timer notifies the peripheral direct memory access device, and the peripheral direct memory access device executes a move procedure to move the data from the volatile memory to the nonvolatile memory; and a power management unit, wherein after the transfer procedure is executed, the peripheral direct memory access device notifies the power management unit that power is to be stopped from being supplied to the volatile memory and the nonvolatile memory.
In some embodiments, the timer is reset if the CPU enters a normal operating mode.
In some embodiments, the moving process includes reading the data from the volatile memory and writing the data to the nonvolatile memory.
In some embodiments, the volatile memory is a static random access memory.
In some embodiments, the non-volatile memory is a flash memory.
In another preferred embodiment, the present invention provides a control method of a microcontroller, comprising the steps of: monitoring a central processing unit; if the CPU enters a sleep mode, a timer is used for starting to calculate a set time; when the set time expires, executing a moving program to move a data from a volatile memory to a nonvolatile memory; and stopping supplying power to the volatile memory and the nonvolatile memory after the moving program is executed.
In some embodiments, the control method further comprises: if the CPU enters a normal operation mode, the timer is reset.
In some embodiments, the moving process includes: reading the data from the volatile memory; and writing the data into the nonvolatile memory.
In another preferred embodiment, the present invention provides a microcontroller comprising: a central processing unit; a volatile memory; a nonvolatile memory for storing a data; a power management unit, wherein if the power management unit receives a wake-up signal, the power management unit starts to supply power to the volatile memory and the nonvolatile memory; and a peripheral direct memory access device, wherein after the volatile memory and the nonvolatile memory are supplied, the power management unit notifies the peripheral direct memory access device, and the peripheral direct memory access device executes a move program to move the data from the nonvolatile memory to the volatile memory; after the moving procedure is executed, the peripheral direct memory access element informs the power management unit, and the power management unit controls the CPU to switch from a sleep mode to a normal working mode.
In some embodiments, the wake-up signal is from a general purpose input output interface.
In some embodiments, the moving process includes reading the data from the nonvolatile memory and writing the data into the volatile memory.
In another preferred embodiment, the present invention provides a control method of a microcontroller, comprising the steps of: if a wake-up signal is received, starting to supply power to a volatile memory and a nonvolatile memory; executing a moving program to move a data from the nonvolatile memory to the volatile memory; and after the moving program is executed, controlling a CPU to switch from a sleep mode to a normal working mode.
In some embodiments, the moving process includes: reading the data from the nonvolatile memory; and writing the data into the volatile memory.
The invention has the advantages of low power consumption, low complexity, low manufacturing cost and the like, so that the invention is very suitable for being applied to various electronic devices.
Drawings
Fig. 1 is a schematic diagram of a microcontroller according to an embodiment of the invention.
Fig. 2 is a schematic diagram of a microcontroller according to an embodiment of the invention.
Fig. 3 is a flowchart of a control method of a microcontroller according to an embodiment of the invention.
Fig. 4 is a flowchart of a control method of a microcontroller according to an embodiment of the invention.
Reference numerals:
100,200: microcontroller
110 central processing unit
115 timer
120 volatile memory
130 non-volatile memory
140 peripheral direct memory access device
150 Power management Unit
190 general input output interface
DA data
TD: time of established period
S310, S320, S330, S340, S350, S360, S410, S420, S430, S440: steps
SW wake-up signal
Detailed Description
The following detailed description of the invention refers to the accompanying drawings, which illustrate specific embodiments of the invention.
Certain terms are used throughout the description and claims to refer to particular components. Those of ordinary skill in the art will appreciate that a hardware manufacturer may refer to the same element by different names. The description and claims do not take the form of an element differentiated by name, but rather by functional differences. In the following description and in the claims, the terms "include" and "comprise" are used in an open-ended fashion, and thus should be interpreted to mean "include, but not limited to. The term "substantially" means that within an acceptable error range, a person skilled in the art can solve the technical problem within a certain error range, and achieve the basic technical effect. In addition, the term "coupled" in this specification includes any direct or indirect electrical connection. Accordingly, if a first device couples to a second device, that connection may be through a direct electrical connection, or through an indirect electrical connection via other devices and connections.
Fig. 1 is a schematic diagram of a microcontroller (Microcontroller Unit, MCU) 100 according to an embodiment of the invention. The microcontroller 100 may be applied to an electronic device, for example: a personal Computer (Personal Computer), a Smart Phone (Smart Phone), a Tablet Computer (Tablet Computer), or a notebook Computer (Notebook Computer). In the embodiment of fig. 1, the microcontroller 100 comprises: a central processing unit (Central Processing Unit, CPU) 110, a Timer (Timer) 115, a Volatile Memory (Volatile Memory) 120, a Non-Volatile Memory (Non-Volatile Memory) 130, a peripheral direct Memory access (Peripheral Direct Memory Access, PDMA) element 140, and a power management unit (Power Management Unit, PMU) 150. It must be understood that although not shown in fig. 1, the microcontroller 100 may also include other elements, such as: a power module (Power Supply Module) or (and) a Housing (Housing).
The CPU 110 may operate in a normal operation Mode (Power-on Mode), a sleep Mode (Power-Down Mode), or a Power-off Mode (Power-off Mode). For example, in the sleep mode, the CPU 110 may operate in a relatively power saving manner, but is not completely powered down. The timer 115 may monitor the status of the central processor 110. If the CPU 110 enters sleep mode, the timer 115 will start counting a predetermined time TD. It must be noted that the timer 115 performs the calculation operation only when the cpu 110 is in the sleep mode. Conversely, if the CPU 110 leaves sleep mode and enters normal operating mode, the timer 115 will be Reset (Reset). In some embodiments, the predetermined time TD may be set to be between 0.5ms and 10ms, for example: 1ms, but is not limited thereto.
Initially, the power management unit 150 may supply power to the volatile memory 120 and the nonvolatile memory 130, wherein the volatile memory 120 may store a data DA. In some embodiments, the volatile Memory 120 is a static random access Memory (Static Random Access Memory, SRAM), and the nonvolatile Memory 130 is a Flash Memory (Flash Memory). However, the present invention is not limited thereto. In other embodiments, the volatile memory 120 and the nonvolatile memory 130 may be implemented with different types of memory.
When the set time TD of the timer 115 expires, no action is taken on behalf of the cpu 110 for a period of time. At this time, the timer 115 may inform the peripheral direct memory access device 140, and the peripheral direct memory access device 140 may execute a Moving Process (Moving Process) to move the data DA from the volatile memory 120 to the nonvolatile memory 130. In some embodiments, the foregoing moving procedure may include: (1) The peripheral direct memory access element 140 reads (reads) the data DA from the volatile memory 120; and (2) the peripheral direct memory access device 140 writes (Write) the data DA to the nonvolatile memory 130, but is not limited thereto.
After the foregoing relocation procedure is performed, the peripheral direct memory access device 140 may inform the power management unit 150, and the power management unit 150 will stop supplying power to the volatile memory 120 and the nonvolatile memory 130. Because the data DA is already stored in the nonvolatile memory 130, no data loss occurs due to the interruption of the power supply. In addition, since the power supplies of the volatile memory 120 and the nonvolatile memory 130 are removed, the overall power consumption of the microcontroller 100 can be greatly reduced. It should be noted that during the foregoing operation, the microcontroller 100 does not wake up the cpu 110 in the sleep mode. Therefore, the present invention can further suppress the power consumption in the sleep mode without being controlled by the cpu 110.
Fig. 2 is a schematic diagram of a microcontroller 200 according to an embodiment of the invention. In the embodiment of fig. 2, microcontroller 200 includes: a central processing unit 110, a volatile memory 120, a nonvolatile memory 130, a peripheral direct memory access device 140, and a power management unit 150. The embodiment of fig. 2 may be considered a reply operation corresponding to the embodiment of fig. 1.
Initially, the cpu 110 may operate in a sleep mode in which the power management unit 150 does not supply power to the volatile memory 120 and the nonvolatile memory 130. That is, both the volatile memory 120 and the nonvolatile memory 130 are in a power-off state, and the nonvolatile memory 130 has stored therein a data DA, which may have been previously moved from the volatile memory 120.
If the power management unit 150 receives a Wake-up Signal (SW), the power management unit 150 starts to supply power to the volatile memory 120 and the nonvolatile memory 130. In some embodiments, the wake-up signal SW is from a General-Purpose Input/Output (GPIO) interface 190, wherein the wake-up signal SW is generated according to a user Input. For example, if the user presses a physical button on the microcontroller 200, a wake-up signal SW is generated and input to the power management unit 150. It must be noted that the general purpose input output interface 190 is not part of the microcontroller 200.
Then, after the volatile memory 120 and the nonvolatile memory 130 have been supplied with power, the power management unit 150 may inform the peripheral direct memory access device 140, and the peripheral direct memory access device 140 may execute another moving procedure to move the data DA from the nonvolatile memory 130 to the volatile memory 120. In some embodiments, the foregoing moving procedure may include: (1) The peripheral direct memory access element 140 reads (reads) the data DA from the nonvolatile memory 130; and (2) the peripheral DMA device 140 writes (writes) the data DA into the volatile memory 120, but is not limited thereto.
After the foregoing relocation procedure is performed, the peripheral DMA device 140 may notify the power management unit 150, and the power management unit 150 may control the CPU 110 to switch from the sleep mode to a normal operation mode. At this time, the data DA is recovered and stored in the volatile memory 120, so that the cpu 110 can execute various programs using the data DA immediately after being awakened, without any operation delay. Therefore, the design of the invention helps to reduce the overall power consumption while maintaining the smoothness of the overall system operation.
Fig. 3 is a flowchart of a control method of a microcontroller according to an embodiment of the invention. First, in step S310, a cpu is monitored. In step S320, it is determined whether the cpu enters a sleep mode. If not, the process returns to step S310. If yes, in step S330, a timer is used to start calculating a predetermined time. In step S340, it is checked whether the predetermined time has expired. If not, the process returns to step S340. If yes, in step S350, a moving procedure is performed to move a data from a volatile memory to a nonvolatile memory. Finally, in step S360, the supply of power to the volatile memory and the nonvolatile memory is stopped. It should be understood that the above steps are not required to be performed sequentially, and each feature of the microcontroller 100 of fig. 1 can be applied to the control method of fig. 3.
Fig. 4 is a flowchart of a control method of a microcontroller according to an embodiment of the invention. First, in step S410, it is determined whether a wake-up signal is received. If not, the process returns to step S410. If yes, in step S420, power supply to a volatile memory and a nonvolatile memory is started. In step S430, a moving procedure is performed to move a data from the nonvolatile memory to the volatile memory. Finally, in step S440, a cpu is controlled to switch from a sleep mode to a normal operation mode. It should be understood that the above steps need not be performed sequentially, and each feature of the microcontroller 200 of fig. 2 can be applied to the control method of fig. 4.
The invention provides a novel microcontroller and a control method. Compared with the traditional design, the invention has the advantages of at least low power consumption, low complexity, low manufacturing cost and the like, so that the invention is very suitable for being applied to various electronic devices.
It should be noted that the above-mentioned device parameters are not limitations of the present invention. The designer can adjust these settings according to different needs. The microcontroller and control method of the present invention are not limited to the states shown in fig. 1-4. The present invention may include only any one or more features of any one or more of the embodiments of fig. 1-4. In other words, not all of the features of the drawings need be implemented in the microcontroller and control method of the present invention at the same time.
The methods of the invention, or specific aspects or portions thereof, may exist in the form of codes. The code may be embodied in a tangible medium, such as a floppy diskettes, CD-ROMs, hard drives, or any other machine-readable storage medium, or any computer program product, wherein, when the code is loaded into and executed by a machine, such as a computer, the machine becomes an apparatus for practicing the invention. The code may also be transmitted over some transmission medium, such as over electrical wiring or cabling, through fiber optics, or via any other form of transmission, wherein, when the code is received and loaded into and executed by a machine, such as a computer, the machine becomes an apparatus for practicing the invention. When implemented in a general-purpose processing unit, the code combines processing units to provide a unique apparatus that operates analogously to application specific logic circuits.
Ordinal numbers such as "first," "second," "third," and the like in the description and in the claims are used for distinguishing between two different elements having the same name and not necessarily for describing a sequential order.
While the invention has been described with reference to the preferred embodiments, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.

Claims (10)

1. A microcontroller, comprising:
a central processing unit;
a timer for monitoring the CPU, wherein if the CPU enters a sleep mode, the timer starts to calculate a set time;
a volatile memory storing a data;
a nonvolatile memory;
a peripheral direct memory access device, wherein when the predetermined time expires, the timer notifies the peripheral direct memory access device, and the peripheral direct memory access device executes a move procedure to move the data from the volatile memory to the nonvolatile memory; and
and a power management unit, wherein after the transfer process is executed, the peripheral DMA device notifies the power management unit, and the power management unit stops supplying power to the volatile memory and the nonvolatile memory.
2. The microcontroller of claim 1 wherein the move program includes reading the data from the volatile memory and writing the data to the nonvolatile memory.
3. The microcontroller of claim 1 wherein the nonvolatile memory is a flash memory.
4. A control method of a microcontroller, comprising:
monitoring a central processing unit;
if the CPU enters a sleep mode, a timer is used for starting to calculate a set time;
when the set time expires, executing a moving program to move a data from a volatile memory to a nonvolatile memory; and
after the moving program is executed, power supply to the volatile memory and the nonvolatile memory is stopped.
5. The control method of claim 4, wherein the volatile memory is a static random access memory.
6. A microcontroller, comprising:
a central processing unit;
a volatile memory;
a nonvolatile memory for storing a data;
a power management unit, wherein if the power management unit receives a wake-up signal; the power management unit will begin to supply power to the volatile memory and the non-volatile memory; and
a peripheral direct memory access device, wherein after the volatile memory and the nonvolatile memory are supplied, the power management unit notifies the peripheral direct memory access device, and the peripheral direct memory access device executes a move program to move the data from the nonvolatile memory to the volatile memory;
after the moving procedure is executed, the peripheral direct memory access element informs the power management unit, and the power management unit controls the CPU to switch from a sleep mode to a normal working mode.
7. The microcontroller of claim 6 wherein the wake-up signal is from a general purpose input output interface.
8. The microcontroller of claim 6 wherein the move program includes reading the data from the nonvolatile memory and writing the data to the volatile memory.
9. A control method of a microcontroller, comprising:
if a wake-up signal is received, starting to supply power to a volatile memory and a nonvolatile memory;
executing a moving program to move a data from the nonvolatile memory to the volatile memory; and
after the moving program is executed, a CPU is controlled to switch from a sleep mode to a normal working mode.
10. The control method of claim 9, wherein the moving procedure comprises:
reading the data from the nonvolatile memory; and
writing the data into the volatile memory.
CN202211088331.6A 2021-12-30 2022-09-07 Microcontroller and control method thereof Pending CN116414448A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
TW110149611A TW202326357A (en) 2021-12-30 2021-12-30 Microcontroller unit and control method thereof
TW110149611 2021-12-30

Publications (1)

Publication Number Publication Date
CN116414448A true CN116414448A (en) 2023-07-11

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TW (1) TW202326357A (en)

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