CN116404030A - Current aperture vertical electron transistor and preparation method thereof - Google Patents
Current aperture vertical electron transistor and preparation method thereof Download PDFInfo
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- 238000002360 preparation method Methods 0.000 title abstract description 8
- 230000004888 barrier function Effects 0.000 claims abstract description 136
- 230000000903 blocking effect Effects 0.000 claims abstract description 60
- 239000000758 substrate Substances 0.000 claims abstract description 51
- 230000005533 two-dimensional electron gas Effects 0.000 claims abstract description 20
- 230000000670 limiting effect Effects 0.000 claims abstract description 7
- 238000000034 method Methods 0.000 claims description 61
- 238000005530 etching Methods 0.000 claims description 22
- 238000004519 manufacturing process Methods 0.000 claims description 13
- 238000001259 photo etching Methods 0.000 claims description 11
- 229910002704 AlGaN Inorganic materials 0.000 claims description 7
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims description 5
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 5
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 claims description 4
- 238000005468 ion implantation Methods 0.000 claims 1
- 238000002248 hydride vapour-phase epitaxy Methods 0.000 description 16
- 229910002601 GaN Inorganic materials 0.000 description 15
- 238000000206 photolithography Methods 0.000 description 9
- 238000005229 chemical vapour deposition Methods 0.000 description 8
- 229910052751 metal Inorganic materials 0.000 description 8
- 239000002184 metal Substances 0.000 description 8
- 230000000694 effects Effects 0.000 description 6
- 239000004065 semiconductor Substances 0.000 description 5
- 239000002210 silicon-based material Substances 0.000 description 5
- 239000013078 crystal Substances 0.000 description 4
- 238000013461 design Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910003465 moissanite Inorganic materials 0.000 description 1
- 239000012466 permeate Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
- H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
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Abstract
The invention provides a current aperture vertical electron transistor and a preparation method thereof, wherein the transistor comprises: a substrate; a contact layer; a drift layer; the current blocking layer is provided with a current hole; a back barrier layer; a channel layer; the top barrier layer and the channel layer form a two-dimensional electron gas channel; the grid electrode is arranged on the top barrier layer and correspondingly arranged above the current hole; the drain electrode is arranged on the bottom surface of the substrate; a source electrode disposed on the top barrier layer; the back barrier layer is provided with a through hole in a region corresponding to the grid electrode, and the aperture of the through hole is smaller than or equal to the radial dimension of the grid electrode and larger than or equal to the aperture of the current hole of the current barrier layer. The current aperture vertical electron transistor has better electron limiting effect, can effectively prevent electrons from drifting in a channel layer outside two-dimensional electron gas, reduce leakage current of the transistor, and improve the switching speed of the transistor, so that the grid electrode can more effectively control the switching of the transistor.
Description
Technical Field
The invention belongs to the field of semiconductor integrated circuit design and manufacture, and particularly relates to a current aperture vertical electronic transistor and a preparation method thereof.
Background
Currently, the mainstream power semiconductor devices (power electronic devices) still mainly use silicon materials, but the silicon materials have low breakdown voltage resistance, and the design and process reach the material limit, so that the silicon materials become the main problems for restricting the development of the silicon materials. The third generation semiconductors (also called wide bandgap semiconductors) represented by SiC and GaN gradually permeate into industries such as electric automobiles, power supplies, consumer electronics and the like in the field of power semiconductors, so that partial substitution of silicon-based materials is realized, and excellent performances are realized in the aspects of miniaturization, low power consumption, high frequency and the like.
An important form of current GaN power devices is the current aperture vertical electron transistor (Current aperture vertical electron transistor, CAVET). However, at present, the current aperture vertical electron transistor is mainly formed by P-type GaN serving as a current blocking layer, channel communication and pinch-off are realized by controlling two-dimensional electron gas through a grid electrode, electrons can cross the channel and pass through an intrinsic GaN layer to flow to the current aperture under high-voltage bias, so that leakage current is increased, the control effect of the grid electrode is reduced, and the reliability of the device is affected.
It should be noted that the foregoing description of the background art is only for the purpose of facilitating a clear and complete description of the technical solutions of the present application and for the convenience of understanding by those skilled in the art. The above-described solutions are not considered to be known to the person skilled in the art simply because they are set forth in the background section of the present application.
Disclosure of Invention
In view of the above-mentioned drawbacks of the prior art, an object of the present invention is to provide a current aperture vertical electron transistor and a method for manufacturing the same, which are used for solving the problems that in the prior art, under high voltage bias, electrons can cross a channel and pass through an intrinsic GaN layer to flow to a current aperture, so that leakage current is increased, control effect of a gate is reduced, and reliability of a device is affected.
To achieve the above and other related objects, the present invention provides a current aperture vertical electron transistor comprising: a substrate; a contact layer disposed on the substrate; a drift layer disposed on the contact layer; the current blocking layer is arranged on the drift layer, and is internally provided with a current hole for limiting a current path; a back barrier layer disposed on the current blocking layer; a channel layer arranged on the current blocking layer and the back barrier layer and filled in the current hole; the top barrier layer is arranged on the channel layer, and the top barrier layer and the channel layer form a two-dimensional electron gas channel; the grid electrode is arranged on the top barrier layer and correspondingly arranged above the current hole; the drain electrode is arranged on the bottom surface of the substrate; the source electrode is arranged on the top barrier layer and arranged on the periphery of the grid structure; and the area of the back barrier layer corresponding to the grid electrode is provided with a through hole, and the aperture of the through hole is smaller than or equal to the radial size of the grid electrode and larger than or equal to the aperture of the current hole of the current barrier layer.
Optionally, the projection of the through hole of the back barrier layer on the gate is completely covered by the gate.
Optionally, the back barrier layer is in direct contact with the current blocking layer.
Optionally, the back barrier layer is embedded in the channel layer, the back barrier layer and the current blocking layer are separated by a part of thickness of the channel layer, and the distance between the top surface of the back barrier layer and the top surface of the channel layer is 30-50 nanometers.
Optionally, the substrate is an n-type doped GaN substrate or an SiC substrate, the contact layer is an n-type heavily doped GaN layer, and the carrier concentration is greater than 1e18/cm 3 The thickness of the contact layer ranges from 200 nanometers to 500 nanometers, the drift layer is an n-type lightly doped GaN layer, and the carrier concentration is 1e15/cm 3 ～1e17/cm 3 The thickness of the drift layer ranges from 1 micron to 100 microns, and the current blocking layer is a p-type GaN layer.
Optionally, the back barrier layer comprises one or more of AlGaN, inGaN, alInGaN, inAlN and AlN, and has a thickness in the range of 15 nm to 30 nm.
Optionally, the channel layer includes an intrinsic GaN layer, the thickness of the channel layer ranges from 100 nm to 200 nm, the top barrier layer includes one of AlGaN, inGaN, alInGaN, inAlN and AlN, and the thickness of the top barrier layer ranges from 15 nm to 30 nm.
Optionally, the gate includes one of a trench gate, a p-type conductive gate, an insulated gate, a floating gate, an ion-implanted gate, and a schottky gate.
The invention also provides a preparation method of the current aperture vertical electron transistor, which comprises the following steps: providing a substrate; forming a contact layer on the substrate; forming a drift layer on the contact layer; sequentially forming a current blocking layer and a back barrier layer on the drift layer, forming a through hole in the back barrier layer and forming a current hole in the current blocking layer, wherein the current hole is used for limiting a current path, and the through hole is larger than or equal to the aperture of the current hole of the current blocking layer; forming a channel layer on the current blocking layer and the back barrier layer, wherein the channel layer is filled in the current hole and the through hole; forming a top barrier layer on the channel layer, wherein the top barrier layer and the channel layer form a two-dimensional electron gas channel; forming a grid electrode and a source electrode on the top barrier layer, wherein the grid electrode is arranged on the top barrier layer and correspondingly arranged above the current hole, the aperture of the through hole is smaller than or equal to the radial dimension of the grid electrode, and the source electrode is arranged on the periphery of the grid electrode structure; and thinning the substrate and forming a drain electrode on the bottom surface of the substrate.
Optionally, forming the through hole and the current hole in the back barrier layer and the current barrier layer simultaneously through a photoetching process and an etching process, wherein the apertures of the through hole and the current hole are equal;
or forming a through hole in the back barrier layer through one photoetching process and etching process, and then forming a current hole in the current barrier layer through another photoetching process and etching process, wherein the aperture of the through hole is larger than that of the current hole.
The invention also provides a preparation method of the current aperture vertical electron transistor, which comprises the following steps: providing a substrate; forming a contact layer on the substrate; forming a drift layer on the contact layer; forming a current blocking layer on the drift layer, forming a bottom channel layer on the current blocking layer, forming a back barrier layer on the bottom channel layer, and forming a via in the back barrier layer and the bottom channel layer and a current aperture in the current blocking layer, the current aperture for defining a current path, the via being greater than or equal to an aperture of the current blocking layer; forming a top channel layer on the back barrier layer, and the top channel layer filling in the via hole and the current hole; forming a top barrier layer on the top channel layer, the top barrier layer and the top channel layer forming a two-dimensional electron gas channel; forming a grid electrode and a source electrode on the top barrier layer, wherein the grid electrode is arranged on the top barrier layer and correspondingly arranged above the current hole, the aperture of the through hole is smaller than or equal to the radial dimension of the grid electrode, and the source electrode is arranged on the periphery of the grid electrode structure; and thinning the substrate and forming a drain electrode on the bottom surface of the substrate.
Optionally, forming the through hole and the current hole in the back barrier layer, the bottom channel layer and the current barrier layer simultaneously through a photolithography process and an etching process, wherein the apertures of the through hole and the current hole are equal; or forming through holes in the back barrier layer and the bottom channel layer through one photoetching process and etching process, and then forming current holes in the current blocking layer through another photoetching process and etching process, wherein the aperture of the through holes is larger than that of the current holes.
As described above, the current aperture vertical electron transistor and the method for manufacturing the same of the present invention have the following advantageous effects:
the invention provides a current aperture vertical electron transistor with a back barrier layer and a preparation method thereof, wherein the current aperture vertical electron transistor has better electron limiting effect, can effectively prevent electrons from drifting in a channel layer outside two-dimensional electron gas, reduce leakage current of the transistor, and improve the switching speed of the transistor, so that a grid electrode can more effectively control the switching of the transistor.
Drawings
The accompanying drawings, which are included to provide a further understanding of the embodiments of the application and are incorporated in and constitute a part of this specification, illustrate embodiments of the application and together with the description serve to explain the principles of the application. It is apparent that the drawings in the following description are only some of the embodiments of the present application.
Fig. 1 to 7 are schematic structural views showing steps of a method for manufacturing a vertical electron transistor with a current aperture according to embodiment 1 of the present invention.
Fig. 8 to 14 are schematic structural views showing steps of a method for manufacturing a vertical electron transistor with a current aperture according to embodiment 2 of the present invention.
Description of element reference numerals
101. 201 contact layer
102. 202 drift layer
103. 203 current blocking layer
104. 204 back barrier layer
105. 205 through hole
106. 206 current hole
107. Channel layer
207a bottom channel layer
207b top channel layer
108. 208 top barrier layer
109. 209 drain electrode
110. 210 grid electrode
111. 211 source electrode
Detailed Description
Other advantages and effects of the present invention will become apparent to those skilled in the art from the following disclosure, which describes the embodiments of the present invention with reference to specific examples. The invention may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present invention.
It should be emphasized that the term "comprises/comprising" when used herein is taken to specify the presence of stated features, integers, steps or components but does not preclude the presence or addition of one or more other features, integers, steps or components.
Features that are described and/or illustrated with respect to one embodiment may be used in the same way or in a similar way in one or more other embodiments in combination with or instead of the features of the other embodiments.
As described in detail in the embodiments of the present invention, the cross-sectional view of the device structure is not partially enlarged to a general scale for convenience of explanation, and the schematic drawings are only examples, which should not limit the scope of the present invention. In addition, the three-dimensional dimensions of length, width and depth should be included in actual fabrication.
For ease of description, spatially relative terms such as "under", "below", "beneath", "above", "upper" and the like may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that these spatially relative terms are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the figures. Furthermore, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers or one or more intervening layers may also be present.
In the context of this application, a structure described as a first feature being "on" a second feature may include embodiments where the first and second features are formed in direct contact, as well as embodiments where additional features are formed between the first and second features, such that the first and second features may not be in direct contact.
It should be noted that, the illustrations provided in the present embodiment merely illustrate the basic concept of the present invention by way of illustration, and only the components related to the present invention are shown in the drawings rather than the number, shape and size of the components in actual implementation, and the form, number and proportion of each component in actual implementation may be arbitrarily changed, and the layout of the components may be more complex.
Example 1
As shown in fig. 7, the present embodiment provides a current aperture vertical electron transistor, which includes: a substrate, a contact layer 101, a drift layer 102, a current blocking layer 103, a back barrier layer 104, a channel layer 107, a top barrier layer 108, a gate 110, a drain 109, and a source 111.
In one embodiment, the contact layer 101 is an n-type heavily doped GaN layer with a carrier concentration of greater than 1e18/cm 3 The thickness of the contact layer 101 ranges from 200 nm to 500 nm. In a specific example, the carrier concentration of the contact layer 101 is 5e18/cm 3 The thickness of the contact layer 101 is 300 nm. In one specific example, the contact layer 101 is part of a substrate. In another specific example, the contact layer 101 is formed over a substrate.
In one embodiment, as shown in fig. 7, the drift layer 102 is disposed on the contact layer 101; the drift layer 102 is an n-type lightly doped GaN layer with carrier concentration of 1e15/cm 3 ～1e17/cm 3 The thickness of the drift layer 102 ranges from 1 micron to 100 microns. In a specific example, the carrier concentration of the drift layer 102 is 1e16/cm 3 The drift layer 102 has a thickness in the range of 50 microns.
In one embodiment, as shown in fig. 7, the current blocking layer 103 is disposed on the drift layer 102, and a current hole 106 is disposed in the current blocking layer 103, where the current hole 106 is used to define a current path. In a specific example, the current blocking layer 103 is a p-type GaN layer.
In one embodiment, as shown in fig. 7, the back barrier layer 104 is disposed on the current blocking layer 103; the region of the back barrier layer 104 corresponding to the gate 110 is provided with a via 105, and the aperture of the via 105 is smaller than or equal to the radial dimension of the gate 110 and larger than or equal to the aperture of the current hole 106 of the current blocking layer 103.
In one embodiment, as shown in fig. 7, the projection of the via 105 of the back barrier layer 104 onto the gate 110 is completely covered by the gate 110. In this example, since the projection of the through hole 105 of the back barrier layer 104 on the gate 110 is completely covered by the gate 110, that is, the back barrier layer 104 covers at least the two-dimensional electron gas region except the gate 110, the control capability of the gate 110 on the two-dimensional electron gas channel near the current hole 106 can be improved, the electron leakage of the two-dimensional electron gas channel in the region except the gate 110 can be avoided, and the leakage current can be reduced.
In one embodiment, as shown in fig. 7, the back barrier layer 104 is in direct contact with the current blocking layer 103. In this example, the back barrier layer 104 is in direct contact with the current blocking layer 103, so that the process steps can be effectively reduced, and the manufacturing cost can be reduced.
In one embodiment, the back barrier layer 104 comprises one or more of AlGaN, inGaN, alInGaN, inAlN and AlN, and the back barrier layer 104 has a thickness in the range of 15 nm to 30 nm. In one specific example, the back barrier layer 104 may have a thickness of 20 nanometers. On the one hand, the barrier layer can effectively prevent electrons from drifting in the channel layer outside the two-dimensional electron gas, reduce the leakage current of the transistor, and promote the switching speed of the transistor, so that the gate 110 can more effectively control the switching of the transistor, on the other hand, on the premise of meeting the above effects, the thickness of the back barrier layer 104 is controlled, so that excessive increase of the thickness of the channel layer 107 can be avoided, and increase of the on-resistance of the transistor is avoided.
In one embodiment, as shown in fig. 7, the channel layer 107 is disposed on the current blocking layer 103 and the back barrier layer 104 and fills the current hole 106.
In one embodiment, the channel layer 107 includes an intrinsic GaN layer, the thickness of the channel layer 107 ranges from 100 nm to 200 nm, and the channel layer 107 has a certain thickness on the basis of completely covering the back barrier layer 104, so that a two-dimensional electron gas channel can be formed with the top barrier layer 108. In one specific example, the channel layer 107 has a thickness in the range of 100 nanometers.
In one embodiment, as shown in fig. 7, the top barrier layer 108 is disposed on the channel layer, the top barrier layer 108 and the channel layer 107 forming a two-dimensional electron gas channel. The top barrier layer 108 comprises one of AlGaN, inGaN, alInGaN, inAlN and AlN, and the top barrier layer 108 has a thickness in the range of 15 nm to 30 nm. In a specific example, the top barrier layer 108 is an AlGaN layer, and the top barrier layer 108 has a thickness of 20 nanometers.
In one embodiment, the gate 110 is disposed on the top barrier layer 108 and correspondingly over the current aperture 106; the drain electrode 109 is disposed at the bottom of the substrate or the bottom surface of the contact layer 101 exposed after the substrate is thinned (i.e., the substrate may remain full or partial thickness, or may be removed completely to expose the bottom surface of the contact layer 101); the source 111 is disposed on the top barrier layer 108 and is disposed on the periphery of the gate 110 structure;
in one embodiment, the gate 110 includes one of a trench gate, a p-type conductive gate, an insulated gate, a floating gate, an ion-implanted gate, and a schottky gate. In one specific example, the gate 110 is a p-type conductive gate that can deplete the two-dimensional electron gas channel underneath, leaving the transistor in a normally off state.
As shown in fig. 1 to 7, the present embodiment further provides a method for preparing a current aperture vertical electron transistor, where the basic parameters of the current aperture vertical electron transistor can be referred to the above examples, and the method includes the steps of:
as shown in fig. 1, step 1) is performed first, and a substrate is provided; 2) Forming a contact layer 101 on the substrate; 3) A drift layer 102 is formed on the contact layer 101.
In one embodiment, the substrate may be an n-type doped gallium nitride single crystal substrate or a silicon carbide single crystal substrate, or the like.
In one embodiment, the drift layer 102 may be formed on the contact layer 101 of the substrate by a Metal Organic Chemical Vapor Deposition (MOCVD) process or Hydride Vapor Phase Epitaxy (HVPE).
As shown in fig. 2 to 4, step 4) is then performed, a current blocking layer 103 and a back barrier layer 104 are sequentially formed on the drift layer 102, a via 105 is formed in the back barrier layer 104, and a current hole 106 is formed in the current blocking layer 103, the current hole 106 is used for defining a current path, and the via 105 is greater than or equal to the aperture of the current hole 106 of the current blocking layer 103.
For example, the current blocking layer 103 and the back barrier layer 104 may be sequentially formed on the drift layer 102 by a Metal Organic Chemical Vapor Deposition (MOCVD) process or a Hydride Vapor Phase Epitaxy (HVPE).
Then, the via hole 105 and the current hole 106 may be etched by a photolithography process and an etching process (e.g., an ICP etching process), and in particular, the via hole 105 and the current hole 106 may be formed by:
the through hole 105 and the current hole 106 are formed in the back barrier layer 104 and the current blocking layer 103 simultaneously through a photolithography process and an etching process, and the apertures of the through hole 105 and the current hole 106 are equal.
Or a via 105 is formed in the back barrier layer 104 by one photolithography process and etching process, and then a current hole 106 is formed in the current blocking layer 103 by another photolithography process and etching process, the via 105 having a larger aperture than the current hole 106, as shown in fig. 4.
As shown in fig. 5, step 5) is then performed, a channel layer 107 is formed on the current blocking layer 103 and the back barrier layer 104, and the channel layer 107 is filled in the current hole 106 and the via hole 105.
For example, to obtain a planar surface of the channel layer 107, the channel layer 107 may be formed on the current blocking layer 103 and the back barrier layer 104 by a Metal Organic Chemical Vapor Deposition (MOCVD) process or Hydride Vapor Phase Epitaxy (HVPE) at a temperature higher than 1150 ℃.
As shown in fig. 6, step 6) is then performed to form a top barrier layer 108 on the channel layer 107, the top barrier layer 108 forming a two-dimensional electron gas channel with the channel layer 107.
The top barrier layer 108 may be formed on the channel layer 107 by, for example, a metal organic chemical vapor deposition process (MOCVD) or Hydride Vapor Phase Epitaxy (HVPE).
As shown in fig. 7, step 7) is then performed, forming a gate 110 and a source 111 on the top barrier layer 108, wherein the gate 110 is disposed on the top barrier layer 108 and is correspondingly disposed above the current hole 106, the aperture of the via 105 is smaller than or equal to the radial dimension of the gate 110, and the source 111 is disposed on the periphery of the gate 110 structure; finally, step 8) is performed, the substrate is thinned, the contact layer 101 is exposed, and a drain electrode 109 is formed on the bottom surface of the contact layer 101; or thinning the substrate and forming a drain 109 on the bottom surface of the remaining portion of the substrate.
Example 2
As shown in fig. 14, the present embodiment provides a current aperture vertical electron transistor having the same basic structure as that of embodiment 1, wherein the difference from embodiment 1 is that: the back barrier layer 204 is embedded in the channel layers 207a, 207b, the back barrier layer 204 and the current blocking layer 203 are separated by a partial thickness of the channel layer 207a, and the distance between the top surface of the back barrier layer 204 and the top surface of the channel layer 207b is 30 nm to 50 nm.
As shown in fig. 8 to 14, the present embodiment further provides a method for manufacturing a current aperture vertical electron transistor, where the basic parameters of the current aperture vertical electron transistor can be referred to the above examples, and the method includes the steps of:
as shown in fig. 8, step 1) is performed first, and a substrate is provided; 2) Forming a contact layer 201 on the substrate; 3) A drift layer 202 is formed on the contact layer 201.
In one embodiment, the substrate may be a gallium nitride single crystal substrate, a silicon carbide single crystal substrate, or the like.
In one embodiment, the drift layer 202 may be formed on the contact layer 201 of the substrate by a metal organic chemical vapor deposition process (MOCVD) or Hydride Vapor Phase Epitaxy (HVPE).
As shown in fig. 9 to 11, step 4) is then performed, a current blocking layer 203 is formed on the drift layer 202, a bottom channel layer 207a is formed on the current blocking layer 203, a back barrier layer 204 is formed on the bottom channel layer 207a, and a via hole 205 is formed in the back barrier layer 204 and the bottom channel layer 207a and a current hole 206 is formed in the current blocking layer 203, the current hole 206 defining a current path, the via hole 205 being greater than or equal to the aperture of the current hole 206 of the current blocking layer 203.
For example, the current blocking layer 203, the bottom channel layer 207a, and the back barrier layer 204 may be sequentially formed on the drift layer 202 by a Metal Organic Chemical Vapor Deposition (MOCVD) process or a Hydride Vapor Phase Epitaxy (HVPE).
Then, the via hole 205 and the current hole 206 may be etched by a photolithography process and an etching process (e.g., an ICP etching process), and in particular, the via hole 205 and the current hole 206 may be formed by:
forming the through hole 205 and the current hole 206 in the back barrier layer 204, the bottom channel layer 207a and the current blocking layer 203 simultaneously by a photolithography process and an etching process, wherein the apertures of the through hole 205 and the current hole 206 are equal; or a via 205 is formed in the back barrier layer 204 and the bottom channel layer 207a by one photolithography process and etching process, and then a current hole 206 is formed in the current blocking layer 203 by another photolithography process and etching process, the via 205 having a larger aperture than the current hole 206, as shown in fig. 4.
As shown in fig. 12, step 5) is then performed, a top channel layer 207b is formed on the back barrier layer 204, and the top channel layer 207b fills the via 205 and the current hole 206.
For example, a top channel layer 207b may be formed on the current blocking layer 203 and the back barrier layer 204 by a metal organic chemical vapor deposition process (MOCVD) or Hydride Vapor Phase Epitaxy (HVPE).
As shown in fig. 13, step 6) is then performed to form a top barrier layer 208 on the top channel layer 207b, the top barrier layer 208 forming a two-dimensional electron gas channel with the top channel layer 207b.
For example, the top barrier layer 208 may be formed on the top channel layer 207b by a metal organic chemical vapor deposition process (MOCVD) or Hydride Vapor Phase Epitaxy (HVPE).
As shown in fig. 14, step 7) is then performed, forming a gate 210 and a source 211 on the top barrier layer 208, wherein the gate 210 is disposed on the top barrier layer 208 and is correspondingly disposed above the current hole 206, the aperture of the through hole 205 is smaller than or equal to the radial dimension of the gate 210, and the source 211 is disposed on the periphery of the gate 210 structure; finally, step 8) is performed to thin the substrate, expose the contact layer 201, and form a drain 209 on the bottom surface of the contact layer 201 or thin the substrate, and form a drain 209 on the bottom surface of the remaining portion of the substrate.
As described above, the current aperture vertical electron transistor and the method for manufacturing the same of the present invention have the following advantageous effects:
the invention provides a current aperture vertical electron transistor with a back barrier layer and a preparation method thereof, wherein the current aperture vertical electron transistor has better electron limiting effect, can effectively prevent electrons from drifting in a channel layer outside two-dimensional electron gas, reduce leakage current of the transistor, and improve the switching speed of the transistor, so that a grid electrode can more effectively control the switching of the transistor.
Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The above embodiments are merely illustrative of the principles of the present invention and its effectiveness, and are not intended to limit the invention. Modifications and variations may be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the invention. Accordingly, it is intended that all equivalent modifications and variations of the invention be covered by the claims, which are within the ordinary skill of the art, be within the spirit and scope of the present disclosure.
Claims (12)
1. A current aperture vertical electron transistor, the current aperture vertical electron transistor comprising:
a substrate;
a contact layer;
a drift layer disposed on the contact layer;
the current blocking layer is arranged on the drift layer, and is internally provided with a current hole for limiting a current path;
a back barrier layer disposed on the current blocking layer;
a channel layer arranged on the current blocking layer and the back barrier layer and filled in the current hole;
the top barrier layer is arranged on the channel layer, and the top barrier layer and the channel layer form a two-dimensional electron gas channel;
the grid electrode is arranged on the top barrier layer and correspondingly arranged above the current hole;
the drain electrode is arranged on the bottom surface of the substrate;
the source electrode is arranged on the top barrier layer and arranged on the periphery of the grid structure;
and the area of the back barrier layer corresponding to the grid electrode is provided with a through hole, and the aperture of the through hole is smaller than or equal to the radial size of the grid electrode and larger than or equal to the aperture of the current hole of the current barrier layer.
2. The current aperture vertical electron transistor of claim 1, wherein: the projection of the through hole of the back barrier layer on the grid electrode is completely covered by the grid electrode.
3. The current aperture vertical electron transistor of claim 1, wherein: the back barrier layer is in direct contact with the current blocking layer.
4. The current aperture vertical electron transistor of claim 1, wherein: the back barrier layer is embedded in the channel layer, the back barrier layer and the current blocking layer are separated by the channel layer with partial thickness, and the distance between the top surface of the back barrier layer and the top surface of the channel layer is 30-50 nanometers.
5. The current aperture vertical electron transistor of claim 1, wherein: the substrate is an n-type doped GaN substrate or a silicon carbide substrate, the contact layer is an n-type heavily doped GaN layer, and the carrier concentration is greater than 1e18/cm 3 The thickness of the contact layer ranges from 200 nanometers to 500 nanometers, the drift layer is an n-type lightly doped GaN layer, and the carrier concentration is 1e15/cm 3 ～1e17/cm 3 The thickness of the drift layer ranges from 1 micron to 100 microns, and the current blocking layer is a p-type GaN layer.
6. The current aperture vertical electron transistor of claim 1, wherein: the back barrier layer comprises one or more of AlGaN, inGaN, alInGaN, inAlN and AlN, and the thickness of the back barrier layer ranges from 15 nanometers to 30 nanometers.
7. The current aperture vertical electron transistor of claim 1, wherein: the channel layer comprises an intrinsic GaN layer, the thickness of the channel layer ranges from 100 nanometers to 200 nanometers, the top barrier layer comprises one of AlGaN, inGaN, alInGaN, inAlN and AlN, and the thickness of the top barrier layer ranges from 15 nanometers to 30 nanometers.
8. The current aperture vertical electron transistor of claim 1, wherein: the grid electrode comprises one of a trench grid, a p-type conductive grid, an insulated grid, a floating gate, an ion implantation grid and a Schottky grid.
9. A method of manufacturing a current aperture vertical electron transistor according to any one of claims 1 to 8, comprising the steps of:
providing a substrate;
forming a contact layer on the substrate;
forming a drift layer on the contact layer;
sequentially forming a current blocking layer and a back barrier layer on the drift layer, forming a through hole in the back barrier layer and forming a current hole in the current blocking layer, wherein the current hole is used for limiting a current path, and the through hole is larger than or equal to the aperture of the current hole of the current blocking layer;
forming a channel layer on the current blocking layer and the back barrier layer, wherein the channel layer is filled in the current hole and the through hole;
forming a top barrier layer on the channel layer, wherein the top barrier layer and the channel layer form a two-dimensional electron gas channel;
forming a grid electrode and a source electrode on the top barrier layer, wherein the grid electrode is arranged on the top barrier layer and correspondingly arranged above the current hole, the aperture of the through hole is smaller than or equal to the radial dimension of the grid electrode, and the source electrode is arranged on the periphery of the grid electrode structure;
and thinning the substrate and forming a drain electrode on the bottom surface of the substrate.
10. The method of manufacturing a current aperture vertical electron transistor according to claim 9, wherein:
forming the through hole and the current hole in the back barrier layer and the current barrier layer simultaneously through a photoetching process and an etching process, wherein the apertures of the through hole and the current hole are equal;
or forming a through hole in the back barrier layer through one photoetching process and etching process, and then forming a current hole in the current barrier layer through another photoetching process and etching process, wherein the aperture of the through hole is larger than that of the current hole.
11. A method of manufacturing a current aperture vertical electron transistor according to any one of claims 1 to 8, comprising the steps of:
providing a substrate;
forming a contact layer on the substrate;
forming a drift layer on the contact layer;
forming a current blocking layer on the drift layer, forming a bottom channel layer on the current blocking layer, forming a back barrier layer on the bottom channel layer, and forming a via in the back barrier layer and the bottom channel layer and a current aperture in the current blocking layer, the current aperture for defining a current path, the via being greater than or equal to an aperture of the current blocking layer;
forming a top channel layer on the back barrier layer, and the top channel layer filling in the via hole and the current hole;
forming a top barrier layer on the top channel layer, the top barrier layer and the top channel layer forming a two-dimensional electron gas channel;
forming a grid electrode and a source electrode on the top barrier layer, wherein the grid electrode is arranged on the top barrier layer and correspondingly arranged above the current hole, the aperture of the through hole is smaller than or equal to the radial dimension of the grid electrode, and the source electrode is arranged on the periphery of the grid electrode structure;
and thinning the substrate and forming a drain electrode on the bottom surface of the substrate.
12. The method of manufacturing a current aperture vertical electron transistor according to claim 11, wherein:
forming the through hole and the current hole in the back barrier layer, the bottom channel layer and the current blocking layer simultaneously through a photoetching process and an etching process, wherein the apertures of the through hole and the current hole are equal;
or forming through holes in the back barrier layer and the bottom channel layer through one photoetching process and etching process, and then forming current holes in the current blocking layer through another photoetching process and etching process, wherein the aperture of the through holes is larger than that of the current holes.
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