CN116403915A

CN116403915A - Substrate assembly and chip forming method

Info

Publication number: CN116403915A
Application number: CN202310666914.0A
Authority: CN
Inventors: 吕展航; 王意坚; 葛婷婷
Original assignee: Smarter Microelectronics Shanghai Co Ltd
Current assignee: Smarter Microelectronics Shanghai Co Ltd
Priority date: 2023-06-07
Filing date: 2023-06-07
Publication date: 2023-07-07

Abstract

The application relates to the technical field of semiconductors, and in particular relates to a method for forming a substrate assembly and a chip, wherein burrs can occur when a substrate is cut to obtain packaging particles, and the substrate is layered, and the method for forming the substrate assembly comprises the following steps: forming a metal layer, wherein the metal layer comprises a packaging region and a cutting region; thinning the cutting area of the metal layer; and forming a dielectric layer on the treated metal layer. Thus, by thinning the cutting area of the metal layer, not only the phenomenon of burrs and layering caused by cutting can be improved, but also the service life of the cutter can be prolonged.

Description

Substrate assembly and chip forming method

Technical Field

The present application relates to the field of semiconductor technology, and relates to, but is not limited to, a method of forming a substrate assembly and a chip.

Background

At present, as electronic products are continuously developed toward small size, multiple functions and high performance, integrated circuit chips are continuously pursuing miniaturization, high density, high power and high speed, and thus, the electromagnetic interference of electronic signals is also more and more serious.

Based on this, electromagnetic Shielding (Electromagnetic Interference Shielding) technology is widely used on chip packages. The electromagnetic shielding technology is to form a thin metal layer on the surface of the packaging body, shield the internal device from external interference through the metal layer, and simultaneously shield the device and the circuit from external interference.

However, in the related art, when a package dicing station cuts a package substrate to obtain individual package particles (units), burrs may occur after dicing and a copper layer may be pulled to cause delamination due to good ductility of copper.

Disclosure of Invention

In view of the foregoing, embodiments of the present application provide a substrate assembly and a method for forming a chip.

In a first aspect, embodiments of the present application provide a method for forming a substrate assembly, the method including:

forming a metal layer, wherein the metal layer comprises a packaging area and a cutting area;

thinning the cutting area of the metal layer;

and forming a dielectric layer on the treated metal layer.

In some embodiments, the method further comprises:

and forming a preset pattern in the packaging area of the metal layer.

In some embodiments, the step of forming the preset pattern in the packaging region of the metal layer and the step of thinning the cutting region of the metal layer are performed synchronously.

In some embodiments, after the preset pattern is formed in the packaging region of the metal layer, thinning is performed on the cutting region of the metal layer.

In some embodiments, the thinning the cutting area of the metal layer includes:

forming a film layer with a specific pattern on the surface of the metal layer;

and etching the exposed metal layer to realize the thinning treatment of the cutting area.

In some embodiments, the metal layer in the packaging region has a first thickness, and the thinned metal layer in the cutting region has a second thickness; the second thickness is 1/3-2/3 of the first thickness.

In some embodiments, the dielectric layer covers a cut region and a packaging region of the metal layer, and the dielectric layer fills a region where the cut region is thinned; the method further comprises the steps of:

and forming a conductive column penetrating through the dielectric layer and positioned on the surface of the metal layer in the packaging region.

In some embodiments, a second layer of the metal layer is formed over the dielectric layer and the conductive pillars.

In some embodiments, after forming the metal layer, the method further comprises:

and electroplating a metal material on the surface of the metal layer positioned in the packaging area.

In a second aspect, an embodiment of the present application provides a method for forming a chip, where the method includes:

forming a substrate assembly by the method described in the above embodiments;

stacking circuit modules to a surface of the package region on the substrate assembly;

forming an insulating layer wrapping the circuit module and covering the surface of the substrate assembly;

cutting the substrate assembly along the cutting area to form a single packaging structure containing a substrate; the single packaging structure exposes the metal layer positioned in the cutting area of the side wall of the substrate;

forming a shielding layer wrapping the insulating layer and the side wall of the substrate; wherein the shielding layer is connected with the exposed metal layer.

The substrate assembly and the method for forming the chip provided by the embodiment of the application, wherein the method for forming the substrate assembly comprises the following steps: forming a metal layer, wherein the metal layer comprises a packaging region and a cutting region; thinning the cutting area of the metal layer; and forming a dielectric layer on the treated metal layer. Therefore, the thickness of the metal layer of the formed substrate assembly in the packaging area is larger than that of the metal layer in the cutting area through thinning treatment of the cutting area of the metal layer, and when the substrate assembly is cut through the cutting area after the surface mounting, the copper cutting amount can be reduced, so that burrs caused by copper cutting and layering caused by copper pulling can be effectively improved. In addition, the copper cutting amount is reduced, so that the abrasion of cutting props can be reduced, and the service life of the cutting tool is prolonged.

Drawings

In the drawings (which are not necessarily drawn to scale), like numerals may describe similar components in different views. Like reference numerals having different letter suffixes may represent different instances of similar components. The drawings illustrate generally, by way of example and not by way of limitation, various embodiments discussed herein.

FIG. 1 is a side view of a package substrate after dicing;

fig. 2 is a schematic structural diagram of a substrate assembly according to an embodiment of the present disclosure;

fig. 3 is a flow chart of a method for forming a substrate according to an embodiment of the present disclosure;

FIG. 4 is a schematic diagram of a metal layer thinning process according to an embodiment of the present disclosure;

fig. 5 is a schematic structural diagram II of a metal layer thinning process according to an embodiment of the present application;

fig. 6 is a schematic structural diagram III of a metal layer thinning process according to an embodiment of the present application;

fig. 7 is a schematic structural diagram of a metal layer thinning process according to an embodiment of the present disclosure;

fig. 8 is a schematic structural diagram of a substrate forming process according to an embodiment of the present disclosure;

fig. 9 is a schematic diagram of a second structure of the substrate forming process according to the embodiment of the present application;

fig. 10 is a schematic structural diagram III of a substrate forming process according to an embodiment of the present application;

fig. 11 is a schematic structural diagram of a substrate forming process according to an embodiment of the present disclosure;

fig. 12 is a schematic diagram of a substrate forming process according to an embodiment of the present disclosure;

fig. 13 is a schematic structural diagram six of a substrate forming process according to an embodiment of the present disclosure;

fig. 14 is a schematic structural diagram seven of a substrate forming process according to an embodiment of the present disclosure;

fig. 15 is a schematic structural diagram eight of a substrate forming process according to an embodiment of the present disclosure;

fig. 16 is a schematic diagram of a substrate forming process according to an embodiment of the present disclosure;

fig. 17 is a schematic structural view of a substrate forming process according to an embodiment of the present disclosure;

fig. 18 is a schematic diagram eleven of a structure of a substrate forming process according to an embodiment of the present disclosure;

fig. 19 is a schematic diagram showing a substrate forming process according to an embodiment of the present disclosure;

fig. 20 is a schematic structural diagram of a substrate forming process according to an embodiment of the present disclosure;

fig. 21 is a schematic structural view fourteen of a substrate forming process according to an embodiment of the present disclosure;

fig. 22 is a schematic structural diagram fifteen of a substrate forming process according to an embodiment of the present disclosure;

fig. 23 is a schematic structural view sixteen of the substrate forming process provided in the embodiment of the present application;

fig. 24 is a schematic structural diagram seventeen of a substrate forming process according to an embodiment of the present disclosure;

fig. 25 is a schematic structural diagram eighteenth of a substrate forming process according to an embodiment of the present disclosure;

fig. 26 is a schematic structural diagram of a substrate provided in an embodiment of the present application;

fig. 27 is a schematic structural diagram of a chip according to an embodiment of the present application;

fig. 28 is a flow chart of a chip forming method according to an embodiment of the present application.

Detailed Description

Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the present application are shown in the drawings, it should be understood that the present application may be embodied in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present application. However, it will be apparent to one skilled in the art that the present application may be practiced without one or more of these details. In other instances, well-known features have not been described in detail so as not to obscure the application; that is, not all features of an actual implementation are described in detail herein, and well-known functions and constructions are not described in detail.

In the drawings, the size of layers, regions, elements and their relative sizes may be exaggerated for clarity. Like numbers refer to like elements throughout.

It will be understood that when an element or layer is referred to as being "on" … …, "" adjacent to "… …," "connected to" or "coupled to" another element or layer, it can be directly on, adjacent to, connected to or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on" … …, "" directly adjacent to "… …," "directly connected to" or "directly coupled to" another element or layer, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present application. When a second element, component, region, layer or section is discussed, it does not necessarily mean that the first element, component, region, layer or section is present in the present application.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.

The conformal shielding is realized by various methods such as electroplating, sputtering, spraying and the like. They are widely used as a new electromagnetic shielding technology for radio frequency, memory and other electronic packages.

In the related art electromagnetic shielding substrate design and manufacturing technology, when a single package particle is cut at a packaging (Saw) station, burrs occur after cutting and a copper layer is pulled to cause delamination problems (as shown by an arrow in fig. 1) due to good ductility of copper.

Based on this, the embodiment of the application provides a new substrate assembly, a forming method thereof, a substrate, a chip and a forming method thereof, because the thickness of the metal layer of the substrate assembly in the packaging area is larger than that in the cutting area, when the substrate assembly is cut through the cutting area after the surface mounting, the copper cutting amount can be reduced, and thus, the phenomenon of layering caused by burrs caused by copper cutting and copper pulling can be effectively improved. In addition, the copper cutting amount is reduced, so that the abrasion of cutting props can be reduced, and the service life of the cutting tool is prolonged.

Fig. 2 is a cross-sectional view of a substrate assembly according to an embodiment of the present application, as shown in fig. 2, the substrate assembly 10 includes a dielectric layer 50 and a metal layer 20 stacked together, the metal layer 20 has a package region P and a cutting region S extending outside the package region P, and a thickness of at least one metal layer 20 at the cutting region S is smaller than a thickness of at least one metal layer at the package region P.

In the embodiment of the present application, the substrate assembly 10 may be an inorganic package substrate and an organic package substrate; the inorganic package substrate may be, for example, a ceramic-based package substrate or a glass-based package substrate, and the organic package substrate may be, for example, a phenolic package substrate, a polyester package substrate or an epoxy package substrate. In other embodiments, the substrate assembly 10 may also be a Core (Core) package substrate and a Coreless (Coreless) package substrate.

In some embodiments, the circuit module is mounted on the surface of the substrate assembly 10, and the substrate assembly 10 and the circuit module may form a package structure. In general, a plurality of circuit modules are mounted on the surface of the substrate assembly 10, and a plurality of package structures can be obtained by cutting the substrate assembly 10 on which the circuit modules are mounted. Here, the area of the surface of the substrate assembly 10 to which the circuit module is mounted is referred to as a package area P, and the area around the package area P for dicing is referred to as a dicing area S.

In some embodiments, the substrate assembly 10 includes at least one metal layer 20, i.e., the substrate 10 has at least one metal pattern, and in many cases, the substrate assembly 10 includes a plurality of metal layers 20 stacked sequentially in a thickness direction of the substrate assembly 10, and the plurality of metal layers 20 are electrically connected through the conductive pillars 40 to form a metal interconnection layer.

With continued reference to fig. 2, the thickness of the metal layer 20 at the packaging region P is greater than the thickness of the metal layer 20 at the cutting region S, so that when the substrate assembly 10 is cut by the cutting region after the bonding, the amount of copper cutting can be reduced, and the phenomena of burrs caused by copper cutting and delamination caused by copper pulling can be effectively improved. In addition, the copper cutting amount is reduced, so that the abrasion of cutting props can be reduced, and the service life of the cutting tool is prolonged.

In some embodiments, referring to fig. 2, when the substrate assembly 10 includes a plurality of metal layers 20, for at least one metal layer 20 or each metal layer 20 of the plurality of metal layers 20, a portion located at the package region P has a first thickness h1; the portion located in the cutting zone S has a second thickness h2; the second thickness h2 is 1/3 to 2/3 of the first thickness h1, for example, 1/2, i.e. the second thickness h2 may be half of the first thickness h1. It should be noted that, when the metal layer 20 is a plurality of layers, the thicknesses of the portions of the metal layer 20 located in the cutting region S may also be different, for example, one of the layers has a thickness h2, and the other layer has a thickness other than h2.

In the embodiment of the present application, the dielectric layer 50 may be fiberglass cloth or other suitable insulating material impregnated with resin.

In some embodiments, the dielectric layer 50 fills the gaps between the multiple metal layers 20, and the thickness of at least one dielectric layer 50 at the cut region S of the metal layer 20 is greater than the thickness thereof at the package region P; the gaps include gaps between the dicing regions S and gaps between the package regions P. With continued reference to fig. 2, the thickness h5 of the dielectric layer 50 in the package region P is 1/3 to 2/3, for example 1/2, of the thickness h6 of the dielectric layer in the dicing region S.

In some embodiments, referring to fig. 2, the substrate assembly 10 further includes a ground layer 10a; the ground layer 10a is connected to a partial region of the metal layer 20 located in the package region P.

In some embodiments, dielectric layer 50 is also located in the gaps between conductive pillars 40.

In some embodiments, the substrate is obtained by removing the cutting region S of the substrate assembly 10, i.e., cutting along the dashed line of fig. 2.

An embodiment of the present application further provides a method for forming a substrate assembly in the foregoing embodiment, and fig. 3 is a schematic flow chart of the method for forming a substrate assembly provided in the embodiment of the present application, as shown in fig. 3, where the method for forming a substrate assembly includes the following steps:

in step S601, a metal layer is formed, where the metal layer includes a package region and a cutting region.

In some embodiments, the metal layer may be formed by electroplating a metal material, such as copper. In other embodiments, the metal layer may also be formed by electroplating any other suitable conductive metal material, such as aluminum, gold, tin, etc.

Step S602, thinning the cut region of the metal layer.

In some embodiments, step S602 may also be replaced with: and electroplating the packaging area of the metal layer.

It should be noted that, the purpose of thinning the cutting area of the metal layer or electroplating the packaging area of the metal layer is as follows: the thickness of the metal layer of the packaging area is larger than that of the metal layer of the cutting area, so that when the substrate is cut through the cutting area after the chip is attached, the copper cutting amount can be reduced, and the phenomenon that burrs brought by copper cutting and copper pulling cause layering is effectively improved.

In some embodiments, step S602 may also be replaced with: electroplating treatment is carried out on the packaging area of the metal layer, and thinning treatment is carried out on the cutting area of the metal layer. In this way, it is further ensured that the thickness of the metal layer of the encapsulation area is greater than the thickness of the metal layer of the dicing area.

Step S603, forming a dielectric layer on the processed metal layer.

In this embodiment, any suitable deposition process may be used to deposit the dielectric material to form the dielectric layer. For example, a chemical vapor deposition process (Chemical Vapor Deposition, CVD), a physical vapor deposition (Physical Vapor Deposition, PVD) process, an atomic layer deposition (Atomic Layer Deposition, ALD) process, a spin-on process, a coating process, or a furnace tube process.

In some embodiments, the method of forming a substrate assembly further includes forming a ground layer on a back side of the substrate assembly; the ground layer is connected with at least a partial area of the metal layer in the cutting area.

It should be noted that, in the embodiment of the present application, the metal layers may be multiple layers, and after each metal layer is formed, the cutting area of the metal layer may be thinned, or the cutting area of at least one metal layer in the multiple layers may be thinned.

In some embodiments, the method of forming a substrate assembly further comprises: and forming a preset pattern in the packaging area of the metal layer.

It should be noted that the preset pattern may be formed by forming a film layer (for example, a hard mask layer) with a preset pattern on the surface of the packaging region of the metal layer, and performing a dry etching treatment on the metal layer.

In some embodiments, since the thinning process and the process of forming the preset pattern are etching processes, the step of forming the preset pattern in the package region of the metal layer and the step of thinning the cut region of the metal layer may be performed simultaneously.

In other embodiments, the thinning process may be performed on the cut region of the metal layer after the predetermined pattern is formed on the package region of the metal layer. Or before the packaging area of the metal layer forms the preset pattern, thinning the cutting area.

In some embodiments, step S602 may include the steps of: forming a film layer with a preset pattern on the surface of the metal layer; and etching the exposed metal layer to realize thinning treatment of the cutting area.

In implementation, a specific etching solution can be adopted to etch the exposed metal layer under specific process conditions so as to realize thinning treatment of the cutting area. Here, the specific etching solution may be an acidic copper chloride solution, wherein the concentration of hydrogen chloride in the etching solution may be 3 to 5 mol per liter (mol/L), and the concentration of copper ions may be 130 to 170 grams per liter (g/L).

In some embodiments, the substrate assembly is typically transported between rollers, the upper surface of the substrate assembly is sprayed with an etching solution, and the etching process (i.e., the thinning process) of the metal layer is controlled by controlling the transport speed of the rollers and the temperature of the etching solution. In this embodiment, for example, the conveying speed of the roller may be controlled to be 2-5 meters per minute (m/min), and the temperature of the etching solution may be controlled to be 50±2 ℃.

Fig. 4 to 7 are schematic structural diagrams illustrating a process of thinning a cutting region of a metal layer according to an embodiment of the present application, and the process of thinning the cutting region of the metal layer is described below with reference to fig. 4 to 7.

In the process of forming the metal layer, a dry film is generally required to form a metal pattern, as shown in fig. 4, the metal layer 20 and the developed film layer 30 are located on the surface of the carrier 100, the carrier 100 includes a package region P and a cutting region S surrounding the package region P, and the metal layer 20 has a thickness h1. When the thinning process is performed, first, forming a film layer 30 with a specific pattern H as shown in fig. 5 on the surfaces of the metal layer 20 and the film layer 30, wherein the specific pattern H exposes the metal layer 20 of the cutting area S; next, the exposed metal layer 20 is etched by using an acidic copper chloride solution under the process conditions that the transmission speed of the roller is 3m/min and the temperature of the etching solution is 50 ℃, so as to thin the metal layer 20 located in the cutting area S, thereby forming a metal layer 20 with a second thickness h2 as shown in fig. 6.

In some embodiments, after the thinning process, the method further comprises: measuring a second thickness h2 of the thinned metal layer 20; judging whether the second thickness h2 meets the preset thickness requirement, wherein the preset thickness requirement is that the second thickness is 1/3-2/3 of the first thickness.

The second thickness h2 of the thinned metal layer 20 may be measured by a copper thickness measuring instrument. When the measured second thickness h2 is 1/3-2/3 of the first thickness h1, the second thickness h2 is considered to meet the thickness requirement, and at this time, the thinning treatment process is ended. When the second thickness h2 is measured to be not 1/3-2/3 of the first thickness h1, judging whether the second thickness h2 is larger than 2/3 of the first thickness h1 or smaller than 1/3 of the first thickness again. When the second thickness h2 is greater than 2/3 of the first thickness, the metal layer 20 located in the cutting area S needs to be continuously thinned until the second thickness h2 meets the thickness requirement; when the second thickness h2 is less than 1/3 of the first thickness h1, it is necessary to plate a metal material on the metal layer 20 located at the cutting area S until the second thickness h2 meets the thickness requirement.

In some embodiments, when the second thickness h2 meets the thickness requirement, the method further comprises: cleaning the current substrate assembly to remove residual etching solution on the surface of the metal layer 20; after cleaning, the substrate assembly is dried and the subsequent substrate assembly production process is continued, e.g., removing film layer 30; in the package region P, conductive pillars 40 (as shown in fig. 7) penetrating the dielectric layer 50 and located on the surface of the metal layer 20 are formed; a dielectric layer 50 as shown in fig. 7 is formed on the surface of the thinned metal layer 20.

In this embodiment of the present application, any suitable cleaning solution may be used to clean the thinned metal layer, for example, water.

In some embodiments, the dielectric layer 50 covers the cutting region S and the packaging region P of the metal layer 20, and the dielectric layer 50 fills the thinned region of the cutting region S; the method for forming the substrate assembly further comprises the following steps: a second metal layer is formed over dielectric layer 50 and conductive post 40.

In other embodiments, after forming the second metal layer, the method of forming a substrate assembly further includes: and forming a third metal layer and a fourth metal layer. And so on until a complete interconnect via is formed.

In the embodiment of the present application, since the electrical transmission path of the coreless substrate is reduced, the inductance of the power supply system loop can be reduced, the transmission characteristic, especially the frequency characteristic, and the higher integration level are widely applied to the radio frequency product, and therefore, the embodiment of the present application uses the coreless substrate as an example, and uses the substrate assembly including four metal layers (for example, the first metal layer M1, the second metal layer M2, the third metal layer M3, and the fourth metal layer M4) as an example, and describes the specific formation process of the substrate assembly in combination with fig. 8 to 27.

In the first step, a carrier 100 as shown in fig. 8 is provided.

In the embodiment of the present application, the carrier 100 may be a double-layer copper foil (Double thin copper foil, DTF) carrier. The upper and lower surfaces of the double-layered copper foil carrier are formed with a first layer of copper foil 101 and a second layer of copper foil 102, which are simultaneously manufactured up and down, and then the substrate assembly is formed by dividing the carrier 100. The first copper foil 101 is removed along with the carrier 100, and the second copper foil 102 is electroplated and thickened to a required thickness as a metal layer. The copper of the first layer copper foil 101 and the copper of the second layer copper foil 102 are specially treated, so that the metal layer and the carrier plate 100 can be separated, i.e., the first layer copper foil 101 and the second layer copper foil 102 can be in a bonding state or a separated state.

The carrier 100 includes a package region P and a dicing region S surrounding the package region P.

In the second step, a first film 31 as shown in fig. 9 is formed on the upper and lower surfaces of the carrier 100.

In this embodiment, the first film 31 covered on the upper surface and the lower surface of the carrier plate 100 is a dry film, and the dry film is a photosensitive polymer material, and can generate a polymerization reaction after being irradiated by ultraviolet rays to form a stable substance attached on the surface of the carrier plate 100, thereby achieving the functions of blocking electroplating and etching.

And thirdly, exposing, developing and electroplating metal.

The first film layer 31 is exposed and developed to expose a portion of the surface of the second-layer copper foil 102, and a metal material, such as copper, is plated on the exposed surface of the second-layer copper foil 102 to form a third metal layer 21 as shown in fig. 10. Wherein the third metal layer 21 has a first thickness h1. In other embodiments, any other suitable conductive material such as aluminum, gold, tin, etc. may be electroplated on the surface of the second layer of copper foil 102.

Fourth, the third metal layer 21 located in the cutting region S is thinned.

The thinning process of the third metal layer 21 located in the cutting region S is the same as that shown in fig. 4 to 7 in the above embodiment, and will not be described again.

In some embodiments, after the thinning process is performed on the third metal layer 21 located at the cutting region S, the third metal layer 21 having the second thickness h2 as shown in fig. 11 is formed. After the thinning process, the method further comprises: judging whether the second thickness h2 of the third metal layer 21 in the cutting area S meets the preset thickness requirement, namely judging whether the second thickness h2 of the third metal layer 21 in the cutting area S is 1/3-2/3 of the first thickness h1 of the third metal layer 21 in the packaging area P. When the second thickness h2 is 1/3-2/3 of the first thickness h1, the second thickness h2 is considered to meet the thickness requirement, and at this time, the thinning process is ended. When the second thickness h2 is not 1/3-2/3 of the first thickness h1, judging whether the second thickness h2 is larger than 2/3 of the first thickness h1 or smaller than 1/3 of the first thickness again. When the second thickness h2 is greater than 2/3 of the first thickness, the third metal layer 21 located in the cutting area S needs to be further thinned until the second thickness h2 meets the thickness requirement; when the second thickness h2 is smaller than 1/3 of the first thickness h1, it is necessary to plate a metal material on the third metal layer 21 located at the cutting region S until the second thickness h2 satisfies the thickness requirement.

In some embodiments, the washing and drying steps are performed when the second thickness h2 of the third metal layer 21 in the cutting region S meets the thickness requirement.

Fifth, forming a second film layer 32 as shown in fig. 12 on the surface of the third metal layer 21 after the thinning treatment; the second film 32 exposes a portion of the third metal layer 21 located in the package region P. Wherein the second film layer 32 is a dry film.

In the sixth step, first conductive pillars 41 as shown in fig. 12 are formed on the exposed surface of the third metal layer 21.

In the embodiment of the present application, the first conductive pillar 41 may be formed by any suitable deposition process (e.g., chemical vapor deposition, physical vapor deposition, atomic layer deposition, etc.) or electroplating process. The material of the first conductive post 41 may be any material with good conductivity, such as copper or titanium.

Seventh, as shown in fig. 13, the second film 32 and the first film 31 are removed.

Here, the second film layer 32 and the first film layer 31 may be washed away with a film washing liquid. The membrane wash may be, for example, a sodium carbonate solution or a sodium bicarbonate solution.

Eighth, the dielectric layer 50 as shown in fig. 14 is filled between the third metal layers 21 located in the package region P, the surface of the third metal layers 21 located in the cutting region S, and the first conductive pillars 41 located in the package region P.

In this embodiment, the dielectric layer 50 may be glass fiber cloth impregnated with resin, and the dielectric layer 50 is flush with the top surface of the first conductive pillar 41.

In the ninth step, a seed layer 60 as shown in fig. 15 is formed on the dielectric layer 50 and the surface of the first conductive pillar 41.

In this embodiment, the seed layer 60 may be formed by sputtering, and the material of the seed layer 60 may be metallic copper or metallic titanium. The thickness of the seed layer 60 may be 3 micrometers (μm).

A tenth step of forming a third film layer 33 as shown in fig. 16 on the surface of the seed layer 60; the third film layer 33 exposes the top surfaces of the first conductive pillars 41 and the top surfaces of the portion of the dielectric layer 50 that interfaces with the first conductive pillars 41. Wherein the third film layer 33 is a dry film.

Eleventh, copper or other metal material is electroplated on the surfaces of the exposed first conductive pillars 41 and the exposed dielectric layer 50 to form the second metal layer 22 as shown in fig. 16. Wherein the second metal layer 22 has a first thickness h1.

Twelfth, the second metal layer 22 located in the cutting region S is thinned to form a metal layer having a second thickness h2 as shown in fig. 17.

The thinning process of the second metal layer 22 located in the cutting region S is the same as that shown in fig. 4 to 7 in the above embodiment, and will not be described here.

In the thirteenth step, the protective film 70 shown in fig. 18 is formed on the surface of the second metal layer 22 after the thinning process. The protective film 70 may be a dry film or a hard mask for protecting the formed second metal layer 22 in a subsequent patterning step.

In the fourteenth step, the carrier 100 is subjected to a dividing process.

With continued reference to fig. 18, the carrier 100 is divided into two parts, i.e., an upper part and a lower part, from between the first layer of copper foil 101 and the second layer of copper foil 102 in the direction of the arrow in the figure, wherein the first layer of copper foil 101 is removed along with the carrier 100, and the second layer of copper foil 102 and the third metal layer 21, the second metal layer 22, and the first conductive post 41 together form a part of the substrate 10.

As can be seen in fig. 18, one carrier plate 100 may form two substrates.

In the fifteenth step, the protective film 70 is removed.

In the embodiment of the present application, the protective film 70 may be washed away by using a cleaning solution, or the protective film 70 may be etched away by using a dry etching technique.

Sixteenth, forming a fourth film layer 34 as shown in fig. 19 on the surfaces of the thinned second metal layer 22 and the second copper foil 102; the fourth film layer 34 exposes a portion of the surface of the second metal layer 22 and a portion of the surface of the second layer copper foil 102. Wherein the fourth film layer 34 is a dry film.

In the seventeenth step, second conductive pillars 42 and third conductive pillars 43 as shown in fig. 19 are formed on the surfaces of the exposed second metal layer 22 and the exposed second layer copper foil 102, respectively.

The second conductive pillar 42 and the third conductive pillar 43 are formed in the same manner as the first conductive pillar 41, and will not be described again here.

Eighteenth, as shown in fig. 20, the fourth film layer 34 and the third film layer 33 are removed, and the seed layer 60 is etched to expose the surface of the dielectric layer 50.

In the embodiment of the present application, the fourth film layer 34 and the third film layer 33 may be washed away by using a film washing liquid. The process of etching the seed layer 60 may be a wet etching process.

Nineteenth, dielectric layer 50 is formed between second conductive pillars 42 and third conductive pillars 43 filled with a dielectric material, as shown in fig. 21.

A twentieth step of sequentially forming a fifth film layer 35 as shown in fig. 22 on the surfaces of the dielectric layer 50, the second conductive pillars 42, and the third conductive pillars 43; the fifth film 35 exposes at least the second conductive pillars 42 and the third conductive pillars 43. The fifth film layer 35 is a dry film.

In a twenty first step, a first metal layer 23 and a fourth metal layer 24 as shown in fig. 23 are formed on the exposed surfaces of the second conductive pillars 42 and the third conductive pillars 43, respectively. Wherein the first metal layer 23 is electrically connected to the second conductive post 42, and the fourth metal layer 24 is connected to the third conductive post 43.

In the embodiment of the present application, the first metal layer 23 and the fourth metal layer 24 each have a first thickness h1. The first metal layer 23 and the fourth metal layer 24 are formed in the same manner as the third metal layer 21, and will not be described again here.

Twenty-second, thinning is performed on the first metal layer 23 and the fourth metal layer 24 located in the cutting region S.

The thinning process of the first metal layer 23 and the fourth metal layer 24 located in the cutting region S is the same as that of the above embodiment, and is not described here.

In a twenty-third step, as shown in fig. 24, the fifth film layer 35 is removed, exposing the surface of the dielectric layer 50.

In the twenty fourth step, solder resist ink 51 shown in fig. 25 is formed on the surface of the dielectric layer 50.

In the twenty-fifth step, the first metal layer 23 and the fourth metal layer 24 are subjected to surface treatment.

In the embodiment of the present application, the surface treatment of the first metal layer 23 and the fourth metal layer 24 may be nickel-palladium immersion gold (Electroless Nickel Electroless Palladium Immersion Gold, ENEPIG) treatment. In other embodiments, the first metal layer 23 and the fourth metal layer 24 may be further subjected to an organic solder mask (Organic Solderability Preservatives, OSP) process to form an organic solder mask 52 as shown in fig. 25 on the surfaces of the first metal layer 23 and the fourth metal layer 24.

The mainstream design of EMI Shielding is to completely spread copper to a cutting area, so that good Shielding integrity is ensured. The utility model provides a do not change and spread copper shape design, reduce and cut copper volume and reach the scheme that improves the layering problem of cutting burr.

Compared with the related art, the embodiment of the application can effectively improve burrs and layering caused by cutting copper at a part to be cut and can prolong the service life of a cutter by reducing the metal thickness of a cutting area.

In addition, in the embodiment of the application, the copper cutting amount can be reduced by half on the basis of the original EMI Shielding design, whether the thinning treatment or the zigzag design or other shape designs.

In some embodiments, processing each metal layer may further include: electroplating a metal material on the surface of the metal layer in the packaging area after forming each metal layer to form a metal layer with a third thickness; wherein the third thickness is greater than the first thickness.

In this embodiment, a thinner metal layer is formed first, and then a metal material is electroplated on the surface of the metal layer in the packaging region, so that the thickness of the metal layer in the packaging region is greater than that in the cutting region.

In another embodiment of the present application, reference is made to fig. 26, which shows a cross-sectional view of a substrate provided by an embodiment of the present application, which is formed by cutting the cut regions of the substrate assembly 10 in any of the embodiments described above. As shown in fig. 26, at least one metal layer 20 of the substrate 200 extends to the side of the substrate assembly and is exposed, and the thickness of the exposed metal layer 20 at the cutting area S is smaller than the thickness of the exposed metal layer at the packaging area P. For example, the thickness h3 of the first metal layer 20 at the cutting area S is smaller than the thickness h4 of the first metal layer 20 at the packaging area P, and the thickness h2 of the second metal layer 20 at the cutting area S is smaller than the thickness h1 of the second metal layer 20 at the packaging area P.

It should be noted that, the structure of the substrate 200 in the embodiment of the present application is similar to that of the substrate assembly 10 in the above embodiment, and the technical features that are not fully disclosed in the embodiment of the present application are understood by referring to the above embodiment, and are not repeated here. The difference from the substrate obtained in the embodiment of fig. 2 is that the thickness of the metal layer in the edge region of the substrate in this embodiment is the thickness after thinning, whereas the thickness of the base layer in the edge region of the substrate obtained in the embodiment of fig. 2 is not thinned.

In another embodiment of the present application, reference is made to fig. 27, which shows a cross-sectional view of a chip provided by an embodiment of the present application. As shown in fig. 27, the chip 300 includes: the substrate, the circuit module 301, the insulating layer 302, and the shielding layer 303 in the above embodiments. The circuit module 301 is disposed on the substrate; an insulating layer 302 wrapping the circuit module 301 and covering the surface of the substrate; the shielding layer 303 wraps the insulating layer 302 and the sidewall of the substrate, and is connected to the exposed portion of the metal layer 20.

Here, the circuit module 301 may be a circuit integrated with any one or more functions. The insulating layer 302 may perform a good protection function and a part of electromagnetic shielding function, so as to improve the overall performance of the chip 300. The material of the insulating layer 302 may include a polyimide layer, a silicone layer, an epoxy layer, or a curable resin-based material layer. The shielding layer 303 is composed of any suitable metallic material.

In some embodiments, the substrate includes a dielectric layer 50 and a metal layer 20 stacked together, the metal layer 20 has a packaging region P and a cutting region S extending outside the packaging region P, and a thickness of at least one metal layer 20 at the cutting region S is smaller than a thickness of at least one metal layer at the packaging region P.

In some embodiments, with continued reference to fig. 27, the substrate further includes conductive posts 40, and the plurality of metal layers 20 are electrically connected by the conductive posts 40.

In some embodiments, referring to fig. 27, the dielectric layer 50 fills the gaps between the metal layers 20, and at least one dielectric layer 50 is thicker in the cut region S of the metal layer 20 than in the package region P.

In some embodiments, with continued reference to fig. 27, dielectric layer 50 is also located in the gaps between conductive pillars 40.

In some embodiments, referring to fig. 27, the substrate further includes a ground layer 10a; the ground layer 10a is connected to at least a portion of the metal layer 20 located in the cutting area S.

In some embodiments, chip 300 may be an integrated circuit chip, such as a NAND Flash Memory chip, a Nor Flash chip, a dynamic random access Memory (Dynamic Random Access Memory, DRAM) chip, a static random access Memory (Static Random Access Memory, SRAM) chip, a Phase-Change Memory (PCM) chip, a ferroelectric Memory chip, a magneto-resistive Memory chip, or a resistive Memory chip.

According to the chip provided by the embodiment of the application, the thickness of the packaging area of the metal layer of the substrate is larger than that of the cutting area, so that the copper cutting amount can be reduced when the cutting area is used for cutting, and the phenomenon that burrs brought by cutting copper and pulling copper cause layering can be effectively improved. In addition, the copper cutting amount is reduced, so that the abrasion of cutting props can be reduced, and the service life of the cutting tool is prolonged.

In addition, an embodiment of the present application further provides a method for forming the above-mentioned chip, and fig. 28 is a schematic flow chart of a method for forming a semiconductor package structure according to an embodiment of the present application, as shown in fig. 28, the method for forming a semiconductor package structure includes the following steps:

step S3301, forming a substrate assembly;

the substrate assembly is formed by the method for forming the substrate assembly in the above embodiment, and will not be described here again.

Step S3302, disposing a circuit module on a surface of a packaging region on the substrate assembly;

step S3303, forming an insulating layer that wraps the circuit module and covers the surface of the substrate assembly;

here, the insulating layer may be any suitable insulating material such as silicon oxide, silicon nitride, silicon oxynitride, etc., and is used to isolate the surface of the circuit module and the substrate assembly from the external environment, so as to prevent the circuit module and the substrate assembly from being affected by external moisture.

Step S3304, cutting the substrate assembly along the cutting area to form a single package structure including the substrate; the single packaging structure exposes the metal layer positioned in the cutting area of the side wall of the substrate;

step S3305, forming a shielding layer wrapping the insulating layer and the side wall of the substrate; wherein the shielding layer is connected with the exposed metal layer.

In this embodiment, a thin metal layer may be formed on the surface of the insulating layer and the sidewall of the substrate by electroplating, sputtering, spraying, or the like, so as to form the shielding layer. The shielding layer can be used for shielding the circuit module inside the single packaging structure from external interference and also shielding the circuit module inside the single packaging structure from external interference.

In some embodiments, the process of stacking the circuit module to the surface of the package region may include the following steps:

1. visual inspection is carried out, and a chip Die with defects in appearance is removed;

2. adopting surface mounting technology (Surface Mounted Technology, SMT) to carry out the mounting;

3. flip chip Attach (flip chip Attach); specifically, the semiconductor chip is dipped with soldering flux and is flip-chip mounted;

4. reflow (Reflow) to melt the solder balls of the flip chip and firmly bond the solder balls with the substrate pads;

5. defluxing (Delete Flux) because Flux residue can affect subsequent bondability with the molding compound;

6. optically automated inspection (Automatically Optical Inspection, AOI);

7. plasma (Plasma) cleaning;

8. prebaking (Prebake); heating the pre-baked substrate to enable the substrate to be combined with the heated plastic packaging material better;

9. plastic packaging (Molding);

10. curing (Cure);

11. printing (Marking); printing a production lot, name, date or logo (logo), etc.;

12. reflow (Reflow) to remove the silver paste of the components cured after SMT;

13. dicing (Saw), dicing the substrate to obtain individual encapsulated particles;

14. designing an electromagnetic shielding layer, for example, forming a thin metal layer on the surface of the package by electroplating, sputtering, spraying and the like;

15. a quality control department (Quality Control Gate) performs shipment inspection;

16. final visual inspection (Final Visual Inspection, FVI);

17. test (Test).

The method for forming the chip provided in the embodiment of the present application is similar to the structure of the chip in the above embodiment, and for technical features that are not fully disclosed in the embodiment of the present application, please understand with reference to the above embodiment, and will not be repeated here.

According to the chip forming method, the thickness of the packaging area of the metal layer of the formed substrate assembly is larger than that of the cutting area, so that when the substrate assembly is cut through the cutting area, the copper cutting amount can be reduced, and burrs caused by copper cutting and layering caused by copper pulling can be effectively improved. In addition, the copper cutting amount is reduced, so that the abrasion of cutting props can be reduced, and the service life of the cutting tool is prolonged.

In several embodiments provided herein, it should be understood that the disclosed structures and methods may be implemented in a non-targeted manner. The above-described structural embodiments are merely illustrative, and for example, the division of units is merely a logic function division, and there may be other division manners in actual implementation, such as: multiple units or components may be combined or may be integrated into another system, or some features may be omitted, or not performed. In addition, the components shown or discussed are coupled to each other or directly. The features disclosed in the embodiments of the method or the apparatus provided in this application may be combined arbitrarily without any conflict to obtain new embodiments of the method or the structure.

The foregoing is merely some embodiments of the present application, but the protection scope of the present application is not limited thereto, and any person skilled in the art can easily think about changes or substitutions within the technical scope of the present application, and the changes or substitutions should be covered in the protection scope of the present application.

Claims

1. A method of forming a substrate assembly, the method comprising:

thinning the cutting area of the metal layer;

and forming a dielectric layer on the treated metal layer.

2. The method according to claim 1, wherein the method further comprises:

and forming a preset pattern in the packaging area of the metal layer.

3. The method of claim 2, wherein the step of forming the predetermined pattern in the encapsulation region of the metal layer is performed simultaneously with the step of thinning the cut region of the metal layer.

4. The method of claim 2, wherein the thinning process is performed on the cut region of the metal layer after the predetermined pattern is formed on the package region of the metal layer.

5. The method according to any one of claims 1 to 4, wherein the thinning of the cut region of the metal layer comprises:

forming a film layer with a specific pattern on the surface of the metal layer;

6. The method of claim 5, wherein the metal layer in the encapsulation area has a first thickness and the thinned metal layer in the dicing area has a second thickness; the second thickness is 1/3-2/3 of the first thickness.

7. The method of claim 5, wherein the dielectric layer covers cut and package regions of the metal layer and fills the thinned regions of the cut regions; the method further comprises the steps of:

8. The method of claim 7, wherein the method further comprises:

and forming a second layer of the metal layer on the dielectric layer and the conductive column.

9. The method of claim 1, wherein after forming the metal layer, the method further comprises:

10. A method of forming a chip, the method comprising:

forming a substrate assembly by the method of any one of the preceding claims 1 to 9;