CN116402009A - Layout wiring method, device and equipment for optoelectronic chip and storage medium - Google Patents
Layout wiring method, device and equipment for optoelectronic chip and storage medium Download PDFInfo
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- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
- G06F30/394—Routing
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- G06F30/39—Circuit design at the physical level
- G06F30/394—Routing
- G06F30/3947—Routing global
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Abstract
The invention discloses a method, a device, equipment and a storage medium for wiring an optoelectronic chip layout, which relate to the technical field of automatic design wiring of the optoelectronic chip layout, and the method comprises the following steps: mapping the layout of the optoelectronic chip to a two-dimensional coordinate system, mapping the PCell port of the parameterized unit to point coordinates, and mapping the waveguide to be wired to a link segment; initializing an optoelectronic chip layout and links, and generating a shortest link path between each group of PCell ports; adding cross waveguide device symbols and/or control points in links to increase the number of bends and/or link line segments, so that the number, the number of bends and the length of the cross waveguide devices of all links are consistent; the completed link path plan is mapped to waveguide traces and the cross waveguide device symbols are mapped to cross waveguide devices. The invention can make the number, length and bending number of the generated multiple waveguide crossing waveguide devices equal, and ensure the small occupied area of the waveguide and the shortest total length of the waveguide.
Description
Technical Field
The invention relates to the technical field of automatic design wiring of optoelectronic chips, in particular to a layout wiring method, device and equipment of an optoelectronic chip and a storage medium.
Background
The conventional optoelectronic chip layout automatic design tool automatically generates waveguide routing according to a Manhattan algorithm for port links between parameterized units (Parameterized cell, PCell) or between system links, namely, a shortest path which is horizontal, flat and vertical is planned.
Many commercial CAD suppliers now offer automated WG (waveguide) routing tools that focus on routing connecting one port to another, fixing waveguide length and number of bends, while bypassing obstacles (e.g., other parameterized cells or chip structures). However, for phase sensitive link structures, such as Integrated Coherent Receivers (ICR), there is a need to precisely control the length of the connecting waveguides, the number of curved waveguides in different links, and to be able to automatically add crossing waveguides (Waveguide Crossing) or other units when crossing occurs, none of the existing methods can automatically add units at the path crossing.
The tool aims at the problem that the automatic adding of the crossed waveguide units is realized while the equal length of the waveguides is realized, the automatic design is not realized, the manual design of the waveguide routing is still relied on, and the manual adding of the crossed waveguide units after the crossing is generated. The waveguide layout and wiring can be realized in a semi-manual and semi-automatic mode, the labor and time are consumed, errors are prone to occur, and the full waveguide length and the occupied area of the whole module are not necessarily optimal solutions when the equal-length waveguide is finally realized.
However, for WG layout and wiring design of a coherent optical chip layout, the problems of equal length and intersection of multiple waveguide wires, that is, equal waveguide lengths, equal number of curved waveguides (generally, consistent default curved waveguide radii), and consistent crossed waveguide units on each waveguide path are required to be considered, and at the same time, it is desirable that the waveguide lengths are smaller to reduce the loss of optical power (although the loss per unit length in silicon light is very small) and the influence on phase delay, so that the crossed waveguide units on each path are ensured to be consistent to reduce the influence on optical modes in the optical transmission process. The high refractive index and contrast of silicon impose stringent requirements on the dimensions of silicon photonic links, and nanoscale variations in waveguide core width or thickness can have a non-negligible impact on the performance of the photonic link.
Disclosure of Invention
Aiming at the defects existing in the prior art, the first aspect of the invention provides an optoelectronic chip layout wiring method which can lead the generated multiple waveguide crossing waveguide devices to be equal in number, length and bending number, and simultaneously ensure that the occupied area of the waveguide is smaller and the total length of the waveguide is shortest.
In order to achieve the above purpose, the invention adopts the following technical scheme:
an optoelectronic chip layout wiring method, comprising the following steps:
mapping the layout of the optoelectronic chip to a two-dimensional coordinate system, mapping the PCell port of the parameterized unit to point coordinates, and mapping the waveguide to be wired to a link segment;
initializing an optoelectronic chip layout and links, and generating a shortest link path between each group of PCell ports;
counting the number, the bending number and the length of the crossed waveguide devices of each link, and adding the number of the bent waveguide devices and/or the line segments of the links by adding symbols of the crossed waveguide devices and/or adding control points in the links so as to enable the number, the bending number and the length of the crossed waveguide devices of all the links to be consistent, thereby completing the planning of the link paths;
the completed link path plan is mapped to waveguide traces and the cross waveguide device symbols are mapped to cross waveguide devices.
In some embodiments, the counting the number, the number of bends and the length of the cross waveguide devices of each link, adding the cross waveguide device symbol and/or adding a control point to the link to add the number of bends and/or the link line segments, so that the number, the number of bends and the length of the cross waveguide devices of all links are consistent, and the link path planning is completed, including:
counting the number, bending number and length of the crossed waveguide devices of each link, and determining the number balance value, bending number balance value and link length balance value of the crossed waveguide devices of the links;
adding cross waveguide device symbols to enable the number of the cross waveguide devices of each link to reach the balance value of the number of the cross waveguide devices;
forming a U-shaped waveguide structure by adding control points on the links so as to change the bending quantity and length of the links simultaneously;
and/or adding control points to form S-shaped bends at the bending positions of the links so as to keep the length of the links unchanged but change the bending quantity of the links, and enabling the bending quantity and the length of all the links to reach a bending quantity balance value and a link length balance value.
In some embodiments, the link's cross waveguide device number balance value is the maximum cross waveguide device number value owned by a single link;
the bending quantity balance value of the link is the maximum bending quantity value which is owned by a single link plus 2;
the link length balance value is the length value of the longest link in all links.
In some embodiments, the optoelectronic chip layout and links are initialized according to a Manhattan algorithm and a Round algorithm, and Manhattan shortest link paths are generated between each group of PCell ports.
In some embodiments, the added control point is placed near the initialized link path.
The second aspect of the invention provides an optoelectronic chip layout wiring device, which can make the number, the length and the bending number of the generated multiple waveguide crossing waveguide devices equal, and simultaneously ensure that the occupied area of the waveguide is smaller and the total length of the waveguide is shortest.
In order to achieve the above purpose, the invention adopts the following technical scheme:
an optoelectronic chip layout wiring device, comprising:
the mapping module is used for mapping the layout of the optoelectronic chip to a two-dimensional coordinate system, mapping the PCell port of the parameterized unit to point coordinates and mapping the waveguide to be wired to a link line segment;
the initialization module is used for initializing the layout and the links of the optoelectronic chip and generating shortest link paths among all groups of PCell ports;
the balancing module is used for counting the number, the bending number and the length of the crossed waveguide devices of each link, and the number, the bending number and the length of the crossed waveguide devices of all links are consistent by adding the signs of the crossed waveguide devices and/or adding control points in the links to add the bending number and/or the link line segments so as to complete the link path planning;
the mapping module is further configured to map the completed link path plan to waveguide traces and cross waveguide device symbols to cross waveguide devices.
In some embodiments, the balancing module counts the number, the number of bends and the length of the cross waveguide devices of each link, and adds the number of bends and/or the line segments of the links by adding cross waveguide device symbols and/or adding control points to the links, so that the number, the number of bends and the length of the cross waveguide devices of all links are consistent, including:
counting the number, bending number and length of the crossed waveguide devices of each link, and determining the number balance value, bending number balance value and link length balance value of the crossed waveguide devices of the links;
adding cross waveguide device symbols to enable the number of the cross waveguide devices of each link to reach the balance value of the number of the cross waveguide devices;
forming a U-shaped waveguide structure by adding control points on the links so as to change the bending quantity and length of the links simultaneously;
and/or adding control points to form S-shaped bends at the bending positions of the links so as to keep the length of the links unchanged but change the bending quantity of the links, and enabling the bending quantity and the length of all the links to reach a bending quantity balance value and a link length balance value.
In some embodiments, the link's cross waveguide device number balance value is the maximum cross waveguide device number value owned by a single link;
the bending quantity balance value of the link is the maximum bending quantity value which is owned by a single link plus 2;
the link length balance value is the length value of the longest link in all links.
A third aspect of the present invention provides an apparatus comprising a processor, a memory, and a computer program stored on the memory and executable by the processor, wherein the computer program when executed by the processor implements the steps of any one of the above-described optoelectronic chip layout routing methods.
A fourth aspect of the present invention provides a computer readable storage medium having a computer program stored thereon, wherein the computer program, when executed by a processor, implements the steps of any one of the above-described optoelectronic chip layout routing methods.
Compared with the prior art, the invention has the advantages that:
the layout wiring method of the optoelectronic chip in the invention comprises the following steps: mapping the layout of the optoelectronic chip to a two-dimensional coordinate system, mapping the PCell port of the parameterized unit to point coordinates, and mapping the waveguide to be wired to a link segment; initializing an optoelectronic chip layout and links, and generating a shortest link path between each group of PCell ports; counting the number, the bending number and the length of the crossed waveguide devices of each link, and adding the number of the bent waveguide devices and/or the line segments of the links by adding symbols of the crossed waveguide devices and/or adding control points in the links so as to enable the number, the bending number and the length of the crossed waveguide devices of all the links to be consistent, thereby completing the planning of the link paths; the completed link path plan is mapped to waveguide traces and the cross waveguide device symbols are mapped to cross waveguide devices. Therefore, the length balance, the bending quantity balance and the cross waveguide device quantity balance of the routing of the plurality of waveguides are realized, and finally, the length error among each waveguide is smaller than an expected value, the quantity of the bent waveguides and the quantity of the cross waveguides are consistent. Meanwhile, the limit condition is met, the waveguide is allowed to be crossed in the wiring process, the layout utilization area is considered, and waste is avoided.
Drawings
FIG. 1 is a flow chart of an optoelectronic chip layout wiring method in an embodiment of the invention;
FIG. 2 is a schematic diagram of a balancing mode in an embodiment of the present invention;
FIG. 3 is a schematic diagram illustrating a link path crossing in an embodiment of the present invention;
fig. 4 is a schematic diagram illustrating another link path crossing in an embodiment of the present invention.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present application more clear, the technical solutions of the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is apparent that the described embodiments are some embodiments of the present application, but not all embodiments. All other embodiments, which can be made by one of ordinary skill in the art without undue burden from the present disclosure, are within the scope of the present application based on the embodiments herein.
Referring to fig. 1, an embodiment of the present invention provides a layout wiring method for an optoelectronic chip, which includes the following steps:
s1, mapping an optoelectronic chip layout to a two-dimensional coordinate system, mapping a parameterized unit PCell port to a point coordinate, and mapping a waveguide to be wired to a link line segment.
Aiming at the defect of the existing optoelectronic chip layout automatic design tool in the aspect of equal-length wiring of waveguides, the embodiment of the invention realizes an automatic wiring mathematical model, the model maps the optoelectronic chip layout to a two-dimensional coordinate system, maps PCell ports to point coordinates, and maps waveguides needing wiring to link line segments, wherein port information comprises angle information.
S2, initializing an optoelectronic chip layout and links, and generating a shortest link path between each group of PCell ports.
The embodiment of the invention provides an automatic waveguide layout wiring algorithm based on a Manhattan path planning algorithm and a Round algorithm. Under the condition of considering various limitations of waveguide wiring avoidance, the algorithm framework maps each component into a Cartesian coordinate system, realizes length balance of a plurality of waveguide routes, bending quantity balance and cross waveguide device quantity balance according to defined port link relation, limiting conditions, manhattan algorithm and Round algorithm, and finally realizes that the length error between each waveguide is smaller than 1nm, the number of the bent waveguides and the number of the cross waveguide devices are consistent. Meanwhile, the limit condition is met, the waveguide is allowed to be crossed in the wiring process, the layout utilization area is considered, and waste is avoided.
Specifically, in step S2, first, a link relation of ports is defined, a curved waveguide radius value r is set, and curves generated in all paths are uniform.
And initializing the layout and links of the optoelectronic chip according to a Manhattan algorithm and a Round algorithm, and generating Manhattan shortest link paths among each group of PCell ports.
Manhattan distance algorithm: manhattan distance-the distance between two points in the north-south direction plus the distance in the east-west direction, e.g., d (i, j) = |x i -x j |+|y i -y j As shown, for a town street with a regular arrangement of north-south, east-west, the distance from one point to another is exactly the distance routed in the north-south direction plus the distance routed in the east-west direction, so manhattan distance is also known as taxi distance.
Round algorithm: the method is used for generating a circular bending waveguide and generating a 90-degree circular arc waveguide with a certain radius at a turning.
S3, counting the number, the bending number and the length of the crossed waveguide devices of each link, and adding the bending number and/or the link line segments by adding the symbols of the crossed waveguide devices and/or adding control points in the links so that the number, the bending number and the length of the crossed waveguide devices of all links are consistent to finish the link path planning.
Specifically, step S3 includes:
s31, counting the number, bending number and length of the crossed waveguide devices of each link, and determining the number balance value, bending number balance value and link length balance value of the crossed waveguide devices of the links;
s32, adding symbols of the crossed waveguide devices to enable the number of the crossed waveguide devices of each link to reach the number balance value of the crossed waveguide devices;
s33, forming a U-shaped waveguide structure by adding control points on the link so as to change the bending quantity and length of the link at the same time;
and/or adding control points to form S-shaped bends at the bending positions of the links so as to keep the length of the links unchanged but change the bending quantity of the links, and enabling the bending quantity and the length of all the links to reach a bending quantity balance value and a link length balance value.
Referring to fig. 2, the embodiment of the present invention mainly adopts two ways to balance the bending number and the length of the link:
u-shaped balance: i.e. forming a U-shaped waveguide structure over the link, in this way both the number of bends and the waveguide length can be increased, and an increase in the length of the P1 path can be seen in fig. 2, with 4 more bends than before balancing.
S-type balance: that is, in the bending position of the link, the control point is added to form an S-shaped bend, in this way, only the number of bends is increased, the waveguide length is not changed, and it can be seen in fig. 2 that the length of the P2 path remains unchanged, and the number of bends is 2 more than before balancing.
It should be noted that, in this embodiment, since the U-shaped balance is increased by at most 4 bending numbers, which is 2 greater than the maximum bending number after the Manhattan distance algorithm is initialized, the bending number balance value of the link is the maximum bending number value owned by a single link plus 2. Further, it is understood that the link length balance value is the length value of the longest link among all links.
Finally, after balancing the number of bends, it is necessary to balance the waveguide lengths, and as shown in fig. 2 (right), it is known that the paths of P1 and P2 satisfy L2> L1, so it is necessary to add a waveguide where P1 forms a U-shaped waveguide structure, so that the final waveguide length coincides with L2, and the specific length is calculated as adding a waveguide having a length of (L2-L1)/2 at the corresponding position of the U-shaped waveguide structure in the figure.
The following is a specific example:
firstly, inputting PCels, placement positions and connection relations among devices through a Manhatten path planning algorithm, setting the bending radius as r, and initializing a chip layout. The waveguide routing of the initialization path is then adjusted to match the length, number of bends, and number of cross cells of the plurality of WG paths. For example, when paths Pi and Pj are required to realize the addition of a cross device, the length of the paths is required to satisfy Li-lj+.1nm, the number of bends bi=bj, and the number of cross cells ci=cj.
Specific analysis for different types of link classifications is as follows:
(1) There are waveguide intersections in the initializing layout links. As shown in fig. 3, paths P1 and P2 are generated and crossed in the initialized layout, loss is ensured to be reduced as much as possible in the paths, a cross unit is added at the cross point, the cross point coordinates are calculated, then the cross unit is placed at the cross point, and finally the link relation between pcells is updated according to layout automation wiring, so that a new waveguide routing is generated.
(2) The cross device needs to be added in other paths. In fig. 4, paths P1, P2, P3 need to be uniform in length, uniform in number of bends, and uniform in number of cross devices per path. There is one intersection of paths P2 and P3, so a cross device should be added to path P1.
(3) When the lengths of the paths are consistent, new control points are calculated and added to match the lengths and the bending numbers between the paths and minimize the layout area. As shown in fig. 2, the equilibrium length of P1 and P2 is required: l1=70 um, l2=100 um, bending number: b1 To meet the balance requirement, L1 is increased to L2, where P1 bends. To meet the equal number of bends, the number of bends on each path is increased to the maximum number of bends plus 2, i.e., b1=max (B1, B2) +2=4, b2=max (B1, B2) +2=4. A new curve is added by adding a new control point in the layout, the position of which is set such that each path length is equal to the maximum length in the corresponding path, i.e. l1=max (L1, L2), l2=max (L1, L2). It should be noted that the control_points coordinates of the waveguide should be set near the initialized path coordinate range to minimize layout area while avoiding control_points from affecting the waveguide routing to create new intersections.
S4, mapping the completed link path planning into waveguide routing, and mapping the cross waveguide device symbol into a cross waveguide device.
Finally, the waveguide lengths, the number of bent waveguides and the number of crossed waveguides on the plurality of waveguide paths are consistent, and the completed link path planning can be mapped into waveguide tracks, and the crossed waveguide device symbols can be mapped into crossed waveguide devices.
In summary, the layout wiring method of the optoelectronic chip in the invention comprises the following steps: mapping the layout of the optoelectronic chip to a two-dimensional coordinate system, mapping the PCell port of the parameterized unit to point coordinates, and mapping the waveguide to be wired to a link segment; initializing an optoelectronic chip layout and links, and generating a shortest link path between each group of PCell ports; counting the number, the bending number and the length of the crossed waveguide devices of each link, and adding the number of the bent waveguide devices and/or the line segments of the links by adding symbols of the crossed waveguide devices and/or adding control points in the links so as to enable the number, the bending number and the length of the crossed waveguide devices of all the links to be consistent, thereby completing the planning of the link paths; the completed link path plan is mapped to waveguide traces and the cross waveguide device symbols are mapped to cross waveguide devices. Therefore, the length balance, the bending quantity balance and the cross waveguide device quantity balance of the routing of the plurality of waveguides are realized, and finally, the length error among each waveguide is smaller than an expected value, the quantity of the bent waveguides and the quantity of the cross waveguides are consistent. Meanwhile, the limit condition is met, the waveguide is allowed to be crossed in the wiring process, the layout utilization area is considered, and waste is avoided.
The embodiment of the invention also provides an optoelectronic chip layout wiring device which comprises a mapping module, an initializing module and a balancing module.
The mapping module is used for mapping the layout of the optoelectronic chip to a two-dimensional coordinate system, mapping the PCell port of the parameterized unit to point coordinates and mapping the waveguide to be wired to a link line segment;
the initialization module is used for initializing the layout and the links of the optoelectronic chip and generating shortest link paths among all groups of PCell ports;
the balancing module is used for counting the number, the bending number and the length of the crossed waveguide devices of each link, and the number, the bending number and the length of the crossed waveguide devices of all links are consistent by adding the signs of the crossed waveguide devices and/or adding control points in the links to add the bending number and/or the link line segments so as to complete the link path planning;
the mapping module is further configured to map the completed link path plan to waveguide traces and cross waveguide device symbols to cross waveguide devices.
In some embodiments, the balancing module counts the number, the number of bends and the length of the cross waveguide devices of each link, and adds the number of bends and/or the line segments of the links by adding cross waveguide device symbols and/or adding control points to the links, so that the number, the number of bends and the length of the cross waveguide devices of all links are consistent, including:
counting the number, bending number and length of the crossed waveguide devices of each link, and determining the number balance value, bending number balance value and link length balance value of the crossed waveguide devices of the links;
adding cross waveguide device symbols to enable the number of the cross waveguide devices of each link to reach the balance value of the number of the cross waveguide devices;
forming a U-shaped waveguide structure by adding control points on the links so as to change the bending quantity and length of the links simultaneously;
and/or adding control points to form S-shaped bends at the bending positions of the links so as to keep the length of the links unchanged but change the bending quantity of the links, and enabling the bending quantity and the length of all the links to reach a bending quantity balance value and a link length balance value.
In some embodiments, the link's cross waveguide device number balance value is the maximum cross waveguide device number value owned by a single link; the bending quantity balance value of the link is the maximum bending quantity value which is owned by a single link plus 2; the link length balance value is the length value of the longest link in all links.
In some embodiments, the initialization module initializes the optoelectronic chip layout and links according to a Manhattan algorithm and a Round algorithm, generating Manhattan shortest link paths between each group of PCell ports.
In some embodiments, the balancing module sets the added control point near the initialized link path.
The embodiment of the invention also provides equipment, which comprises a processor, a memory and a computer program stored on the memory and executable by the processor, wherein the steps of the layout wiring method of the optoelectronic chip are realized when the computer program is executed by the processor.
It should be appreciated that the processor may be a central processing unit (Central Processing Unit, CPU), but may also be other general purpose processors, digital signal processors (Digital Signal Processor, DSP), application specific integrated circuits (Application Specific Integrated Circuit, ASIC), field-programmable gate arrays (Field-Programmable Gate Array, FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, or the like. Wherein the general purpose processor may be a microprocessor or the processor may be any conventional processor or the like.
The embodiment of the invention also provides a computer readable storage medium, wherein the computer readable storage medium is stored with a computer program, and the steps of the layout wiring method of the optoelectronic chip are realized when the computer program is executed by a processor.
Those of ordinary skill in the art will appreciate that all or some of the steps, systems, functional modules/units in the apparatus, and methods disclosed above may be implemented as software, firmware, hardware, and suitable combinations thereof. In a hardware implementation, the division between the functional modules/units mentioned in the above description does not necessarily correspond to the division of physical components; for example, one physical component may have multiple functions, or one function or step may be performed cooperatively by several physical components. Some or all of the physical components may be implemented as software executed by a processor, such as a central processing unit, digital signal processor, or microprocessor, or as hardware, or as an integrated circuit, such as an application specific integrated circuit. Such software may be distributed on computer-readable storage media, which may include computer-readable storage media (or non-transitory media) and communication media (or transitory media).
The term computer-readable storage medium includes volatile and nonvolatile, removable and non-removable media implemented in any method or technology for storage of information, such as computer-readable instructions, data structures, program modules or other data, as known to those skilled in the art. Computer-readable storage media includes, but is not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital Versatile Disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other medium which can be used to store the desired information and which can be accessed by a computer. Furthermore, as is well known to those of ordinary skill in the art, communication media typically embodies computer readable instructions, data structures, program modules or other data in a modulated data signal such as a carrier wave or other transport mechanism and includes any information delivery media.
By way of example, the computer readable storage medium may be an internal storage unit of the electronic device of the foregoing embodiments, such as a hard disk or a memory of the electronic device. The computer readable storage medium may also be an external storage device of the electronic device, such as a plug-in hard disk, a Smart Media Card (SMC), a Secure Digital (SD) Card, a Flash memory Card (Flash Card) or the like, which are provided on the electronic device.
The foregoing is merely a specific implementation of the embodiment of the present invention, but the protection scope of the embodiment of the present invention is not limited thereto, and any person skilled in the art may easily think of various equivalent modifications or substitutions within the technical scope of the embodiment of the present invention, and these modifications or substitutions should be covered in the protection scope of the embodiment of the present invention. Therefore, the protection scope of the embodiments of the present invention shall be subject to the protection scope of the claims.
Claims (10)
1. An optoelectronic chip layout wiring method is characterized by comprising the following steps:
mapping the layout of the optoelectronic chip to a two-dimensional coordinate system, mapping the PCell port of the parameterized unit to point coordinates, and mapping the waveguide to be wired to a link segment;
initializing an optoelectronic chip layout and links, and generating a shortest link path between each group of PCell ports;
counting the number, the bending number and the length of the crossed waveguide devices of each link, and adding the number of the bent waveguide devices and/or the line segments of the links by adding symbols of the crossed waveguide devices and/or adding control points in the links so as to enable the number, the bending number and the length of the crossed waveguide devices of all the links to be consistent, thereby completing the planning of the link paths;
the completed link path plan is mapped to waveguide traces and the cross waveguide device symbols are mapped to cross waveguide devices.
2. An optoelectronic chip layout wiring method according to claim 1, wherein the counting of the number, the number of bends and the length of the cross waveguide devices of each link, by adding cross waveguide device symbols in the links and/or adding control points to add the number of bends and/or link segments, makes the number, the number of bends and the length of the cross waveguide devices of all links uniform, so as to complete the link path planning, comprises:
counting the number, bending number and length of the crossed waveguide devices of each link, and determining the number balance value, bending number balance value and link length balance value of the crossed waveguide devices of the links;
adding cross waveguide device symbols to enable the number of the cross waveguide devices of each link to reach the balance value of the number of the cross waveguide devices;
forming a U-shaped waveguide structure by adding control points on the links so as to change the bending quantity and length of the links simultaneously;
and/or adding control points to form S-shaped bends at the bending positions of the links so as to keep the length of the links unchanged but change the bending quantity of the links, and enabling the bending quantity and the length of all the links to reach a bending quantity balance value and a link length balance value.
3. An optoelectronic chip layout wiring method according to claim 2, wherein:
the number balance value of the crossed waveguide devices of the links is the maximum number value of the crossed waveguide devices in a single link;
the bending quantity balance value of the link is the maximum bending quantity value which is owned by a single link plus 2;
the link length balance value is the length value of the longest link in all links.
4. An optoelectronic chip layout wiring method according to claim 1, wherein:
and initializing an optoelectronic chip layout and links according to a Manhattan algorithm and a Round algorithm, and generating Manhattan shortest link paths among each group of PCell ports.
5. An optoelectronic chip layout wiring method according to claim 1, wherein: the added control point is set near the initialized link path.
6. An optoelectronic chip layout wiring device, comprising:
the mapping module is used for mapping the layout of the optoelectronic chip to a two-dimensional coordinate system, mapping the PCell port of the parameterized unit to point coordinates and mapping the waveguide to be wired to a link line segment;
the initialization module is used for initializing the layout and the links of the optoelectronic chip and generating shortest link paths among all groups of PCell ports;
the balancing module is used for counting the number, the bending number and the length of the crossed waveguide devices of each link, and the number, the bending number and the length of the crossed waveguide devices of all links are consistent by adding the signs of the crossed waveguide devices and/or adding control points in the links to add the bending number and/or the link line segments so as to complete the link path planning;
the mapping module is further configured to map the completed link path plan to waveguide traces and cross waveguide device symbols to cross waveguide devices.
7. An optoelectronic chip layout wiring device according to claim 6, wherein the balancing module counts the number, the number of bends and the length of the cross waveguide devices of each link, and adds the number of bends and/or the length of the cross waveguide devices of all links by adding cross waveguide device symbols and/or adding control points to the links to increase the number of bends and/or the length of the links, comprising:
counting the number, bending number and length of the crossed waveguide devices of each link, and determining the number balance value, bending number balance value and link length balance value of the crossed waveguide devices of the links;
adding cross waveguide device symbols to enable the number of the cross waveguide devices of each link to reach the balance value of the number of the cross waveguide devices;
forming a U-shaped waveguide structure by adding control points on the links so as to change the bending quantity and length of the links simultaneously;
and/or adding control points to form S-shaped bends at the bending positions of the links so as to keep the length of the links unchanged but change the bending quantity of the links, and enabling the bending quantity and the length of all the links to reach a bending quantity balance value and a link length balance value.
8. An optoelectronic chip layout wiring device as claimed in claim 7 wherein:
the number balance value of the crossed waveguide devices of the links is the maximum number value of the crossed waveguide devices in a single link;
the bending quantity balance value of the link is the maximum bending quantity value which is owned by a single link plus 2;
the link length balance value is the length value of the longest link in all links.
9. An apparatus comprising a processor, a memory, and a computer program stored on the memory and executable by the processor, wherein the computer program when executed by the processor performs the steps of an optoelectronic chip layout routing method according to any one of claims 1 to 5.
10. A computer-readable storage medium, on which a computer program is stored, wherein the computer program, when executed by a processor, implements the steps of an optoelectronic chip layout routing method according to any one of claims 1 to 5.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310301068.2A CN116402009A (en) | 2023-03-24 | 2023-03-24 | Layout wiring method, device and equipment for optoelectronic chip and storage medium |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310301068.2A CN116402009A (en) | 2023-03-24 | 2023-03-24 | Layout wiring method, device and equipment for optoelectronic chip and storage medium |
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| Publication Number | Publication Date |
|---|---|
| CN116402009A true CN116402009A (en) | 2023-07-07 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202310301068.2A Pending CN116402009A (en) | 2023-03-24 | 2023-03-24 | Layout wiring method, device and equipment for optoelectronic chip and storage medium |
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| Country | Link |
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| CN (1) | CN116402009A (en) |
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- 2023-03-24 CN CN202310301068.2A patent/CN116402009A/en active Pending
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