CN116167328A - Layout wiring method, device and equipment for optoelectronic chip and storage medium - Google Patents
Layout wiring method, device and equipment for optoelectronic chip and storage medium Download PDFInfo
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Abstract
The invention discloses a method, a device, equipment and a storage medium for wiring an optoelectronic chip layout, which relate to the technical field of automatic design wiring of the optoelectronic chip layout, and the method comprises the following steps: mapping the layout of the optoelectronic chip to a two-dimensional coordinate system, mapping the PCell port of the parameterized unit to point coordinates, and mapping the waveguide to be wired to a link segment; initializing an optoelectronic chip layout and links, and generating a shortest link path between each group of PCell ports; counting the bending number and the bending length of each link, and adding control points in the links to increase the bending number and/or the link line segments so that the bending number and the bending length of all the links are consistent; and adjusting the link control points to ensure that all links have no cross so as to complete the link path planning, and mapping the link path planning into waveguide routing. The invention can make the length of the generated multiple waveguides equal, the bending quantity equal, avoid the intersection of the waveguides, and ensure the smaller occupied area of the waveguides and the shortest total length of the waveguides.
Description
Technical Field
The invention relates to the technical field of automatic design wiring of optoelectronic chips, in particular to a layout wiring method, device and equipment of an optoelectronic chip and a storage medium.
Background
The conventional optoelectronic chip layout automatic design tool automatically generates waveguide routing according to a Manhattan algorithm for port links between parameterized units (Parameterized cell, PCell) or between system links, namely, a shortest path which is horizontal, flat and vertical is planned.
Many commercial CAD suppliers now offer automated WG (waveguide) routing tools that focus on routing connecting one port to another, fixing waveguide length and number of bends, while bypassing obstacles (e.g., other parameterized cells or chip structures). However, for phase sensitive link structures, such as Integrated Coherent Receivers (ICR), etc., there is a need to precisely control the length of the connection waveguide in different links, and none of the existing methods can achieve balancing the total length and the number of bends of multiple WG paths at the same time.
The tool aims at the problem of equal length of the waveguide, does not realize automatic equal length wiring, still relies on manual calculation of the length difference and the bending wave derivative difference, and changes the trend of the waveguide by adding a control point (control_points) on the waveguide path, thereby realizing the change of the length of the waveguide and the number of the bending waveguides. The waveguide equal-length wiring is realized in a semi-manual and semi-automatic mode, the labor is consumed, the time is consumed, the mistakes are easy to occur, and the full waveguide length and the occupied area of the whole module are not necessarily optimal solutions when the equal-length waveguide is finally realized.
However, for Waveguide (WG) routing design of a coherent optical chip layout, the problem that a plurality of waveguides are equal in routing length needs to be considered, that is, the waveguides are equal in length, the number of curved waveguides is equal (the curved waveguides are generally the same in radius by default), and at the same time, it is desirable that the waveguide length be smaller to reduce the loss of optical power (although the loss per unit length is very small in silicon light) and the effect on phase delay. The high refractive index and contrast of silicon impose stringent requirements on the dimensions of silicon photonic links, and nanoscale variations in waveguide core width or thickness can have a non-negligible impact on the performance of the photonic link.
Disclosure of Invention
Aiming at the defects existing in the prior art, the first aspect of the invention provides a layout wiring method of an optoelectronic chip, which can lead the lengths of a plurality of generated waveguides to be equal, lead the bending quantity to be equal, avoid the intersection of the waveguides, ensure that the occupied area of the waveguides is smaller and lead the total length of the waveguides to be shortest.
In order to achieve the above purpose, the invention adopts the following technical scheme:
an optoelectronic chip layout wiring method, comprising the following steps:
mapping the layout of the optoelectronic chip to a two-dimensional coordinate system, mapping the PCell port of the parameterized unit to point coordinates, and mapping the waveguide to be wired to a link segment;
initializing an optoelectronic chip layout and links, and generating a shortest link path between each group of PCell ports;
counting the bending number and the bending length of each link, and adding control points in the links to increase the bending number and/or the link line segments so that the bending number and the bending length of all the links are consistent;
and adjusting the link control points to ensure that all links have no cross so as to complete the link path planning, and mapping the link path planning into waveguide routing.
In some embodiments, the counting the number and the length of the bending of each link, adding a control point to the links to add the number of bending and/or the length of the links, so that the number and the length of the bending of all links are consistent, includes:
counting the bending number and length of each link, and determining the bending number balance value and the link length balance value of the link;
forming a U-shaped waveguide structure by adding control points on the links so as to change the bending quantity and length of the links simultaneously;
and/or adding control points to form S-shaped bends at the bending positions of the links so as to keep the length of the links unchanged but change the bending quantity of the links, and enabling the bending quantity and the length of all the links to reach a bending quantity balance value and a link length balance value.
In some embodiments, the link's bending number balance value is the maximum bending number value owned by a single link plus 2;
the link length balance value is the length value of the longest link in all links.
In some embodiments, the adjusting the link control point to make the links have no cross, includes:
extracting a control point list corresponding to each link;
the value of the abscissa and the ordinate of the link control point is compared and adjusted, so that the links have no cross.
In some embodiments, the comparing and adjusting the magnitude of the abscissa and the ordinate of the link control point to make the links have no cross, includes:
when two link control points meet:
when Pa [ i ] & y=Pb [ j ] & y=Pb [ k ] & y, and Pb [ k ] & x < Pa [ i ] & x < Pb [ j ] & x, judging that the link transversely crosses, wherein Pa and Pb are path symbols, i, j and k are control points, and x and y are the horizontal coordinate and the vertical coordinate of the control points respectively;
and (3) adjusting the coordinates of Pa [ i ] to enable Pa [ i ]. Y=Pa [ i ]. Y + -r, wherein r is the length of the bending radius.
In some embodiments, the comparing and adjusting the magnitude of the abscissa and the ordinate of the link control point to make the links have no cross, further includes:
when two link control points meet:
when Pa [ i ] & x=Pb [ j ] & x=Pb [ k ] & x, and Pb [ k ] & y is smaller than Pa [ i ] & y is smaller than Pb [ j ] & y, judging that the longitudinal direction of the link is crossed, wherein Pa and Pb are path symbols, i, j and k are control points, and x and y are the horizontal coordinate and the vertical coordinate of the control points respectively;
and (3) adjusting the coordinates of Pa [ i ] to enable Pa [ i ]. X=Pa [ i ]. X + -r, wherein r is the length of the bending radius.
In some embodiments, the optoelectronic chip layout and links are initialized according to a Manhattan algorithm and a Round algorithm, and Manhattan shortest link paths are generated between each group of PCell ports.
The second aspect of the invention provides an optoelectronic chip layout wiring device, which can make the lengths of a plurality of generated waveguides equal, the number of bends equal, avoid the intersection of the waveguides, ensure that the occupied area of the waveguides is smaller and the total length of the waveguides is shortest.
In order to achieve the above purpose, the invention adopts the following technical scheme:
an optoelectronic chip layout wiring device, comprising:
the mapping module is used for mapping the layout of the optoelectronic chip to a two-dimensional coordinate system, mapping the PCell port of the parameterized unit to point coordinates and mapping the waveguide to be wired to a link line segment;
the initialization module is used for initializing the layout and the links of the optoelectronic chip and generating shortest link paths among all groups of PCell ports;
the balancing module is used for counting the bending number and length of each link, enabling the bending number and length of all links to be consistent by adding the bending number and/or adding the link line segments in the links, and adjusting the link control points to enable all links to be free of crossing so as to complete the link path planning;
the mapping module is further configured to map the completed link path plan to a waveguide trace.
A third aspect of the present invention provides an apparatus comprising a processor, a memory, and a computer program stored on the memory and executable by the processor, wherein the computer program when executed by the processor implements the steps of any one of the above-described optoelectronic chip layout routing methods.
A fourth aspect of the present invention provides a computer readable storage medium having a computer program stored thereon, wherein the computer program, when executed by a processor, implements the steps of any one of the above-described optoelectronic chip layout routing methods.
Compared with the prior art, the invention has the advantages that:
the layout wiring method of the optoelectronic chip in the invention comprises the following steps: mapping the layout of the optoelectronic chip to a two-dimensional coordinate system, mapping the PCell port of the parameterized unit to point coordinates, and mapping the waveguide to be wired to a link segment; initializing an optoelectronic chip layout and links, and generating a shortest link path between each group of PCell ports; counting the bending number and the bending length of each link, and adding control points in the links to increase the bending number and/or the link line segments so that the bending number and the bending length of all the links are consistent; and adjusting the link control points to ensure that all links have no cross so as to complete the link path planning, and mapping the link path planning into waveguide routing. Therefore, the length balance of the routing of the plurality of waveguides can be realized, the bending quantity is balanced, and finally, the length error between each waveguide is smaller than an expected value. Meanwhile, the limit condition is met, the waveguide is prevented from crossing in the wiring process, the layout utilization area is considered, and waste is avoided.
Drawings
FIG. 1 is a flow chart of an optoelectronic chip layout wiring method in an embodiment of the invention;
FIG. 2 is a schematic diagram of a balancing mode in an embodiment of the present invention;
FIG. 3 is a schematic diagram of a path initialization in an embodiment of the present invention;
FIG. 4 is a schematic diagram of a path control point after adjustment according to an embodiment of the present invention;
fig. 5 is a schematic diagram after path balancing in an embodiment of the invention.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present application more clear, the technical solutions of the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is apparent that the described embodiments are some embodiments of the present application, but not all embodiments. All other embodiments, which can be made by one of ordinary skill in the art without undue burden from the present disclosure, are within the scope of the present application based on the embodiments herein.
Referring to fig. 1, an embodiment of the present invention provides a layout wiring method for an optoelectronic chip, which includes the following steps:
s1, mapping an optoelectronic chip layout to a two-dimensional coordinate system, mapping a parameterized unit PCell port to a point coordinate, and mapping a waveguide to be wired to a link line segment.
Aiming at the defect of the existing optoelectronic chip layout automatic design tool in the aspect of equal-length wiring of waveguides, the embodiment of the invention realizes an automatic wiring mathematical model, the model maps the optoelectronic chip layout to a two-dimensional coordinate system, maps PCell ports to point coordinates, and maps waveguides needing wiring to link line segments, wherein port information comprises angle information.
S2, initializing an optoelectronic chip layout and links, and generating a shortest link path between each group of PCell ports.
The embodiment of the invention provides an automatic wiring algorithm based on a Manhattan path planning algorithm and a Round algorithm. Under the condition of considering various limitations of waveguide wiring avoidance, the algorithm framework maps each component into a Cartesian coordinate system, realizes length balance of a plurality of waveguide routes according to defined port link relation, limiting conditions, a Manhattan algorithm and a Round algorithm, and finally realizes that the length error between each waveguide is smaller than 1nm.
Meanwhile, the limit condition is met, the waveguide is prevented from crossing in the wiring process, the layout utilization area is considered, and waste is avoided.
Specifically, all newly added control points should be in the range of the existing ports as far as possible, i.e. Pleft, x < Pnew, x < Pright, x, pdown, y < Pnew, y < Pup, y, where P is a path symbol, left, new, right, down and up are related control points, and x and y are the abscissa and ordinate of the control points, respectively.
Specifically, in step S2, first, a link relation of ports is defined, a curved waveguide radius value r is set, and curves generated in all paths are uniform.
And initializing the layout and links of the optoelectronic chip according to a Manhattan algorithm and a Round algorithm, and generating Manhattan shortest link paths among each group of PCell ports.
Manhattan distance algorithm: manhattan distance-the distance between two points in the north-south direction plus the distance in the east-west direction, e.g., d (i, j) = |x i -x j |+|y i -y j As shown, for a town street with a regular arrangement of north-south, east-west, the distance from one point to another is exactly the distance routed in the north-south direction plus the distance routed in the east-west direction, so manhattan distance is also known as taxi distance.
Round algorithm: the method is used for generating a circular bending waveguide and generating a 90-degree circular arc waveguide with a certain radius at a turning.
S3, counting the bending number and the bending length of each link, and adding control points in the links to increase the bending number and/or the link line segments so that the bending number and the bending length of all the links are consistent.
Specifically, step S3 includes:
s31, counting the bending number and the bending length of each link, and determining the bending number balance value and the link length balance value of the links.
S32, forming a U-shaped waveguide structure by adding control points on the link so as to change the bending quantity and length of the link at the same time;
and/or adding control points to form S-shaped bends at the bending positions of the links so as to keep the length of the links unchanged but change the bending quantity of the links, and enabling the bending quantity and the length of all the links to reach a bending quantity balance value and a link length balance value.
Referring to fig. 2, the embodiment of the present invention mainly adopts two ways to balance the bending number and the length of the link:
u-shaped balance: i.e. forming a U-shaped waveguide structure over the link, in this way both the number of bends and the waveguide length can be increased, and an increase in the length of the P1 path can be seen in fig. 2, with 4 more bends than before balancing.
S-type balance: that is, in the bending position of the link, the control point is added to form an S-shaped bend, in this way, only the number of bends is increased, the waveguide length is not changed, and it can be seen in fig. 2 that the length of the P2 path remains unchanged, and the number of bends is 2 more than before balancing.
It should be noted that, in this embodiment, since the U-shaped balance is adopted to increase the maximum number of bends by 4, which is 2 greater than the maximum number of bends after the Manhattan distance algorithm is initialized, the link bend number balance value is the maximum number of bends in a single link plus 2. Further, it is understood that the link length balance value is the length value of the longest link among all links.
Finally, after balancing the number of bends, it is necessary to balance the waveguide lengths, and as shown in fig. 2 (right), it is known that the paths of P1 and P2 satisfy L2> L1, so it is necessary to add a waveguide where P1 forms a U-shaped waveguide structure, so that the final waveguide length coincides with L2, and the specific length is calculated as adding a waveguide having a length of (L2-L1)/2 at the corresponding position of the U-shaped waveguide structure in the figure.
S4, adjusting the link control points to enable all links to be free of crossing, so that the link path planning is completed, and the link path planning is mapped into waveguide routing.
S41, extracting a control point list corresponding to each link.
S42, comparing and adjusting the values of the abscissas and the ordinates of the link control points to ensure that all links have no cross.
Specifically, when the two link control points satisfy:
when Pa [ i ] & y=Pb [ j ] & y=Pb [ k ] & y, and Pb [ k ] & x < Pa [ i ] & x < Pb [ j ] & x, judging that the link transversely crosses, wherein Pa and Pb are path symbols, i, j and k are control points, and x and y are the horizontal coordinate and the vertical coordinate of the control points respectively;
and (3) adjusting the coordinates of Pa [ i ] to enable Pa [ i ]. Y=Pa [ i ]. Y + -r, wherein r is the length of the bending radius.
When two link control points meet:
when Pa [ i ] & x=Pb [ j ] & x=Pb [ k ] & x, and Pb [ k ] & y is smaller than Pa [ i ] & y is smaller than Pb [ j ] & y, judging that the longitudinal direction of the link is crossed, wherein Pa and Pb are path symbols, i, j and k are control points, and x and y are the horizontal coordinate and the vertical coordinate of the control points respectively;
and (3) adjusting the coordinates of Pa [ i ] to enable Pa [ i ]. X=Pa [ i ]. X + -r, wherein r is the length of the bending radius.
The following is a specific example for further explanation:
referring to fig. 3 to 5, the link paths P1, P2 are initialized, wherein the control point coordinates of P1 and P2 are respectively:
P1[(0,0),(0,-20),(-40,-20),(-40,-60)]；
P2[(5,0),(5,-20),(-15,-20),(-15,-60)]；
it can be seen that P1 has a length of 100um, P2 has a length of 80um, both have a number of bends of 2, a link length balance of 100um, and a link bend number balance of 4 (because the maximum value is 2).
Since P2[3] y=P1 [2] y=P1 [3] y, P1[3] x < P2[3] x < P1[2] x. In order to avoid the crossing of the waveguides, the control point of P2 is adjusted, P2[3]. Y < P1[2]. Y, and the specific moving length is set to be the length of a bending radius. Then, according to the method shown above, the length and the bending number are balanced, namely, the P1 is balanced in an S shape, the P2 is balanced in a U shape, as shown in FIG. 5, the length of the two balanced parts is 100um, and the bending number is 4.
In summary, the layout wiring method of the optoelectronic chip in the invention comprises the following steps: mapping the layout of the optoelectronic chip to a two-dimensional coordinate system, mapping the PCell port of the parameterized unit to point coordinates, and mapping the waveguide to be wired to a link segment; initializing an optoelectronic chip layout and links, and generating a shortest link path between each group of PCell ports; counting the bending number and the bending length of each link, and adding control points in the links to increase the bending number and/or the link line segments so that the bending number and the bending length of all the links are consistent; and adjusting the link control points to ensure that all links have no cross so as to complete the link path planning, and mapping the link path planning into waveguide routing. Therefore, the length balance of the routing of the plurality of waveguides can be realized, the bending quantity is balanced, and finally, the length error between each waveguide is smaller than an expected value. Meanwhile, the limit condition is met, the waveguide is prevented from crossing in the wiring process, the layout utilization area is considered, and waste is avoided.
The embodiment of the invention also provides an optoelectronic chip layout wiring device which comprises a mapping module, an initializing module and a balancing module.
The mapping module is used for mapping the layout of the optoelectronic chip to a two-dimensional coordinate system, mapping the PCell port of the parameterized unit to point coordinates and mapping the waveguide to be wired to a link line segment;
the initialization module is used for initializing the layout and the links of the optoelectronic chip and generating shortest link paths among all groups of PCell ports;
the balancing module is used for counting the bending number and length of each link, enabling the bending number and length of all links to be consistent by adding the bending number and/or adding the link line segments in the links, and adjusting the link control points to enable all links to be free of crossing so as to complete the link path planning;
the mapping module is further configured to map the completed link path plan to a waveguide trace.
In some embodiments, the balancing module counts the number and length of the bends of each link, and adds a control point to the links to increase the number of bends and/or link segments, so that the number and length of bends of all links are consistent, including:
counting the bending number and length of each link, and determining the bending number balance value and the link length balance value of the link;
forming a U-shaped waveguide structure by adding control points on the links so as to change the bending quantity and length of the links simultaneously;
and/or adding control points to form S-shaped bends at the bending positions of the links so as to keep the length of the links unchanged but change the bending quantity of the links, and enabling the bending quantity and the length of all the links to reach a bending quantity balance value and a link length balance value.
In some embodiments, the link's bending number balance value is the maximum bending number value owned by a single link plus 2; the link length balance value is the length value of the longest link in all links.
In some embodiments, the balancing module adjusts the link control point so that there is no cross-over between links, including:
extracting a control point list corresponding to each link;
the value of the abscissa and the ordinate of the link control point is compared and adjusted, so that the links have no cross.
In some embodiments, the balancing module compares and adjusts the magnitude of the abscissa and the ordinate of the link control point to make the links have no cross, and the balancing module includes:
when two link control points meet:
when Pa [ i ] & y=Pb [ j ] & y=Pb [ k ] & y, and Pb [ k ] & x < Pa [ i ] & x < Pb [ j ] & x, judging that the link transversely crosses, wherein Pa and Pb are path symbols, i, j and k are control points, and x and y are the horizontal coordinate and the vertical coordinate of the control points respectively;
and (3) adjusting the coordinates of Pa [ i ] to enable Pa [ i ]. Y=Pa [ i ]. Y + -r, wherein r is the length of the bending radius.
In some embodiments, the balancing module makes no cross between links by comparing and adjusting the magnitude of the abscissa and the ordinate of the link control point, and further includes:
when two link control points meet:
when Pa [ i ] & x=Pb [ j ] & x=Pb [ k ] & x, and Pb [ k ] & y is smaller than Pa [ i ] & y is smaller than Pb [ j ] & y, judging that the longitudinal direction of the link is crossed, wherein Pa and Pb are path symbols, i, j and k are control points, and x and y are the horizontal coordinate and the vertical coordinate of the control points respectively;
and (3) adjusting the coordinates of Pa [ i ] to enable Pa [ i ]. X=Pa [ i ]. X + -r, wherein r is the length of the bending radius.
In some embodiments, the initialization module initializes the optoelectronic chip layout and links according to a Manhattan algorithm and a Round algorithm, generating Manhattan shortest link paths between each group of PCell ports.
The embodiment of the invention also provides equipment, which comprises a processor, a memory and a computer program stored on the memory and executable by the processor, wherein the steps of the layout wiring method of the optoelectronic chip are realized when the computer program is executed by the processor.
It should be appreciated that the processor may be a central processing unit (Central Processing Unit, CPU), but may also be other general purpose processors, digital signal processors (Digital Signal Processor, DSP), application specific integrated circuits (Application Specific Integrated Circuit, ASIC), field-programmable gate arrays (Field-Programmable Gate Array, FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, or the like. Wherein the general purpose processor may be a microprocessor or the processor may be any conventional processor or the like.
The embodiment of the invention also provides a computer readable storage medium, wherein the computer readable storage medium is stored with a computer program, and the steps of the layout wiring method of the optoelectronic chip are realized when the computer program is executed by a processor.
Those of ordinary skill in the art will appreciate that all or some of the steps, systems, functional modules/units in the apparatus, and methods disclosed above may be implemented as software, firmware, hardware, and suitable combinations thereof. In a hardware implementation, the division between the functional modules/units mentioned in the above description does not necessarily correspond to the division of physical components; for example, one physical component may have multiple functions, or one function or step may be performed cooperatively by several physical components. Some or all of the physical components may be implemented as software executed by a processor, such as a central processing unit, digital signal processor, or microprocessor, or as hardware, or as an integrated circuit, such as an application specific integrated circuit. Such software may be distributed on computer-readable storage media, which may include computer-readable storage media (or non-transitory media) and communication media (or transitory media).
The term computer-readable storage medium includes volatile and nonvolatile, removable and non-removable media implemented in any method or technology for storage of information, such as computer-readable instructions, data structures, program modules or other data, as known to those skilled in the art. Computer-readable storage media includes, but is not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital Versatile Disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other medium which can be used to store the desired information and which can be accessed by a computer. Furthermore, as is well known to those of ordinary skill in the art, communication media typically embodies computer readable instructions, data structures, program modules or other data in a modulated data signal such as a carrier wave or other transport mechanism and includes any information delivery media.
By way of example, the computer readable storage medium may be an internal storage unit of the electronic device of the foregoing embodiments, such as a hard disk or a memory of the electronic device. The computer readable storage medium may also be an external storage device of the electronic device, such as a plug-in hard disk, a Smart Media Card (SMC), a Secure Digital (SD) Card, a Flash memory Card (Flash Card) or the like, which are provided on the electronic device.
The foregoing is merely a specific implementation of the embodiment of the present invention, but the protection scope of the embodiment of the present invention is not limited thereto, and any person skilled in the art may easily think of various equivalent modifications or substitutions within the technical scope of the embodiment of the present invention, and these modifications or substitutions should be covered in the protection scope of the embodiment of the present invention. Therefore, the protection scope of the embodiments of the present invention shall be subject to the protection scope of the claims.
Claims (10)
1. An optoelectronic chip layout wiring method is characterized by comprising the following steps:
mapping the layout of the optoelectronic chip to a two-dimensional coordinate system, mapping the PCell port of the parameterized unit to point coordinates, and mapping the waveguide to be wired to a link segment;
initializing an optoelectronic chip layout and links, and generating a shortest link path between each group of PCell ports;
counting the bending number and the bending length of each link, and adding control points in the links to increase the bending number and/or the link line segments so that the bending number and the bending length of all the links are consistent;
and adjusting the link control points to ensure that all links have no cross so as to complete the link path planning, and mapping the link path planning into waveguide routing.
2. An optoelectronic chip layout wiring method according to claim 1, wherein the counting of the number and length of bends of each link is performed by adding control points to the links to add the number of bends and/or link segments so that the number of bends and lengths of all links are identical, and the method comprises the steps of:
counting the bending number and length of each link, and determining the bending number balance value and the link length balance value of the link;
forming a U-shaped waveguide structure by adding control points on the links so as to change the bending quantity and length of the links simultaneously;
and/or adding control points to form S-shaped bends at the bending positions of the links so as to keep the length of the links unchanged but change the bending quantity of the links, and enabling the bending quantity and the length of all the links to reach a bending quantity balance value and a link length balance value.
3. An optoelectronic chip layout wiring method according to claim 2, wherein:
the bending quantity balance value of the link is the maximum bending quantity value which is owned by a single link plus 2;
the link length balance value is the length value of the longest link in all links.
4. An optoelectronic chip layout wiring method according to claim 1, wherein the adjusting the link control points so that there is no cross between links comprises:
extracting a control point list corresponding to each link;
the value of the abscissa and the ordinate of the link control point is compared and adjusted, so that the links have no cross.
5. An optoelectronic chip layout wiring method according to claim 4, wherein the comparing and adjusting the magnitude of the abscissa of the link control point to make the links have no cross, comprises:
when two link control points meet:
when Pa [ i ] & y=Pb [ j ] & y=Pb [ k ] & y, and Pb [ k ] & x < Pa [ i ] & x < Pb [ j ] & x, judging that the link transversely crosses, wherein Pa and Pb are path symbols, i, j and k are control points, and x and y are the horizontal coordinate and the vertical coordinate of the control points respectively;
and (3) adjusting the coordinates of Pa [ i ] to enable Pa [ i ]. Y=Pa [ i ]. Y + -r, wherein r is the length of the bending radius.
6. An optoelectronic chip layout wiring method according to claim 4 or 5, wherein the comparing and adjusting the values of the abscissa and the ordinate of the link control points make the links have no cross, and further comprising:
when two link control points meet:
when Pa [ i ] & x=Pb [ j ] & x=Pb [ k ] & x, and Pb [ k ] & y is smaller than Pa [ i ] & y is smaller than Pb [ j ] & y, judging that the longitudinal direction of the link is crossed, wherein Pa and Pb are path symbols, i, j and k are control points, and x and y are the horizontal coordinate and the vertical coordinate of the control points respectively;
and (3) adjusting the coordinates of Pa [ i ] to enable Pa [ i ]. X=Pa [ i ]. X + -r, wherein r is the length of the bending radius.
7. An optoelectronic chip layout wiring method according to claim 1, wherein:
and initializing an optoelectronic chip layout and links according to a Manhattan algorithm and a Round algorithm, and generating Manhattan shortest link paths among each group of PCell ports.
8. An optoelectronic chip layout wiring device, comprising:
the mapping module is used for mapping the layout of the optoelectronic chip to a two-dimensional coordinate system, mapping the PCell port of the parameterized unit to point coordinates and mapping the waveguide to be wired to a link line segment;
the initialization module is used for initializing the layout and the links of the optoelectronic chip and generating shortest link paths among all groups of PCell ports;
the balancing module is used for counting the bending number and length of each link, enabling the bending number and length of all links to be consistent by adding the bending number and/or adding the link line segments in the links, and adjusting the link control points to enable all links to be free of crossing so as to complete the link path planning;
the mapping module is further configured to map the completed link path plan to a waveguide trace.
9. An apparatus comprising a processor, a memory, and a computer program stored on the memory and executable by the processor, wherein the computer program when executed by the processor performs the steps of an optoelectronic chip layout routing method according to any one of claims 1 to 7.
10. A computer-readable storage medium, on which a computer program is stored, wherein the computer program, when executed by a processor, implements the steps of an optoelectronic chip layout routing method according to any one of claims 1 to 7.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310301075.2A CN116167328A (en) | 2023-03-24 | 2023-03-24 | Layout wiring method, device and equipment for optoelectronic chip and storage medium |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310301075.2A CN116167328A (en) | 2023-03-24 | 2023-03-24 | Layout wiring method, device and equipment for optoelectronic chip and storage medium |
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| CN116167328A true CN116167328A (en) | 2023-05-26 |
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| CN202310301075.2A Pending CN116167328A (en) | 2023-03-24 | 2023-03-24 | Layout wiring method, device and equipment for optoelectronic chip and storage medium |
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| CN (1) | CN116167328A (en) |
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