CN1163953C - Substrate-type semiconductor device packing method without glue overflow - Google Patents
Substrate-type semiconductor device packing method without glue overflow Download PDFInfo
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- CN1163953C CN1163953C CNB001345451A CN00134545A CN1163953C CN 1163953 C CN1163953 C CN 1163953C CN B001345451 A CNB001345451 A CN B001345451A CN 00134545 A CN00134545 A CN 00134545A CN 1163953 C CN1163953 C CN 1163953C
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
The present invention discloses a substrate type semiconductor device packaging method which can avoid overflow of colloid. The present invention is characterized in that an extending void part is formed in a specific position in an electrical property insulating layer on the surface of a substrate; the specific position is the crossing point of the electrical property insulating layer, a solid part of a mould and a mould cavity of the mould when the substrate type semiconductor device is fixed to a position in the mould. In the manufacture process of packaging colloid, colloid packaging materials which flow into the void part can rapidly absorb heat in the mould, the viscosity of the colloid packaging materials is increased, and the flow velocity is decelerated; therefore, the colloid packaging materials can not flow into the pressing gap between the electrical property insulating layer and the mould easily, and the overflow of the colloid is avoided.
Description
The present invention relates to a kind of semiconductor packaging, particularly a kind of substrate-type semiconductor device packing method of the glue that prevents to overflow, it can be in order to encapsulating a substrate-type semiconductor device, produces the glue phenomenon of overflowing but can not make on the exposing surface of the encapsulation unit of making.
Substrate-type semiconductor device is a kind of semiconductor device that is established on the substrate (substrate), that is is that ground is settled semiconductor wafer wherein with the substrate.In putting after brilliant program finishes; generally must carry out a packing colloid manufacture process (encapsulation process) again; form a packing colloid (molded compound by die casting method (molding); or title encapsulation body); in order to coat semiconductor chip, protect semiconductor chip can not be subjected to the influence of the moisture of external environment condition or pollution therefrom and damage.
Yet a problem of known substrate-type semiconductor device packing method is the colloid encapsulating material that adopted in the packing colloid manufacture process, be generally epoxy resin (epoxy resin), be easy to overflow to packing colloid exposing surface in addition, even and overflow to the electric connection pad that exposes, make made encapsulation unit have not good outward appearance, and make the electric connection pad that exposes have not good electric connection effect.Below be Figure 1A to 1C, Fig. 2 A to 2B, Fig. 3 A to 3B, and Fig. 4 A to 4C of conjunction with figs., sketch the excessive glue problem in the encapsulation process of substrate-type semiconductor device of four kinds of different types respectively.
Figure 1A to 1C shows a kind of known single-chip bonding wire type substrate-type semiconductor device packing method.
Please at first consult Figure 1A, the composition member of the semiconductor device of this kind pattern comprises: (a) substrate 100, and it has a positive 100a and a back side 100b; (b) the semiconductor chip 110, and it is placed in the positive 100a top of substrate 100; (c) one first electrical insulation layer 121, it is formed on the positive 100a of substrate 100, in order to as a top weld pad cover curtain (solder mask, S/M); (d) one second electrical insulation layer 122, it is formed on the back side 100b of substrate 100, in order to as a bottom weld pad cover curtain; And (e) a plurality of electric connection pads 130, it is arranged on the back side 100b of substrate 100, and by second electrical insulation layer 122 and mutual electrical isolation.
Above-mentioned as yet not package semiconductor device adopt a special set of molds 140 to carry out the packing colloid manufacture process.This set of molds 140 comprises a bed die 141 and a mold 142; Wherein bed die 141 has a smooth upper surface 141a, and mold 142 then has a predetermined die cavity 142a.
See also Figure 1B, then promptly carry out a packing colloid manufacture process, wherein with shown in Figure 1A as yet not package semiconductor device be placed on the certain position of set of molds 140, second electrical insulation layer 122 that also is about to the bottom is pressed on the flat surfaces 141a of bed die 141, and mold 142 is pressed on the top of bed die 141, and make semiconductor chip 110 be arranged in the die cavity 142a of mold 142.Can for example be epoxy resin then, be injected into via the passage shown in the arrow M among the die cavity 142a, form a packing colloid 150 therefrom, in order to coat semiconductor chip 110 and substrate 100 a colloid encapsulating material.
Yet, owing to also can't reach bubble-tight pressing between second electrical insulation layer 122 and the bed die 141, therefore still have an extremely narrow and small slit (as locating of the S indication among Figure 1B) between the two, make an a spot of encapsulating material can infiltrate so far among the S of slit, that is on the lower surface of excessive glue to the second electrical insulation layer 122.
Please then consult Fig. 1 C, after the packing colloid manufacture process is finished, can will finish package semiconductor device and in set of molds 140, take out.But because above-mentioned excessive glue problem, therefore having some residual excessive glue 150a is covered on the lower surface of second electrical insulation layer 122, even and be covered on the exposing surface of electric connection pad 130, make made encapsulation unit have not good outward appearance, and make electric connection pad 130 have not good electric connection effect simultaneously.
A kind of solution of above-mentioned excessive glue problem then promptly adopts sand mill or laser devices to carry out an excessive glue clear program (de-flashprocess) for after the packing colloid manufacture process is finished, and thus residual excessive glue 150a is disposed.
Yet the shortcoming of this kind solution is that it is easy to the lower surface of wounded substrate, makes made encapsulation unit still have not good outward appearance.Known to pile up twin-core sheet bonding wire type substrate-type semiconductor device packing method Fig. 2 A to 2B be cross-sectional view, wherein shows a known twin-core sheet bonding wire type substrate-type semiconductor device packing method that piles up; And this method for packing also has aforesaid excessive glue problem.
Shown in Fig. 2 A, the composition member of the semiconductor device of this kind pattern comprises: (a) substrate 200, and it has a positive 200a and a back side 200b; (b) two semiconductor chips 211,212, it is placed on the positive 200a of substrate 200 with stack manner; And (c) electrical insulation layer 220, it is formed on the back side 200b of substrate 200, in order to as a bottom weld pad cover curtain.
Above-mentioned package semiconductor device not as yet adopts the set of molds identical with aforesaid Figure 1A those shown to carry out a packing colloid manufacture process, therefore will be not it not be done the explanation that repeats in this.Yet because this bottom framework of substrate-type semiconductor device that piles up twin-core sheet bonding wire type is roughly similar in appearance to the single-chip bonding wire N-type semiconductor N device shown in aforesaid Figure 1A, so it also has aforesaid excessive glue problem.
Shown in Fig. 2 B, after the packing colloid manufacture process is finished, can form a packing colloid 250, in order to coat substrate 200 and semiconductor chip 211,212.But because can there be some residual excessive glue 250a in above-mentioned excessive glue problem on the surrounding edge of the exposing surface of the electrical insulation layer 220 of bottom.
Fig. 3 A to 3B is a cross-sectional view, wherein shows a known inversion chip-shaped (flipchip) semiconductor device packing method; And this method for packing also has aforesaid excessive glue problem.
As shown in Figure 3A, the composition member of the semiconductor device of this kind pattern comprises: (a) substrate 300, and it has a positive 300a and a back side 300b; (b) the semiconductor chip 310, and it is with inverted covering on the positive 300a that crystal type is placed in substrate 300; And (c) electrical insulation layer 320, it is formed on the back side 300b of substrate 300, in order to as a bottom weld pad cover curtain.
Above-mentioned package semiconductor device not as yet adopts the set of molds identical with aforesaid Figure 1A those shown to carry out a packing colloid manufacture process, therefore will be not it not be done the explanation that repeats in this.Yet because this is inverted chip-shaped bottom framework roughly similar in appearance to piling up twin-core sheet bonding wire type shown in the single-chip bonding wire type shown in aforesaid Figure 1A and Fig. 2 A, so it also has aforesaid excessive glue problem.
Shown in Fig. 3 B, after the packing colloid manufacture process is finished, can form a packing colloid 350, in order to coat substrate 300 and semiconductor chip 310.But because can there be some residual excessive glue 350a in above-mentioned excessive glue problem on the surrounding edge of the exposing surface of the electrical insulation layer 320 of bottom.
The excessive glue phenomenon of above-mentioned three kinds of semiconductor devices all betides the below of its substrate.Yet, the top that the substrate of some semiconductor device also may take place the excessive glue phenomenon of this kind, the described ball grid array type semiconductor device of for example following Fig. 4 A to 4C.
Fig. 4 A to 4C is a cross-sectional view, wherein shows known ball grid array type (BallGrid Array, BGA) semiconductor device packing method; And this method for packing also has aforesaid excessive glue problem.
Please at first consult Fig. 4 A, the composition member of the semiconductor device of this kind pattern comprises: (a) substrate 400, and it has a positive 400a and a back side 400b; (b) the semiconductor chip 410, and it is placed on the positive 400a of substrate 400; (c) one first electrical insulation layer 421, it is formed on the positive 400a of substrate 400, in order to as a top weld pad cover curtain; (d) one second electrical insulation layer 422, it is formed on the back side 400b of substrate 400, in order to as a bottom weld pad cover curtain; And (e) a plurality of solder ball pads (solder-ball pads) 430, it is formed at the back side 400b of substrate 400, and by second electrical insulation layer 422 and mutual electrical isolation.
The above-mentioned ball grid array type semiconductor device that does not encapsulate as yet adopts a special set of molds 440 to carry out the packing colloid manufacture process.This set of molds 440 comprises a bed die 441 and a mold 442; Wherein bed die 441 has a smooth upper surface 441a, and mold 442 then has a predetermined die cavity 442a and a smooth lower surface 442b.
See also Fig. 4 B, then promptly carry out a packing colloid manufacture process, wherein the ball grid array type semiconductor device that does not encapsulate as yet shown in Fig. 4 A is placed on the certain position of set of molds 440, make second electrical insulation layer 422 on the back side 400b of substrate 400 be placed on the flat surfaces 441a of bed die 441, and make semiconductor chip 410 be arranged in the die cavity 442a of mold 442.Can for example be epoxy resin then, be injected into via the passage shown in the arrow M among the die cavity 442a, form a packing colloid 450 therefrom, in order to coat semiconductor chip 410 and substrate 400 a colloid encapsulating material.
Yet, owing to also can't reach bubble-tight pressing between the lower surface 442b of first electrical insulation layer 421 and mold 442, therefore still have an extremely narrow and small slit (as locating of the S indication among Fig. 4 B) between the two, make an a spot of encapsulating material can infiltrate so far among the S of slit, that is on the surface of excessive glue to the first electrical insulation layer 421.
Please then consult Fig. 4 C, after the packing colloid manufacture process was finished, the ball grid array type semiconductor device that can will finish encapsulation took out in set of molds 440.But, make made encapsulation unit have not good outward appearance because therefore above-mentioned excessive glue problem has some residual excessive glue 450a and be covered on the surface of first electrical insulation layer 421.
Relevant patented technology for example comprises United States Patent (USP) the 6th, 040, No. 622.This patented technology has been described a kind of multimedia circuit card (multi-media card, MMC) method for packing of used substrate-type semiconductor device.Yet the shortcoming of this patented technology is packing colloid manufacture process wherein and still can produces aforesaid excessive glue phenomenon.
The shortcoming of known technology in view of the above, main purpose of the present invention is to provide a kind of substrate-type semiconductor device packing method, and it can prevent aforesaid excessive glue phenomenon, so that the encapsulation unit of making has clean outward appearance.
Another object of the present invention is to provide a kind of substrate-type semiconductor device packing method, it can prevent aforesaid excessive glue phenomenon, influences it so that the electric connection pad that exposes is not covered by residual excessive glue can and electrically connect effect.According to above-described purpose, the present invention promptly provides a kind of substrate-type semiconductor device packing method of novelty.
A kind of substrate-type semiconductor device packing method, it is applicable to encapsulation one substrate-type semiconductor device; This substrate-type semiconductor device comprises that a substrate, at least one semiconductor chip are placed in this substrate and at least one electrical insulation layer is formed on the surface of this substrate;
This substrate-type semiconductor device packing method comprises following steps:
(1) a prefabricated set of molds, it has a predetermined die cavity;
(2) form on the ad-hoc location of hollow sectors in this electrical insulation layer that extends; This ad-hoc location is during for the certain position of this substrate-type semiconductor device in being fixed in this set of molds, the entity part of this electrical insulation layer, this set of molds, and the die cavity three of this set of molds between the locating of intersection; And this hollow sectors has a predetermined height and a width;
(3) this substrate-type semiconductor device is fixed in the die cavity of this set of molds; Wherein this hollow sectors is convenient to act as between the entity part of this substrate and this set of molds the fluid passage of a stricturization; And
(4) a colloid encapsulating material is injected among the die cavity of this set of molds, uses forming a packing colloid, in order to coat this substrate-type semiconductor device; Wherein this colloid encapsulating material is when flowing into the defined stricturization of this hollow sectors fluid passage, and its flow velocity will be slowed down and be difficult for overflow to the pressing gap between this electrical insulation layer and this set of molds, therefore prevents the glue phenomenon of overflowing.
A kind of substrate-type semiconductor device packing method, it is applicable to encapsulation one substrate-type semiconductor device; This substrate-type semiconductor device comprises that a substrate, at least one semiconductor chip are placed on the top surface of this substrate and an electrical insulation layer is formed on the lower surface of this substrate;
This substrate-type semiconductor device packing method comprises following steps:
(1) a prefabricated set of molds, it has a predetermined die cavity;
(2) form a stepped hollow sectors of extending on the surrounding edge of this electrical insulation layer; And this stepped hollow sectors has a predetermined height and a width;
(3) this substrate-type semiconductor device is fixed in the die cavity of this set of molds; Wherein this stepped hollow sectors is convenient to act as between this substrate and this set of molds fluid passage of a stricturization; And
(4) a colloid encapsulating material is injected among the die cavity of this set of molds, uses forming a packing colloid, in order to coat this substrate-type semiconductor device; Wherein this colloid encapsulating material is when flowing into the defined stricturization of this stepped hollow sectors fluid passage, its flow velocity will be slowed down and will be difficult for overflow to this electrical insulation layer and this set of molds pressing gap between the two, therefore prevent the glue phenomenon of overflowing.
A kind of substrate-type semiconductor device packing method, it is applicable to encapsulation one substrate-type semiconductor device; This substrate-type semiconductor device comprises that a substrate, at least one electrical insulation layer are formed on the top surface of this substrate and at least one semiconductor chip is placed on this electrical insulation layer;
This substrate-type semiconductor device packing method comprises following steps:
(1) a prefabricated set of molds, it has a predetermined die cavity;
(2) form on the ad-hoc location of channel form hollow sectors in this electrical insulation layer that extends; This ad-hoc location is during for the certain position of this substrate-type semiconductor device in being fixed in this set of molds, the entity part of this electrical insulation layer, this set of molds, and the die cavity three of this set of molds between the locating of intersection; And this channel form hollow sectors has a predetermined height and a width;
(3) this substrate-type semiconductor device is fixed in the die cavity of this set of molds; Wherein this channel form hollow sectors is convenient to act as between the entity part of this substrate and this set of molds the fluid passage of a stricturization; And
(4) a colloid encapsulating material is injected among the die cavity of this set of molds, uses forming a packing colloid, in order to coat this substrate-type semiconductor device; Wherein this colloid encapsulating material is when flowing into the defined stricturization of this channel form hollow sectors fluid passage, its flow velocity will be slowed down and will be difficult for overflow to this electrical insulation layer and this set of molds pressing gap between the two, therefore prevent the glue phenomenon of overflowing.
The characteristics of substrate-type semiconductor device packing method of the present invention are to form on the ad-hoc location in the electrical insulation layer of hollow sectors on substrate surface that extends; This ad-hoc location is this substrate-type semiconductor device when being fixed in certain position in the mould, electrical insulation layer wherein, the entity part of mould, and the die cavity three of mould between the locating of intersection.
In the packing colloid manufacture process, because this hollow sectors promptly is equivalent to the fluid passage of a stricturization, make that flowing into the colloid encapsulating material of hollow sectors so far can absorb heat in the mould more quickly, and make its viscosity become big and slow down its flow velocity; Therefore make the colloid encapsulating material be difficult for and then overflow is gone among the pressing gap between electrical insulation layer and the mould, that is be not easy to produce the glue phenomenon of overflowing on the exposing surface of electrical insulation layer.
Essence technology contents of the present invention and embodiment have been described in detail with graphic mode and have been drawn among this Figure of description.These graphic content Descriptions are as follows:
Figure 1A to 1C (known technology) is a cross-sectional view, wherein shows a known single-chip bonding wire type substrate-type semiconductor device packing method;
Fig. 2 A to 2B (known technology) is a cross-sectional view, wherein shows a known twin-core sheet bonding wire type substrate-type semiconductor device packing method that piles up;
Fig. 3 A to 3B (known technology) is a cross-sectional view, wherein shows a known inversion chip type semi-conductor device method for packing;
Fig. 4 A to 4C (known technology) is a cross-sectional view, wherein shows a known ball grid array type semiconductor device packing method;
Fig. 5 A to 5C is a cross-sectional view, wherein shows first embodiment of substrate-type semiconductor device packing method of the present invention;
Fig. 6 A to 6B is a cross-sectional view, wherein shows second embodiment of substrate-type semiconductor device packing method of the present invention;
Fig. 7 A to 7B is a cross-sectional view, wherein shows the 3rd embodiment of substrate-type semiconductor device packing method of the present invention;
Fig. 8 A to 8C is a cross-sectional view, wherein shows the 4th embodiment of substrate-type semiconductor device packing method of the present invention.
The drawing reference numeral explanation
The top surface of 100 substrate 100a substrates 100
121 first electrical insulation layers (weld pad cover curtain)
122 second electrical insulation layers (weld pad cover curtain)
Stepped hollow sectors 130 electric connection pads of 122a
140 set of molds, 141 bed dies
142a die cavity 150 packing colloids
Residual excessive glue 200 substrates of 150a
The lower surface of the top surface 200b substrate 200 of 200a substrate 200
211 first semiconductor chips, 212 second semiconductor chips
220 electrical insulation layers (weld pad cover curtain) the stepped hollow sectors of 220a
The residual excessive glue of 250 packing colloid 250a
The top surface of 300 substrate 300a substrates 300
320 electrical insulation layers (weld pad cover curtain) the stepped hollow sectors of 320a
The residual excessive glue of 350 packing colloid 350a
The top surface of 400 substrate 400a substrates 400
421 first electrical insulation layers (weld pad cover curtain)
421a channel form hollow sectors
422 second electrical insulation layers (weld pad cover curtain)
430 solder ball pads, 440 set of molds
The upper surface of 441 bed die 441a bed dies 441
442 mold 442a die cavitys
The residual excessive glue of 450a
Below be Fig. 5 A to 5C, Fig. 6 A to 6B, Fig. 7 A to 7B and Fig. 8 A to 8C of conjunction with figs., describe the embodiment that explanation the present invention is applied to encapsulate the substrate-type semiconductor device of various different types respectively in detail.
Be Fig. 5 A to 5C of conjunction with figs. below first embodiment (Fig. 5 A to 5C), describe the explanation first embodiment of the present invention in detail.This embodiment also is the substrate-type semiconductor device that is applied to encapsulate a single-chip bonding wire type, but can prevent the excessive glue problem in the known technology shown in Figure 1A to 1C.Among Fig. 5 A to 5C and Figure 1A to 1C, identical member indicates with identical label.
Please at first consult Fig. 5 A, the composition member of the substrate-type semiconductor device of this single-chip bonding wire type comprises: (a) substrate 100, and it has a positive 100a and a back side 100b; (b) the semiconductor chip 110, and it is placed in the positive 100a top of substrate 100; (c) one first electrical insulation layer 121, it is formed on the positive 100a of substrate 100, in order to as a top weld pad cover curtain (solder mask, S/M); (d) one second electrical insulation layer 122, it is formed on the back side 100b of substrate 100, in order to as a bottom weld pad cover curtain; And (e) a plurality of electric connection pads 130, it is arranged on the back side 100b of substrate 100, and by second electrical insulation layer 122 and mutual electrical isolation.
Key technology main points of the present invention promptly are to form a stepped hollow sectors 122a on the surrounding edge of second electrical insulation layer 122 of bottom, and make this stepped hollow sectors 122a have a predetermined height H and a width W.Basically, the height H of this stepped hollow sectors 122a must be roughly between 0.01mm and 0.05mm, and the best is 0.03mm, and width W must be roughly between 0.4mm and 1.2mm, but the best is 0.6mm.
Above-mentioned as yet not package semiconductor device adopt a special set of molds 140 to carry out the packing colloid manufacture process.This set of molds 140 comprises a bed die 141 and a mold 142; Wherein bed die 141 has a smooth upper surface 141a, and mold 142 then has a predetermined die cavity 142a.See also Fig. 5 B, then promptly carry out a packing colloid manufacture process, wherein with shown in Fig. 5 A as yet not package semiconductor device be placed on the certain position of set of molds 140, second electrical insulation layer 122 that also is about to the bottom is placed on the flat surfaces 141a of bed die 141, and mold 142 is pressed on the top of bed die 141, and make semiconductor chip 110 be arranged in the die cavity 142a of mold 142.Can for example be epoxy resin then, be injected into via the passage of arrow M indication among the die cavity 142a, form a packing colloid 150 therefrom, in order to coat semiconductor chip 110 and substrate 100 a colloid encapsulating material.
In above-mentioned packing colloid manufacture process, because stepped hollow sectors 122a promptly is equivalent to the fluid passage of a stricturization, the feasible inflow so far colloid encapsulating material of stepped hollow sectors 122a can absorb heat in the bed die 141 more quickly, and makes its viscosity become big and slow down its flow velocity; Therefore make the colloid encapsulating material be difficult for and then overflow is gone among the pressing gap between second electrical insulation layer 122 and the bed die 141, that is be not easy to produce on second electrical insulation layer 122 and the electric connection pad 130 excessive glue phenomenon.
Please then consult Fig. 5 C, after the packing colloid manufacture process is finished, can will finish package semiconductor device and in set of molds 140, take out.Than the known technology shown in Figure 1A to 1C, can not have residual excessive glue on second electrical insulation layer 122 bottom the present invention can make and the electric connection pad 130; Therefore can make made encapsulation unit have clean outward appearance, and make electric connection pad 130 can guarantee that it electrically connects effect simultaneously.
Below be Fig. 6 A to 6B of conjunction with figs., describe the explanation second embodiment of the present invention in detail.This embodiment is applied to encapsulate one to pile up the substrate-type semiconductor device of twin-core sheet bonding wire type, but can prevent the excessive glue problem in the known technology shown in Fig. 2 A to 2B.Among Fig. 6 A to 6B and Fig. 2 A to 2B, identical member indicates with identical label.
As shown in Figure 6A, this composition member that piles up twin-core sheet bonding wire type substrate-type semiconductor device comprises: (a) substrate 200, and it has a positive 200a and a back side 200b; (b) two semiconductor chips 211,212, it is placed on the positive 200a of substrate 200 with stack manner; And (c) electrical insulation layer 220, it is formed on the back side 200b of substrate 200, in order to as a bottom weld pad cover curtain.
Key technology main points of the present invention promptly are to form a stepped hollow sectors 220a on the surrounding edge of the electrical insulation layer 220 of bottom; And this stepped hollow sectors 220a has a predetermined height H and a width W.Basically, the height H of this stepped hollow sectors 220a must be roughly between 0.01mm and 0.05mm, and the best is 0.03mm, and width W must be roughly between 0.4mm and 1.2mm, but the best is 0.6mm.
Above-mentioned package semiconductor device not as yet adopts the set of molds identical with the embodiment shown in Fig. 5 A to 5C to carry out a packing colloid manufacture process, therefore will be not it not be done the explanation that repeats in this.In this packing colloid manufacture process, stepped hollow sectors 220a promptly is equivalent to the fluid passage of a stricturization; Therefore also can reach the anti-overflow glue effect identical with first embodiment.
Shown in Fig. 6 B, after the packing colloid manufacture process is finished, can form a packing colloid 250, in order to coat substrate 200 and semiconductor chip 211,212.But, can not have the glue phenomenon of overflowing on the exposing surface of the electrical insulation layer 220 bottom the present invention can make than the known technology shown in Fig. 2 A to 2B.
Below be Fig. 7 A to 7B of conjunction with figs., describe the explanation third embodiment of the present invention in detail.This embodiment is applied to encapsulate one to be inverted chip type semi-conductor device, but can prevent the excessive glue problem in the known technology shown in Fig. 3 A to 3B.Among Fig. 7 A to 7B and Fig. 3 A to 3B, identical member indicates with identical label.
Shown in Fig. 7 A, this composition member of being inverted chip type semi-conductor device comprises: (a) substrate 300, and it has a positive 300a and a back side 300b; (b) the semiconductor chip 310, and it is with inverted covering on the positive 300a that crystal type is placed in substrate 300; And (c) electrical insulation layer 320, it is formed on the back side 300b of substrate 300, in order to as a bottom weld pad cover curtain.
Key technology main points of the present invention promptly are to form a stepped hollow sectors 320a on the surrounding edge of the electrical insulation layer 320 of bottom; And this stepped hollow sectors 320a has a predetermined height H and a width W.Basically, the height H of this stepped hollow sectors 320a must be roughly between 0.01mm and 0.05mm, and the best is 0.03mm, and width W must be roughly between 0.4mm and 1.2mm, but the best is 0.6mm.
Above-mentioned package semiconductor device not as yet adopts the set of molds identical with the embodiment shown in Fig. 5 A to 5C to carry out a packing colloid manufacture process, therefore will be not it not be done the explanation that repeats in this.In this packing colloid manufacture process, stepped hollow sectors 320a promptly is equivalent to the fluid passage of a stricturization; Therefore also can reach the anti-overflow glue effect identical with first embodiment.
Shown in Fig. 7 B, after the packing colloid manufacture process is finished, can form a packing colloid 350, in order to coat substrate 300 and semiconductor chip 310.But, can not have the glue phenomenon of overflowing on the exposing surface of the electrical insulation layer 320 bottom the present invention can make than the known technology shown in Fig. 3 A to 3B.
Below be Fig. 8 A to 8C of conjunction with figs., describe the explanation fourth embodiment of the present invention in detail.This embodiment is applied to encapsulate a ball grid array type semiconductor device, but can prevent the excessive glue problem in the known technology shown in Fig. 4 A to 4C.In Fig. 8 A to 8C and Fig. 4 A to 4C, identical member indicates with identical label.
Please at first consult Fig. 8 A, the composition member of this ball grid array type semiconductor device comprises: (a) substrate 400, and it has a positive 400a and a back side 400b; (b) the semiconductor chip 410, and it is placed on the positive 400a of substrate 400; (c) one first electrical insulation layer 421, it is formed on the positive 400a of substrate 400, in order to as a top weld pad cover curtain; (d) one second electrical insulation layer 422, it is formed on the back side 400b of substrate 400, in order to as a bottom weld pad cover curtain; And (e) a plurality of solder ball pads (solder-ball pads) 430, it is formed at the back side 400b of substrate 400, and by second electrical insulation layer 422 and mutual electrical isolation.
The above-mentioned ball grid array type semiconductor device that does not encapsulate as yet adopts a special set of molds 440 to carry out the packing colloid manufacture process.This set of molds 440 comprises a bed die 441 and a mold 442; Wherein bed die 441 has a smooth upper surface 441a, and mold 442 then has a predetermined die cavity 442a and a smooth lower surface 442b.
Key technology main points of the present invention promptly are to form on the ad-hoc location of a channel form hollow sectors 421a in first electrical insulation layer 421; This ad-hoc location also is when package semiconductor device is not fixed on the certain position in the set of molds 440 as yet, the lower surface 442b of first electrical insulation layer 421, mold 442, and the die cavity 442a three of mold 442 between the locating of intersection.This channel form hollow sectors 421a has a predetermined height H and a width W.Basically, the height H of this channel form hollow sectors 421a must be roughly between 0.01mm and 0.05mm, and the best is 0.03mm, and width W must be roughly between 0.4mm and 1.2mm, but the best is 0.6mm.
Please then consult Fig. 8 B, then promptly carry out a packing colloid manufacture process, wherein with shown in Fig. 8 A as yet not package semiconductor device be fixed on the certain position of set of molds 440, make the lower surface 442b of mold 442 be pressed on second electrical insulation layer 422, and make semiconductor chip 410 place the die cavity 442a of mold 442.Can for example be epoxy resin then, be injected into via the passage of arrow M indication among the die cavity 442a, form a packing colloid 450 therefrom, in order to coat semiconductor chip 410 and substrate 400 a colloid encapsulating material.
In above-mentioned packing colloid manufacture process, channel form hollow sectors 421a promptly is equivalent to the fluid passage of a stricturization, the feasible inflow so far colloid encapsulating material of channel form hollow sectors 421a can absorb heat in the mold 442 more quickly, and makes its viscosity become big and slow down its flow velocity; Therefore make the colloid encapsulating material that injects be difficult for and then overflow is gone among the pressing gap between the lower surface 442b of first electrical insulation layer 421 and mold 442, that is be not easy to produce excessive glue phenomenon on the exposing surface of first electrical insulation layer 421.
Please then consult Fig. 8 C, after the packing colloid manufacture process is finished, can will finish package semiconductor device and in set of molds 440, take out.Than the known technology shown in Fig. 4 A to 4C, the present invention can make and can not have residual excessive glue on the exposing surface of first electrical insulation layer 421 at substrate top; Therefore can make made encapsulation unit have clean outward appearance.
Among several embodiment in front, the present invention system is applied to the substrate-type semiconductor device of four kinds of different types respectively.In the broadest sense, the semiconductor device that the present invention was suitable for is changed to and comprises that a substrate, at least one semiconductor chip are placed in the surface that this substrate and at least one electrical insulation layer be formed at this substrate and go up (can be top surface or lower surface), uses preventing to exist on this electrical insulation layer the glue phenomenon of overflowing.
Characteristics of the present invention are to form on the ad-hoc location in the electrical insulation layer of hollow sectors on substrate surface that extends; This ad-hoc location is this substrate-type semiconductor device when being fixed in certain position in the mould, electrical insulation layer wherein, the entity part of mould, and the die cavity three of mould between the locating of intersection.In the packing colloid manufacture process, because this hollow sectors promptly is equivalent to the fluid passage of a stricturization, make that flowing into the colloid encapsulating material of hollow sectors so far can absorb heat in the mould more quickly, and make its viscosity become big and slow down its flow velocity; Therefore make the colloid encapsulating material be difficult for and then overflow is gone among the pressing gap between electrical insulation layer and the mould, that is be not easy to produce the glue phenomenon of overflowing on the exposing surface of electrical insulation layer.
The above is preferred embodiment of the present invention only, is not in order to limit the scope of essence technology contents of the present invention.Essence technology contents of the present invention is broadly to define in the described claim.Any technology entity or method that other people are finished if be identical or be a kind of change of equivalence with the described claim definien of institute, all will be regarded as being covered by among this claim scope.
Claims (12)
1. substrate-type semiconductor device packing method, it is applicable to encapsulation one substrate-type semiconductor device; This substrate-type semiconductor device comprises that a substrate, at least one semiconductor chip are placed in this substrate and at least one electrical insulation layer is formed on the surface of this substrate;
This substrate-type semiconductor device packing method comprises following steps:
(1) a prefabricated set of molds, it has a predetermined die cavity;
(2) form on the ad-hoc location of hollow sectors in this electrical insulation layer that extends; This ad-hoc location is during for the certain position of this substrate-type semiconductor device in being fixed in this set of molds, the entity part of this electrical insulation layer, this set of molds, and the die cavity three of this set of molds between the locating of intersection; And this hollow sectors has a predetermined height and a width;
(3) this substrate-type semiconductor device is fixed in the die cavity of this set of molds; Wherein this hollow sectors is convenient to act as between the entity part of this substrate and this set of molds the fluid passage of a stricturization; And
(4) a colloid encapsulating material is injected among the die cavity of this set of molds, uses forming a packing colloid, in order to coat this substrate-type semiconductor device; Wherein this colloid encapsulating material is when flowing into the defined stricturization of this hollow sectors fluid passage, and its flow velocity will be slowed down and be difficult for overflow to the pressing gap between this electrical insulation layer and this set of molds, therefore prevents the glue phenomenon of overflowing.
2. substrate-type semiconductor device packing method as claimed in claim 1, wherein in step (2), the height of the hollow sectors in this electrical insulation layer is between 0.01mm and 0.05mm, and width then is between 0.4mm and 1.2mm.
3. substrate-type semiconductor device packing method as claimed in claim 2, wherein the height of the hollow sectors in this electrical insulation layer is 0.03mm, width is 0.6mm.
4. substrate-type semiconductor device packing method as claimed in claim 1, wherein this substrate-type semiconductor device is a single-chip bonding wire type.
5. substrate-type semiconductor device packing method as claimed in claim 1, wherein this substrate-type semiconductor device is to pile up twin-core sheet bonding wire type.
6. substrate-type semiconductor device packing method as claimed in claim 1, wherein this substrate-type semiconductor device is that an inversion is chip-shaped.
7. substrate-type semiconductor device packing method as claimed in claim 1, wherein this substrate-type semiconductor device is a ball grid array type.
8. substrate-type semiconductor device packing method as claimed in claim 1, wherein the hollow sectors of this extension is one to be positioned at the stepped hollow sectors on the surrounding edge of this electrical insulation layer.
9. substrate-type semiconductor device packing method, it is applicable to encapsulation one substrate-type semiconductor device; This substrate-type semiconductor device comprises that a substrate, at least one electrical insulation layer are formed on the top surface of this substrate and at least one semiconductor chip is placed on this electrical insulation layer;
This substrate-type semiconductor device packing method comprises following steps:
(1) a prefabricated set of molds, it has a predetermined die cavity;
(2) form on the ad-hoc location of channel form hollow sectors in this electrical insulation layer that extends; This ad-hoc location is during for the certain position of this substrate-type semiconductor device in being fixed in this set of molds, the entity part of this electrical insulation layer, this set of molds, and the die cavity three of this set of molds between the locating of intersection; And this channel form hollow sectors has a predetermined height and a width;
(3) this substrate-type semiconductor device is fixed in the die cavity of this set of molds; Wherein this channel form hollow sectors is convenient to act as between the entity part of this substrate and this set of molds the fluid passage of a stricturization; And
(4) a colloid encapsulating material is injected among the die cavity of this set of molds, uses forming a packing colloid, in order to coat this substrate-type semiconductor device; Wherein this colloid encapsulating material is when flowing into the defined stricturization of this channel form hollow sectors fluid passage, its flow velocity will be slowed down and will be difficult for overflow to this electrical insulation layer and this set of molds pressing gap between the two, therefore prevent the glue phenomenon of overflowing.
10. substrate-type semiconductor device packing method as claimed in claim 9, wherein in step (2), the height of this channel form hollow sectors is between 0.01mm and 0.05mm, and width then is between 0.4mm and 1.2mm.
11. substrate-type semiconductor device packing method as claimed in claim 10, wherein the height of this channel form hollow sectors is 0.03mm, and width is 0.6mm.
12. substrate-type semiconductor device packing method as claimed in claim 9, wherein this substrate-type semiconductor device is a ball grid array type.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB001345451A CN1163953C (en) | 2000-12-11 | 2000-12-11 | Substrate-type semiconductor device packing method without glue overflow |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB001345451A CN1163953C (en) | 2000-12-11 | 2000-12-11 | Substrate-type semiconductor device packing method without glue overflow |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1357910A CN1357910A (en) | 2002-07-10 |
| CN1163953C true CN1163953C (en) | 2004-08-25 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB001345451A Expired - Lifetime CN1163953C (en) | 2000-12-11 | 2000-12-11 | Substrate-type semiconductor device packing method without glue overflow |
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| Country | Link |
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| CN (1) | CN1163953C (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100433304C (en) * | 2004-09-07 | 2008-11-12 | 日月光半导体制造股份有限公司 | Basilar plate strip for transparent package |
| US7588999B2 (en) * | 2005-10-28 | 2009-09-15 | Semiconductor Components Industries, Llc | Method of forming a leaded molded array package |
| KR101293024B1 (en) * | 2011-11-11 | 2013-08-05 | 에스엔유 프리시젼 주식회사 | Apparatus for Manufacturing Flat panel display |
| CN103367264B (en) * | 2012-03-27 | 2016-08-31 | 南亚科技股份有限公司 | A kind of encapsulating carrier plate avoiding glue material overflow |
-
2000
- 2000-12-11 CN CNB001345451A patent/CN1163953C/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| CN1357910A (en) | 2002-07-10 |
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