CN116388758A - Sampling thermal noise elimination circuit, capacitance digital converter and Internet of things chip - Google Patents
Sampling thermal noise elimination circuit, capacitance digital converter and Internet of things chip Download PDFInfo
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/06—Continuously compensating for, or preventing, undesired influence of physical parameters
- H03M1/08—Continuously compensating for, or preventing, undesired influence of physical parameters of noise
- H03M1/089—Continuously compensating for, or preventing, undesired influence of physical parameters of noise of temperature variations
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/124—Sampling or signal conditioning arrangements specially adapted for A/D converters
- H03M1/1245—Details of sampling arrangements or methods
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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Abstract
The invention discloses a sampling thermal noise elimination circuit, a capacitance-to-digital converter and an internet of things chip, the sampling thermal noise elimination circuit comprises: the device comprises a sampling capacitor, a first-stage analog-to-digital converter, a residual amplifier and a second-stage analog-to-digital converter, wherein the sampling capacitor is used for acquiring a voltage signal corresponding to an input physical signal to be detected; the first-stage analog-to-digital converter is used for carrying out digital conversion quantization on the voltage signal acquired by the sampling capacitor; the residual voltage signal after being converted by the first-stage analog-to-digital converter and the sampling thermal noise of the first-stage analog-to-digital converter are amplified and then transmitted to the second-stage analog-to-digital converter; the second-stage analog-to-digital converter is used for carrying out digital conversion quantization on the residual voltage signal and the sampling thermal noise output by the residual amplifier; the residual amplifier only works in the process of collecting and sampling thermal noise and the process of amplifying signals through time sequence control. The invention is very suitable for circuits with smaller sampling capacitance.
Description
Technical Field
The present invention relates to the field of integrated circuits, and in particular, to a sampling thermal noise cancellation circuit, a capacitive digital converter, and an internet of things chip.
Background
In the field of internet of things (IoT) applications, capacitive sensors are integrated in large numbers in a chip to convert external physical information into digital signals. External physical information changes (acceleration, air pressure, temperature and humidity, etc.) react on the change of the Capacitance value, and the external physical information changes to a digital domain through a Capacitance-to-Digital Converter (CDC) converter to perform subsequent processing, so that high energy efficiency and high precision of the Capacitance sensor are necessary.
For capacitive sensors, sampling thermal noise kT/C is a critical factor limiting the accuracy of capacitive conversion, especially in more and more small sampling capacitance applications, where sampling thermal noise is increasingly not negligible. Fig. 1 is a simplified schematic diagram of a conventional sampling circuit of an analog-to-digital converter, as shown in fig. 1, in the sampling process of the analog-to-digital converter, an upper stage board is VCM level, and a lower stage board is an input signal. When the upper polar plate is disconnected first, all charges related to signals are stored on the capacitor, and the upper polar plate stores sampling thermal noise. Because the sampling thermal noise is inversely proportional to the size of the sampling capacitor, the larger the sampling capacitor is, the smaller the noise is, so in the prior art, in order to ensure the conversion accuracy, the capacitance-to-digital converter generally suppresses the thermal noise by adding the sampling capacitor, but adding the sampling capacitor not only increases the sampling time and the chip area, but also increases the power consumption of charging and discharging the sampling capacitor, and the method is not applicable to the application occasion of the small sampling capacitor.
Disclosure of Invention
The invention provides a sampling thermal noise elimination circuit, a capacitance-to-digital converter and an Internet of things chip, which can overcome the technical problems, so that the circuit can have high conversion precision by adopting a smaller sampling capacitance.
The invention provides a sampling thermal noise elimination circuit, comprising: the device comprises a sampling capacitor, a first-stage analog-to-digital converter, a residual amplifier and a second-stage analog-to-digital converter, wherein the sampling capacitor is used for acquiring a voltage signal corresponding to an input physical signal to be detected; the first-stage analog-to-digital converter is used for carrying out digital conversion quantization on the voltage signal acquired by the sampling capacitor; the residual voltage signal after being converted by the first-stage analog-to-digital converter and the sampling thermal noise of the first-stage analog-to-digital converter are amplified and then transmitted to the second-stage analog-to-digital converter; the second-stage analog-to-digital converter is used for carrying out digital conversion quantization on the residual voltage signal and the sampling thermal noise output by the residual amplifier; the residual amplifier only works in the process of collecting and sampling thermal noise and the process of amplifying signals through time sequence control.
The invention also provides a sampling thermal noise elimination method, which is suitable for the capacitance-to-digital converter and comprises the following steps:
in the input signal sampling stage, a first polar plate of a sampling capacitor is reset to virtual ground, a second polar plate is connected with a reference level, and a voltage signal positively correlated with an input physical signal to be detected is sampled and stored on the sampling capacitor;
in the sampling stage of sampling thermal noise, a reset switch of a first polar plate of a sampling capacitor is disconnected, and a residual amplifier is started to amplify and store the sampling thermal noise;
in the first stage of analog-to-digital conversion, the residual amplifier is disconnected, and the first stage of analog-to-digital converter carries out digital conversion quantization on the voltage signal acquired by the sampling capacitor;
and the residual amplifying stage is communicated with a closed loop of the residual amplifier, and the residual amplifier amplifies the residual voltage signal converted by the first-stage analog-to-digital converter and the sampling thermal noise of the first-stage analog-to-digital converter and transmits the amplified residual voltage signal and the sampling thermal noise to the second-stage analog-to-digital converter.
The invention also provides a capacitor digital converter which comprises the sampling thermal noise elimination circuit.
The invention also provides an internet of things chip comprising the capacitor digital converter.
The invention only works in the sampling amplifying process of sampling thermal noise and the signal amplifying process, but does not work at other times, so the power consumption of the amplifier can be greatly reduced, thereby the power consumption of the whole capacitance-digital converter is reduced, and meanwhile, the design of the noise elimination amplifier with higher gain and bandwidth can be adopted because the residual amplifier does not work in a full period. In addition, in the capacitance-to-digital conversion circuit, the variation frequency of the input signal is about kilohertz or less, which is not easy to cause the problem that the output end of the first amplifier is saturated due to noise sampling, so that the gain of the amplifier can be further increased. The method ensures conversion accuracy by eliminating sampling thermal noise instead of increasing sampling capacitance, and is very suitable for small sampling capacitance application. The sampling thermal noise elimination technology is applied to the capacitive sensor structure with low input frequency, so that the elimination effect is improved, the sampling thermal noise is eliminated more completely, and the original thermal noise precision theoretical upper limit of the capacitive sensor is broken through.
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In order to more clearly illustrate the embodiments of the present invention or the technical solutions of the prior art, the drawings that are needed in the embodiments or the description of the prior art will be briefly described below, it will be obvious that the drawings in the following description are some embodiments of the present invention, and that other drawings can be obtained according to these drawings without inventive effort to a person skilled in the art.
FIG. 1 is a simplified schematic diagram of a sampling circuit of a conventional analog-to-digital converter;
fig. 2 is a schematic circuit diagram of a capacitive-to-digital converter according to an embodiment of the present invention;
fig. 3 is a schematic diagram of a sampling thermal noise cancellation circuit according to an embodiment of the present invention;
FIG. 4 is a timing diagram of the control switches of FIG. 3;
FIG. 5 is a circuit portion related to sampling thermal noise cancellation provided by an embodiment of the present invention;
FIGS. 6a-6d show portions of circuitry associated with sampling thermal noise cancellation during different sequences;
FIG. 7 is a graph showing the average noise data of the capacitive-to-digital converter according to an embodiment of the present invention;
fig. 8 is a diagram showing the noise energy efficiency of the capacitive-to-digital converter according to the embodiment of the present invention compared with the prior art.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the present invention more apparent, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are some embodiments of the present invention, but not all embodiments of the present invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
In order to make the technical scheme of the present invention more clear, the following detailed description of the embodiments of the present invention is given with reference to the accompanying drawings.
Fig. 2 is a schematic circuit diagram of a capacitive-to-digital converter according to an embodiment of the present invention, where, as shown in fig. 2, the capacitive-to-digital converter is in a pipeline type and mainly includes a first stage ADC (S1 SAR), a second stage ADC (ADC 2), and a residual amplifier between stages, an input physical signal is sampled by a sampling capacitor at a front end to obtain an input signal Vin, and a sampling thermal noise V is also stored in the sampling capacitor n-ktc The first stage ADC of the capacitor digital converter carries out digital conversion quantization on an input signal, the process is coarse quantization, the residual signal is required to be further finely quantized after the quantization is finished, a residual amplifier is required to amplify the residual signal before the second stage ADC is finely quantized, and a digital result Dout output by the final converter is superposition of the coarse quantization result D1 of the first stage ADC and the fine quantization result D2 of the second stage ADC, and the fine quantization result is required to be divided by the amplification factor A of the residual amplifier before superposition due to residual amplification before fine quantization. The conversion and quantization result of the second-stage analog-to-digital converter is reduced by the amplification factor of the residual amplifier through the digital signal output circuit and then is overlapped with the conversion and quantization result of the first-stage analog-to-digital converter to be output, and then all the capacitance and digital conversion results are obtained.
As described above, in order to ensure conversion accuracy, the capacitive-to-digital converter employs a method of adding a sampling capacitor to suppress thermal noise, which not only brings about problems of increased sampling time and increased chip area and large power consumption, but also is not suitable for application in small sampling capacitor. In the circuit of the embodiment of the invention, in order to ensure the conversion accuracy, a method for eliminating sampling thermal noise kT/C is adopted, the power consumption and the area cost are not increased in the process of eliminating the sampling thermal noise, and meanwhile, the circuit design structure is simple. Fig. 3 is a schematic diagram of a sampling thermal noise cancellation circuit according to an embodiment of the present invention, fig. 4 is a timing diagram of each control switch in fig. 3, and fig. 5 and fig. 6a-6d are simplified views, only circuit portions related to sampling thermal noise cancellation are shown, as shown in fig. 3, the sampling thermal noise cancellation circuit according to the present embodiment is suitable for a capacitive-to-digital converter, and includes: the device comprises a sampling capacitor at the front end, a first-stage analog-to-digital converter, a residual amplifier and a second-stage analog-to-digital converter, wherein the sampling capacitor is used for acquiring a voltage signal corresponding to an input physical signal to be detected; the first-stage analog-to-digital converter is used for carrying out digital conversion quantization on the voltage signal acquired by the sampling capacitor; the residual voltage signal after being converted by the first-stage analog-to-digital converter and the sampling thermal noise of the first-stage analog-to-digital converter are amplified and then transmitted to the second-stage analog-to-digital converter; the second-stage analog-to-digital converter is used for carrying out digital conversion quantization on the residual voltage signal and the sampling thermal noise output by the residual amplifier; the residual amplifier is made to operate only in the process of collecting the sampling thermal noise and the process of amplifying the signal by the timing control as shown in fig. 4.
In order to ensure the linear amplification and gain stability of the amplifier, the residual amplifier further comprises a closed loop feedback loop, and in order to further reduce the power consumption, the output end of the residual amplifier is further provided with a relevant level shift capacitor.
In a specific application, the residue amplifier comprises: the first amplifier is used for amplifying the sampling thermal noise, storing the electric charge corresponding to the amplified sampling thermal noise on the noise elimination capacitor and amplifying the residual signal. In order to further improve the amplification gain of the residual amplifier circuit part, the residual amplifier further comprises a second amplifier connected with the noise elimination capacitor, and when the residual signal is amplified, the second amplifier starts the amplifying operation.
In a specific operation of the above circuit, the timing control shown in fig. 4 is adopted, and the circuit structures in fig. 5 correspond to different operation timing stages, respectively, as shown in fig. 6a-6b, according to the timing, whether the corresponding element circuit is connected to the circuit is controlled by the switch, wherein the black element and the connection line are structures connected to the circuit in the corresponding period, the gray element and the connection line are structures not connected to the circuit in the corresponding period, and the following detailed description is given:
during the period t0-t1, the upper polar plate of the sampling capacitor is reset to the virtual ground VCM, the lower polar plate is connected with a reference level, a charge signal positively correlated with the capacitor to be tested is established on the sampling capacitor, the rest circuit structure is reset, and the circuit structure of the circuit in the period shown in FIG. 5 is shown in FIG. 6 a.
During t1-t2, the reset switch of the upper polar plate of the sampling capacitor is firstly disconnected, at this time, the charge on the capacitor is fixed, the voltage with the same size as the sampling thermal noise is reserved at the upper polar plate, and the lower polar plate is still the reference voltage. The first amplifier A1 is activated and the noise canceling capacitor Cnc stores the charge of the sampled thermal noise amplified by A1 times, and the circuit configuration of the circuit shown in fig. 5 during this period is shown in fig. 6 b.
During the period t2-t3, the whole residual amplifier is disconnected, and the voltage conversion quantization of the first-stage analog-to-digital converter is normally performed, and the circuit structure of the circuit shown in fig. 5 during the period is shown in fig. 6 c.
During t3-t4, the connected headroom amplifier performs closed loop headroom amplification. At this time, because there is noise charge on Cnc, and the virtual ground effect of the amplifier is still at ground at the right end of Cnc, so a sampling thermal noise is remained at the input end of the closed loop structure, and the noise signal is transferred to the second stage for quantization, and finally cancellation is achieved, and the circuit structure of the circuit in the period shown in fig. 5 is shown in fig. 6 d.
In the embodiment of the invention, as can be seen from the circuit structure during the different time sequences, the first amplifier A1 in the residual amplifier is not always started in the whole circuit operation, but only works in the sampling amplification process of sampling thermal noise and the signal amplification process, and is not started in other times, namely, a discontinuous opening mode is adopted, so that the power consumption of the amplifier can be greatly reduced, the power consumption of the whole capacitance digital converter is reduced, and meanwhile, the sampling thermal noise to be eliminated can be amplified and transmitted to the second analog-digital conversion circuit of the later stage for cancellation; since the first of the headroom amplifiers is not fully on, a higher gain and bandwidth noise cancellation amplifier design may be employed. In addition, in the capacitance-to-digital conversion circuit, the variation frequency of the input signal is about kilohertz or less, which is not easy to cause the problem that the output end of the first amplifier is saturated due to noise sampling, so that the gain of the amplifier can be further increased. In this embodiment, the thermal noise cancellation method is used to sample rather than increasing the sampling capacitance, so this method is also suitable for small sampling capacitance applications. The sampling thermal noise elimination technology is applied to the structure of the capacitive sensor with low input frequency, so that the elimination effect is improved, the sampling thermal noise is eliminated more completely, and the original upper limit of the thermal noise precision of the capacitive sensor is broken through.
The embodiment of the invention also provides a sampling thermal noise elimination method corresponding to the circuit structure, and the method comprises the following steps of corresponding to the different time sequence periods:
in the input signal sampling stage, corresponding to the period t0-t1 in fig. 4, the first polar plate of the sampling capacitor is reset to virtual ground, the second polar plate is connected with a reference level, and a voltage signal positively correlated with an input physical signal to be detected is sampled and stored on the sampling capacitor;
a sampling thermal noise sampling stage, corresponding to a period t1-t2 in fig. 4, of turning off a reset switch of a first polar plate of a sampling capacitor, and starting a residual amplifier to amplify and store the sampling thermal noise;
a first-stage analog-to-digital conversion stage, corresponding to the period t2-t3 in fig. 4, of turning off the residual amplifier, wherein the first-stage analog-to-digital converter performs digital conversion quantization on the voltage signal acquired by the sampling capacitor;
and a residual amplifying stage, corresponding to a period t3-t4 in fig. 4, of communicating with a closed loop of the residual amplifier, wherein the residual amplifier amplifies the residual voltage signal converted by the first-stage analog-to-digital converter and the sampling thermal noise of the first-stage analog-to-digital converter and transmits the amplified residual voltage signal and the sampling thermal noise to the second-stage analog-to-digital converter.
In the above method for removing sampling thermal noise, the method may further include a digital signal output stage, configured to reduce the amplification factor of the residual amplifier by the conversion quantization result of the second stage analog-to-digital converter, and output the result after superposition with the conversion quantization result of the first stage analog-to-digital converter.
The embodiment of the invention also provides a capacitance-to-digital converter, which comprises the sampling thermal noise elimination circuit in the embodiment.
The embodiment of the invention also provides an Internet of things chip which comprises the capacitor digital converter.
Fig. 7 is an average noise data test result and a spectrum chart of the capacitive-to-digital converter provided in the embodiment of the present invention, and fig. 8 is a comparison chart of noise energy efficiency of the capacitive-to-digital converter provided in the embodiment of the present invention with the prior art, as shown in fig. 7 and fig. 8, in which the embodiment of the present invention performs streaming and verification under the TSMC 22nm process. At a supply voltage of 1.1V and an operating frequency of 200kHz, the power consumption is about 4.71uW, and the energy efficiency index is 7.9fJ/conv. -step, and the conversion accuracy is 37.12aF. Under the limitation of sampling thermal noise, the theoretical precision upper limit is 51.8aF, and compared with the upper limit, the invention improves the conversion precision by about 14aF, thereby realizing the breakthrough of conversion precision. The kT/C sampling thermal noise can be practically eliminated by more than 99% in the circuit, so that the whole conversion is basically not influenced by the noise, the conversion precision is greatly improved, the system noise requirement is reduced, and the energy efficiency is further improved.
The invention can be applied to the capacitive sensors such as humidity, distance, fingerprint, pressure, acceleration and the like in the Internet of things system to perform high-precision capacitance value conversion. Compared with the current highest energy efficiency level (16 fJ/conv. -step) within 1fF conversion precision, the energy efficiency is improved by 2 times. The overall performance is in outstanding level in the capacitive sensor, meanwhile, the conversion speed is high, the precision is high, and the capacitive sensor can work under different frequencies. The average noise data and corresponding spectrograms obtained from the test are shown in fig. 7, where the noise data at 384fF input is 37.12aF. Compared with other prior art schemes, the five-pointed star shape in the figure is the noise energy efficiency performance of the invention, and the other is the noise and energy efficiency performance of various high-performance capacitance sensors in recent years, and the figure shows that the invention has high accuracy (Resolution) and very high energy efficiency (FOM).
Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present invention, and are not limiting; although the invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit of the invention.
Claims (10)
1. A sampling thermal noise cancellation circuit for a capacitive-to-digital converter, comprising: the device comprises a sampling capacitor, a first-stage analog-to-digital converter, a residual amplifier and a second-stage analog-to-digital converter, wherein the sampling capacitor is used for acquiring a voltage signal corresponding to an input physical signal to be detected; the first-stage analog-to-digital converter is used for carrying out digital conversion quantization on the voltage signal acquired by the sampling capacitor; the residual voltage signal after being converted by the first-stage analog-to-digital converter and the sampling thermal noise of the first-stage analog-to-digital converter are amplified and then transmitted to the second-stage analog-to-digital converter; the second-stage analog-to-digital converter is used for carrying out digital conversion quantization on the residual voltage signal and the sampling thermal noise output by the residual amplifier; the residual amplifier only works in the process of collecting and sampling thermal noise and the process of amplifying signals through time sequence control.
2. The circuit of claim 1, wherein the headroom amplifier comprises: the first amplifier is used for amplifying the sampling thermal noise, storing the electric charge corresponding to the amplified sampling thermal noise on the noise elimination capacitor and amplifying the residual signal.
3. The circuit of claim 2, wherein the residual amplifier further comprises a second amplifier coupled to the noise cancellation capacitor, the second amplifier being turned on for amplification during the residual signal amplification.
4. A circuit according to any of claims 1-3, wherein the margin amplifier further comprises a closed feedback loop.
5. The circuit of claim 4, wherein the headroom amplifier output is provided with an associated level shifting capacitance in a closed feedback loop.
6. The circuit of claim 1, further comprising: and the digital signal output circuit is used for reducing the conversion and quantization result of the second-stage analog-to-digital converter by the amplification factor of the residual amplifier and then superposing the conversion and quantization result of the first-stage analog-to-digital converter and outputting the result.
7. A method for sampling thermal noise cancellation for a capacitive-to-digital converter, comprising:
in the input signal sampling stage, a first polar plate of a sampling capacitor is reset to virtual ground, a second polar plate is connected with a reference level, and a voltage signal positively correlated with an input physical signal to be detected is sampled and stored on the sampling capacitor;
in the sampling stage of sampling thermal noise, a reset switch of a first polar plate of a sampling capacitor is disconnected, and a residual amplifier is started to amplify and store the sampling thermal noise;
in the first stage of analog-to-digital conversion, the residual amplifier is disconnected, and the first stage of analog-to-digital converter carries out digital conversion quantization on the voltage signal acquired by the sampling capacitor;
and the residual amplifying stage is communicated with a closed loop of the residual amplifier, and the residual amplifier amplifies the residual voltage signal converted by the first-stage analog-to-digital converter and the sampling thermal noise of the first-stage analog-to-digital converter and transmits the amplified residual voltage signal and the sampling thermal noise to the second-stage analog-to-digital converter.
8. The method as recited in claim 7, further comprising:
and in the digital signal output stage, the conversion and quantization result of the second-stage analog-to-digital converter is reduced by the amplification factor of the residual amplifier and then is overlapped with the conversion and quantization result of the first-stage analog-to-digital converter to be output.
9. A capacitive-to-digital converter comprising a sampling thermal noise cancellation circuit as claimed in any one of claims 1 to 6.
10. An internet of things chip comprising the capacitive-to-digital converter of claim 9.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN116738158A (en) * | 2023-08-11 | 2023-09-12 | 山东凌远机电科技有限公司 | Intelligent evaluation method for loss of distribution box system |
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| CN116738158A (en) * | 2023-08-11 | 2023-09-12 | 山东凌远机电科技有限公司 | Intelligent evaluation method for loss of distribution box system |
| CN116738158B (en) * | 2023-08-11 | 2023-10-24 | 山东凌远机电科技有限公司 | Intelligent evaluation method for loss of distribution box system |
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