CN116387242B - Method for processing through silicon via - Google Patents
Method for processing through silicon via Download PDFInfo
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- CN116387242B CN116387242B CN202310356953.0A CN202310356953A CN116387242B CN 116387242 B CN116387242 B CN 116387242B CN 202310356953 A CN202310356953 A CN 202310356953A CN 116387242 B CN116387242 B CN 116387242B
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- double
- silicon compound
- etching
- compound layer
- polished
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- 238000000034 method Methods 0.000 title claims abstract description 50
- 229910052710 silicon Inorganic materials 0.000 title claims abstract description 10
- 239000010703 silicon Substances 0.000 title claims abstract description 10
- 238000005530 etching Methods 0.000 claims abstract description 54
- 150000003377 silicon compounds Chemical class 0.000 claims abstract description 51
- 238000005498 polishing Methods 0.000 claims abstract description 15
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 9
- 238000003672 processing method Methods 0.000 claims abstract description 9
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 12
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 claims description 6
- 238000004518 low pressure chemical vapour deposition Methods 0.000 claims description 6
- 239000000377 silicon dioxide Substances 0.000 claims description 6
- 235000012239 silicon dioxide Nutrition 0.000 claims description 6
- 238000002360 preparation method Methods 0.000 claims description 5
- 238000004026 adhesive bonding Methods 0.000 claims description 4
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 3
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 claims description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 3
- 238000002834 transmittance Methods 0.000 abstract description 10
- 239000000463 material Substances 0.000 abstract description 6
- 241000724291 Tobacco streak virus Species 0.000 abstract description 5
- 239000004065 semiconductor Substances 0.000 abstract description 3
- 239000010410 layer Substances 0.000 description 33
- 235000012431 wafers Nutrition 0.000 description 14
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 6
- 230000009286 beneficial effect Effects 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 239000011241 protective layer Substances 0.000 description 1
- 239000002210 silicon-based material Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Mechanical Treatment Of Semiconductor (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The application relates to a through silicon via processing method, and relates to the technical field of semiconductor device materials. The method comprises the following steps: obtaining double polished sheets; generating a silicon compound layer on the surface of the double polished piece; preparing a preset pattern on the first surface; etching the silicon compound layer on the first surface of the double polished wafer at a first preset depth based on a preset pattern, wherein the first preset depth is 200-300 mu m; exposing; protecting the first surface; etching on the silicon compound layer from the second surface until the double polishing is completed; and photoresist is removed from the etched double polished sheets. And in the process of TSV processing, respectively generating silicon compound layers on two opposite surfaces of the double polished surfaces, carrying out partial etching from the first surface after generating the silicon compound layers, preparing the same pattern on the second surface after etching, and starting etching from the second surface to double polishing. The process method can be used for processing TSVs on thicker materials with high light transmittance, and the bottom morphology and the top morphology are consistent after processing.
Description
Technical Field
The application relates to the technical field of semiconductor device materials, in particular to a silicon through hole processing method.
Background
Through-Silicon via (TSV) processing is a common processing method, and is often used in semiconductor device packaging links.
In the related art, the process of processing the through silicon via includes the process of etching the bottom.
However, when the process flow includes etching the bottom, the through silicon via processing is generally a low transmittance processing, and involves a thickness of 200um to 300um, and the existing processing types are mainly low transmittance or high transmittance and large size. The processing of the TSV with high light transmittance and small size is very few, and in practice, the etched bottom morphology existing in the processing of the TSV with high light transmittance and small size cannot be maintained, and the bottom morphology and the top have an excessively large phase difference.
Disclosure of Invention
The application relates to a processing method of a through silicon via, which can process on a silicon material with high light transmittance and small size and can prevent the problem of overlarge phase difference between the bottom morphology and the top after etching. The method comprises the following steps:
obtaining double polished sheets;
generating a silicon compound layer on the surface of the double polished piece;
preparing a preset pattern on the first surface of the double polished sheets;
etching the silicon compound layer on the first surface of the double polished wafer at a first preset depth based on a preset pattern, wherein the first preset depth is 200-300 mu m;
double-sided exposure is carried out on the double-polished piece so as to prepare a preset pattern on the silicon compound layer on the second surface of the double-polished piece;
protecting the first surface;
etching from the second surface on the silicon compound layer based on the preset pattern of the second surface until the double polishing is completed;
and removing photoresist from the etched double polished sheets to obtain the processed double polished sheets.
In an alternative embodiment, the silicon compound layer may be implemented as at least one of LPTEOS, PETEOS and LPSIN;
wherein:
LPTEOS indicates a method of preparation for obtaining silicon dioxide by low pressure chemical vapor deposition using an ethyl silicate source to form a silicon compound layer;
PETEOS indicates a preparation method of obtaining silicon dioxide by plasma enhanced chemical vapor deposition using an ethyl silicate source to form a silicon compound layer;
LPSIN indicates a method of preparing silicon nitride by low pressure chemical vapor deposition to form a silicon compound layer.
In an alternative embodiment, the silicon compound layer has a thickness of at least 2 μm.
In an alternative embodiment, etching at a first predetermined depth on the silicon compound layer of the first surface of the twin wafer based on a predetermined pattern comprises:
and etching the silicon compound layer on the first surface of the double polished wafer at a first preset depth by etching equipment based on the preset pattern.
In an alternative embodiment, the etching angle of the etching apparatus is not less than 80 °.
In an alternative embodiment, protecting the first surface includes:
performing gluing protection on the first surface;
or alternatively, the first and second heat exchangers may be,
and carrying out film pasting protection on the first surface.
In an alternative embodiment, etching from the second surface on the silicon compound layer to a double polish-through based on the predetermined pattern of the second surface comprises:
etching from the second surface to a second preset depth on the silicon compound layer at a first speed based on the preset pattern of the second surface;
etching is carried out at a second speed until the double polishing is completed for a moment, wherein the second speed is smaller than the first speed.
In an alternative embodiment, the thickness of the twin fling is 400 μm.
The technical scheme provided by the application has the beneficial effects that at least:
and in the process of TSV processing, respectively generating silicon compound layers on two opposite surfaces of the double polished surfaces, carrying out partial etching from the first surface after generating the silicon compound layers, preparing the same pattern on the second surface after etching, and starting etching from the second surface to double polishing. The process method can be used for processing TSVs on thicker materials with high light transmittance, and the bottom morphology and the top morphology are consistent after processing.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for the description of the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present application, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic flow chart of a TSV processing method according to an exemplary embodiment of the present application.
Fig. 2 is a flow chart illustrating another TSV processing method according to an exemplary embodiment of the present application.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the present application more apparent, the embodiments of the present application will be described in further detail with reference to the accompanying drawings.
Fig. 1 shows a schematic flow chart of a TSV processing method according to an exemplary embodiment of the present application, which includes:
and 101, obtaining double polished sheets.
In the embodiment of the application, the double polishing sheets are made of silicon. The double polishing sheet in the embodiment of the application is used as a wafer.
And 102, generating a silicon compound layer on the surface of the double polished piece.
In the embodiment of the application, the silicon compound layer is used as a mask to cover the surface of the double-polished piece. Alternatively, the silicon compound layer will cover at least two opposing surfaces of the twin fling for carrying the pattern.
Step 103, preparing a preset pattern on the first surface of the double polished wafer.
In the embodiment of the application, the preset pattern is the pattern required to be prepared by the TSV process, and corresponds to the wiring on the wafer.
And 104, etching the silicon compound layer on the first surface of the double polished wafer at a first preset depth based on the preset pattern.
In the embodiment of the application, the first preset depth is smaller than the thickness of the double polished sheets. Optionally, the first preset depth is 200 μm to 300 μm.
Step 105, double-sided exposure is performed on the double polished wafer.
After etching, in the embodiment of the application, the same preset pattern is prepared on the second surface of the double-polished surface in a double-sided exposure mode.
And 106, protecting the first surface.
The process is a process of protecting the first surface having the etched pattern and forming a protective layer.
And step 107, etching from the second surface on the silicon compound layer until the double polishing is completed on the basis of the preset pattern of the second surface.
After the etching in the previous stage is performed, etching is performed from the second surface until the double polishing sheets are penetrated.
And step 108, photoresist removing is carried out on the double polished wafers after the etching to obtain the processed double polished wafers.
The process is a process of removing the photoresist from the photoresist coating protection process shown in step 106, and obtaining a finished product.
In summary, in the method provided by the embodiment of the application, in the process of TSV processing, silicon compound layers are respectively generated on two opposite surfaces of the double polished surface, after the silicon compound layers are generated, partial etching is performed from the first surface, after etching, the same pattern is prepared on the second surface, and etching is performed from the second surface to double polishing. The process method can be used for processing TSVs on thicker materials with high light transmittance, and the bottom morphology and the top morphology are consistent after processing.
Fig. 2 is a schematic flow chart of another TSV processing method according to an exemplary embodiment of the present application, which includes:
step 201, obtaining double polished sheets.
In the embodiment of the application, the thickness of the double polished sheets is 400 mu m.
Step 202, preparing a silicon compound layer on the surface of the double polished piece.
In an embodiment of the present application, the silicon compound layer may be implemented as at least one of LPTEOS, PETEOS and LPSIN. Wherein: LPTEOS indicates a method of preparation for obtaining silicon dioxide by low pressure chemical vapor deposition using an ethyl silicate source to form a silicon compound layer; PETEOS indicates a preparation method of obtaining silicon dioxide by plasma enhanced chemical vapor deposition using an ethyl silicate source to form a silicon compound layer; LPSIN indicates a method of preparing silicon nitride by low pressure chemical vapor deposition to form a silicon compound layer.
In the above case, the silicon compound layer has a thickness of at least 2 μm.
Step 203, preparing a preset pattern on the first surface of the double polished wafer.
This process corresponds to the process shown in step 101 and will not be described in detail here.
Step 204, etching is performed on the silicon compound layer on the first surface of the double-polished wafer at a first preset depth by an etching device based on the preset pattern.
In the embodiment of the application, the etching equipment can be realized as an etching machine. The application is not limited to the number of the etching equipment. Optionally, during etching, the etching angle is not less than 80 °.
Step 205, performing double-sided exposure on the double-polished wafer to prepare a preset pattern on the silicon compound layer on the second surface of the double-polished wafer.
This process corresponds to the process shown in step 105 and will not be described in detail here.
Step 206, protecting the first surface.
In the embodiment of the application, the protection mode comprises gluing protection or film pasting protection, wherein the gluing thickness is not less than 3 mu m.
Step 207, etching is performed on the silicon compound layer from the second surface to a second predetermined depth at a first speed based on the predetermined pattern of the second surface.
And step 208, etching at a second speed until the double polishing is completed.
In an embodiment of the present application, the second speed is less than the first speed. That is, a low-speed etching mode is adopted at the end of etching, so that the possible damage probability to the double polished sheets is reduced.
And 209, removing photoresist from the etched double polished sheets by a dry method or a wet method to obtain the processed double polished sheets.
In summary, in the method provided by the embodiment of the application, in the process of TSV processing, silicon compound layers are respectively generated on two opposite surfaces of the double polished surface, after the silicon compound layers are generated, partial etching is performed from the first surface, after etching, the same pattern is prepared on the second surface, and etching is performed from the second surface to double polishing. The process method can be used for processing TSVs on thicker materials with high light transmittance, and the bottom morphology and the top morphology are consistent after processing.
The foregoing description of the preferred embodiments of the present application is not intended to be limiting, but rather is intended to cover all modifications, equivalents, alternatives, and improvements within the spirit and principles of the present application.
Claims (7)
1. A through silicon via processing method, the method comprising:
obtaining double polished sheets;
generating a silicon compound layer on the surface of the double polished piece;
preparing a preset pattern on the first surface of the double polished sheets;
etching the silicon compound layer on the first surface of the double polished wafer at a first preset depth based on the preset pattern, wherein the first preset depth is 200-300 mu m;
performing double-sided exposure on the double-polished piece to prepare the preset pattern on the silicon compound layer on the second surface of the double-polished piece;
protecting the first surface;
etching the silicon compound layer from the second surface based on the preset pattern of the second surface until the double polishing is completed;
photoresist is removed from the etched double polished sheets, and processed double polished sheets are obtained;
wherein, protect the first surface, include:
performing gluing protection on the first surface;
or alternatively, the first and second heat exchangers may be,
performing film pasting protection on the first surface;
and etching the silicon compound layer from the second surface to the double polishing moment through based on the preset pattern of the second surface, wherein the method comprises the following steps of:
etching from the second surface to a second preset depth on the silicon compound layer at a first speed based on the preset pattern of the second surface;
and etching at a second speed until the double polishing is completed, wherein the second speed is smaller than the first speed.
2. The method of claim 1, wherein the silicon compound layer is implemented as at least one of LPTEOS, PETEOS and LPSIN;
wherein:
the LPTEOS indicates a method of preparing silicon dioxide by low pressure chemical vapor deposition using an ethyl silicate source to form the silicon compound layer;
the PETEOS indicates a preparation method of obtaining silicon dioxide by plasma enhanced chemical vapor deposition using an ethyl silicate source to form the silicon compound layer;
the LPSIN indicates a method of preparing silicon nitride obtained by low pressure chemical vapor deposition to form the silicon compound layer.
3. The method of claim 2, wherein the silicon compound layer has a thickness of at least 2 μm.
4. The method of claim 1, wherein the etching at a first predetermined depth on the silicon compound layer of the first surface of the twin die based on the predetermined pattern comprises:
and etching the silicon compound layer on the first surface of the double polished wafer at a first preset depth by etching equipment based on the preset pattern.
5. The method of claim 4, wherein the etching angle of the etching apparatus is not less than 80 °.
6. The method of claim 1, wherein the photoresist stripping of the etched-through twin cast sheet to obtain a processed twin cast sheet comprises:
and removing photoresist from the etched double polished sheets by a dry method or a wet method to obtain the processed double polished sheets.
7. The method of claim 1, wherein the twin fling thickness is 400 μιη.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310356953.0A CN116387242B (en) | 2023-04-04 | 2023-04-04 | Method for processing through silicon via |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310356953.0A CN116387242B (en) | 2023-04-04 | 2023-04-04 | Method for processing through silicon via |
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| Publication Number | Publication Date |
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| CN116387242A CN116387242A (en) | 2023-07-04 |
| CN116387242B true CN116387242B (en) | 2023-12-05 |
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20130101918A (en) * | 2012-03-06 | 2013-09-16 | (주) 이피웍스 | Method for forming a through silicon via |
| CN108793064A (en) * | 2018-05-07 | 2018-11-13 | 瑞声科技(新加坡)有限公司 | The processing method of conductive structure |
| CN111834285A (en) * | 2020-07-20 | 2020-10-27 | 武汉新芯集成电路制造有限公司 | Semiconductor device and method for manufacturing the same |
| CN113053805A (en) * | 2021-03-11 | 2021-06-29 | 长鑫存储技术有限公司 | Semiconductor structure forming method and semiconductor structure |
| CN115440653A (en) * | 2022-04-02 | 2022-12-06 | 合肥本源量子计算科技有限责任公司 | Preparation method of semiconductor structure, semiconductor structure and superconducting quantum device |
-
2023
- 2023-04-04 CN CN202310356953.0A patent/CN116387242B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20130101918A (en) * | 2012-03-06 | 2013-09-16 | (주) 이피웍스 | Method for forming a through silicon via |
| CN108793064A (en) * | 2018-05-07 | 2018-11-13 | 瑞声科技(新加坡)有限公司 | The processing method of conductive structure |
| CN111834285A (en) * | 2020-07-20 | 2020-10-27 | 武汉新芯集成电路制造有限公司 | Semiconductor device and method for manufacturing the same |
| CN113053805A (en) * | 2021-03-11 | 2021-06-29 | 长鑫存储技术有限公司 | Semiconductor structure forming method and semiconductor structure |
| CN115440653A (en) * | 2022-04-02 | 2022-12-06 | 合肥本源量子计算科技有限责任公司 | Preparation method of semiconductor structure, semiconductor structure and superconducting quantum device |
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| CN116387242A (en) | 2023-07-04 |
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