KR20110080551A - Method of manufacturing semiconductor device prevented wafer warpage - Google Patents

Method of manufacturing semiconductor device prevented wafer warpage Download PDF

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KR20110080551A
KR20110080551A KR1020100000835A KR20100000835A KR20110080551A KR 20110080551 A KR20110080551 A KR 20110080551A KR 1020100000835 A KR1020100000835 A KR 1020100000835A KR 20100000835 A KR20100000835 A KR 20100000835A KR 20110080551 A KR20110080551 A KR 20110080551A
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film
thin film
wafer
semiconductor device
warpage
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KR1020100000835A
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Korean (ko)
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이민영
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주식회사 하이닉스반도체
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Publication of KR20110080551A publication Critical patent/KR20110080551A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30625—With simultaneous mechanical treatment, e.g. mechanico-chemical polishing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/31051—Planarisation of the insulating layers
    • H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
    • H01L21/31055—Planarisation of the insulating layers involving a dielectric removal step the removal being a chemical etching step, e.g. dry etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/32115—Planarisation
    • H01L21/3212—Planarisation by chemical mechanical polishing [CMP]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32134—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by liquid etching only

Abstract

The present invention is to provide a semiconductor device manufacturing method that can ensure a desired level of wafer warpage characteristics during backside polishing and at the same time prevent defocusing and chucking errors in the process, the semiconductor device manufacturing method of the present invention is a front film and a back Preparing a wafer on which a thin film is formed; Forming a dummy film (tensile stress film, eg, nitride film) on the front thin film; And removing the back side thin film, and the present invention described above uses dry etching or single side cleaning to remove the back side film or to form a dummy film on the front side of the wafer, thereby exposing the wafer by removing the back side thin film. There is an effect that can prevent the defocusing process and the chucking error of the deposition process. In addition, the present invention has the effect of predicting the required wafer warp from the physical information of the back side film deposited on the back side.

Description

Method of manufacturing semiconductor device preventing wafer warpage {METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE PREVENTED WAFER WARPAGE}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device capable of preventing wafer warpage.

Double Die Package (DDP), Quad Die Package (QDP), System In Package (SIP), Pakcage On Package (POP), Through Si Via (TSV), etc. The following thin thickness wafers are required.

To satisfy this thin thickness, the initial warpage of the wafer must be minimized before backgrinding the wafer. For example, to maintain the initial warpage of the wafer at about -150 μm or less, during chucking error and exposure processes due to excessive compressive stress in the previous process during the final warpage targeting of the wafer. This results in defocusing problems.

In recent years, as the diameter of the wafer (D) is gradually increased to 100 mm, 200 mm, and 300 mm in order to reduce the process cost, the wafer warpage increases exponentially due to the stress of the thin film deposited on the wafer front. do. Since the wafer warpage is proportional to the square of the diameter D of the wafer (D 2 ) (see Equation 1 to be described later), a 300 mm wafer compared to a 200 mm wafer is about two times larger.

Therefore, as the diameter of the wafer increases, the problem of defocusing on the exposure process or chucking error on the deposition process becomes more serious due to the wafer warpage. The chucking error is an error that slips down when the wafer on which the thin film is to be deposited is placed on a chuck such as an electrostatic chuck.

In this regard, conventionally, the wafer warpage is controlled by controlling the stress of the thin film stacked on the front surface of the wafer, but it is not easy to secure the final warpage during the process.

SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing a semiconductor device capable of preventing wafer defocusing and chucking errors in a process while ensuring desired wafer warping characteristics during backside polishing.

The semiconductor device manufacturing method of the present invention for achieving the above object comprises the steps of preparing a wafer formed with a front thin film and a rear thin film; Forming a dummy film on the front thin film; And removing the backside thin film, wherein the dummy film comprises a film having a tensile stress.

In addition, the semiconductor device manufacturing method of the present invention comprises the steps of preparing a wafer on which the front thin film and the rear thin film; And removing the rear thin film, wherein the removing the rear thin film is characterized by using reactive ion etching (RIE) or single side cleaning.

In addition, the semiconductor device manufacturing method of the present invention comprises the steps of preparing a wafer on which the front thin film and the rear thin film; Removing the rear thin film; And polishing the back side of the wafer, wherein removing the back side thin film may predict wafer warpage using the physical information of the back side thin film, and at the step of causing the predicted wafer warpage, It is characterized by removing. The physical information includes the stress, thickness, Poisson's ratio and Young's modulus of the backside film.

The present invention described above prevents the defocusing of the exposure process and the chucking error of the deposition process by removing the back film by removing the back film by using dry etching or single side cleaning or by forming a dummy film on the front surface of the wafer. It can work. Also,

In addition, the present invention has the effect of predicting the required wafer warp from the physical information of the back side film deposited on the back side.

1 is a view illustrating a wafer warpage variation and a chucking error generation interval according to a process step;
2A to 2C illustrate a method for preventing warpage of a wafer according to a first embodiment of the present invention.
3 is a view comparing the warpage of the wafer before and after back film removal.
4A and 4B illustrate a method for preventing warpage of a wafer according to a second embodiment of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings, in order to facilitate a person skilled in the art to easily carry out the technical idea of the present invention. do.

The present invention provides a method of dry etching or wet etching a thin film deposited on a wafer backside by Chemical Vapor Deposition (CVD) during a semiconductor device manufacturing process in an appropriate step. In this way, it is possible to maintain final warpage of the wafer and chip after backside polishing, and to prevent defocusing of the exposure process and chucking errors of the deposition process.

 In addition, by identifying the types of thin films deposited on the back surface of the wafer and calculating the expected warpage, it is possible to provide appropriate information on which process step the back side thin film should be removed.

1 is a view illustrating a wafer warpage variation and a chucking error generation interval according to a process step. In FIG. 1, the horizontal axis represents the process step, and the vertical axis represents the wafer warpage. For example, the process steps include before the interlayer insulating film deposition 11, after the M1C etching 12, after the metal interlayer insulating film deposition 13, after the MT2 etching 14, and before the repair mask 15. Graph P1 represents a wafer warpage change according to the prior art, and graph P2 represents a wafer warpage change according to embodiments of the present invention.

Referring to FIG. 1, chucking errors occur when the wafer warpage deviates from ˜ ± 300 μm or more (see reference numerals 16, 17, and 18).

Referring to graph P2, it can be seen that according to embodiments of the present invention, wafer warpage can be significantly reduced in each step than in the prior art.

2A to 2C illustrate a method of preventing warping of a wafer according to a first embodiment of the present invention.

As shown in FIG. 2A, various thin films are formed on the front and backsides of the wafer 101 for the semiconductor device manufacturing process. For example, a front thin film is formed on the front surface of the wafer 101. The front thin film includes various thin films constituting a semiconductor chip, and includes a first polysilicon 102, a nitride film 104A, and a second polysilicon 105A. A backside thin film is formed on the backside of the wafer 101. The backside thin film includes at least one of an oxide film, a nitride film, and polysilicon. The backside thin film includes an oxide film 103, a nitride film 104B and a second polysilicon 105B. The nitride films 104A and 104B and the second polysilicon 105A and 105B may be simultaneously formed on the front and rear surfaces of the wafer 101. The nitride films 104A and 104B include low pressure nitride films. The low pressure nitride film is a nitride film deposited using Low Pressure Chemical Vapor Deposition (LPCVD). In addition to the oxide film 103, polysilicon may be included.

Subsequently, an interlayer insulating film 106 is formed on the entire surface of the wafer 101 on which various thin films are formed. The interlayer insulating film 106 includes an oxide film.

As described above, when the interlayer insulating film 106 is formed on the entire surface of the wafer 101, the wafer warpage (H1, H1 means initial wafer warpage) is about -200 mu m. When the wafer warpage H1 has a negative value such as about −200 μm, warpage due to tension occurs. On the contrary, in the case where bending due to compression occurs, the value is positive.

If the wafer warpage is large, it means that the wafer warps a lot. Therefore, after the interlayer insulating film 106 is formed, the wafer 101 is warped much by tension.

A dummy layer is formed to alleviate warpage of the wafer.

As shown in FIG. 2B, a dummy film 107 is formed on the interlayer insulating film 106.

The dummy film 107 includes a film having a selectivity and a back side thin film removed during a subsequent wet etching process. For example, it includes a film having a selectivity with the second polysilicon 105B. Preferably, the dummy film 107 includes a nitride film. In wet etching, the nitride film has a selectivity with polysilicon. The nitride film used as the dummy film 107 is formed using plasma enhanced CVD (PECVD). By using the plasma chemical vapor deposition method, the nitride film has a tensile stress. As such, when the nitride film having the tensile stress is formed, the compressive stress can be relaxed. Accordingly, the wafer warpage is reduced as indicated by the reference 'H2'.

As shown in FIG. 2C, the backside thin film is removed. Wet etching is used to remove the back film. Wet etch includes a wet dip.

When applying the wet dip, an etchant corresponding to the remaining films on the back surface of the wafer 101 is used. For example, when removing polysilicon, a mixed solution of nitric acid and hydrofluoric acid (HNO 3 / HF) is used. When removing the nitride film, 165 ° C phosphoric acid (H 3 PO 4 @ 165 ° C) is used. When the polysilicon is removed using a mixed solution of nitric acid and hydrofluoric acid, the nitride film has a selectivity and is not removed.

First, the second polysilicon 105B on the back surface of the wafer is removed using a mixed solution of nitric acid and hydrofluoric acid. At this time, since the dummy film 107 formed on the entire surface of the wafer 101 includes a nitride film, it is not removed with a selectivity. In addition, the nitride film 104B formed on the back surface of the wafer is not removed.

Next, the nitride film 104B remaining on the back surface of the wafer is removed. The nitride film 104B is removed using 165 ° C phosphoric acid (H 3 PO 4 @ 165 ° C). When the nitride film 104B is removed, the dummy film 107 on the entire surface of the wafer is also removed at the same time. When phosphoric acid is used, the oxide film and polysilicon have a selectivity and are not removed. Therefore, the interlayer insulating film 106 and the oxide film 103 are not removed.

After the wet dip is completed, all of the nitride film is removed from the wafer backside. Most of the oxide film 103 remains on the back surface of the wafer.

When the wet dip is completed as described above, the wafer warpage is relaxed. For example, the wafer warpage H3 is about -50 mu m. Compared with the initial wafer warpage H1 of FIG. 2A, the wafer warpage is significantly reduced.

The back film is mostly made of polysilicon and low pressure nitride (LP Nitride) and has a tensile warpage of ˜160 μm with a thickness of 7000 μm.

It is known that the wafer warpage can be obtained by Equation 1.

Figure pat00001

Figure pat00002
,

Figure pat00003

Where h 0 is the warpage of the wafer, ν is the Poiison ratio, E is the Young's Modulus, t f is the thickness of the thin film, t s is the thickness of the wafer, D is the diameter of the wafer, and σ f is It shows the stress of the thin film.

The Young's modulus and Poisson's ratio are unique values already known according to the deposition and heat treatment of the thin film. When a large number of layers consisting of a single thin film are stacked on the wafer, the wafer warpage can be predicted by Equation (1).

K = 1.656 × 10 7 [dyne / cm 2 ]

The intrinsic stress of LP Nitride is about 1.1 × 10 10 [dyne / cm 2 ], and the intrinsic stress of polysilicon (after thermal cycle) is about 1 × 10 9 [dyne / cm 2 ]. The total thickness of the low pressure nitride film is about 2000 mm 3, and the total thickness of polysilicon is about ˜5,000 mm 3.

The total wafer warpage is calculated using the parameters. The wafer warpage by the low-pressure nitride film is about 133 mu m and the wafer warpage by polysilicon is about 30 mu m. Therefore, the total wafer warpage is 163 mu m.

3 is a view comparing the warpage of the wafer before and after removing the back film.

Referring to Fig. 3, the horizontal axis is the warp before removing the rear thin film, and the vertical axis is the warp after removing the rear thin film.

The wafer warpage obtained by Equation 1 is almost the same as the wafer warpage actually measured as shown in FIG. 3. Therefore, when the physical information (thickness, Poisson's ratio, stress, Young's modulus) of the backside thin film is obtained, the wafer warpage may be predicted by the backside thin film.

On the other hand, the wafer warpage after deposition of the interlayer dielectric film reaches about -200 mu m. By removing the rear thin film, the stress on the front surface of the wafer approaches 0 mu m. This ensures sufficient margin for chucking errors or defocusing in subsequent processes. Meanwhile, the factor that determines the warpage of the wafer and the chip after polishing the back side is due to the stress between the front thin film deposited on the front surface of the wafer and the wafer, regardless of the presence or absence of the rear thin film. As shown in FIG. 3, the warpage of the wafer about -160 μm in the presence of the back side thin film coincides with about 0 μm after the back side thin film removal. Therefore, when applying the first embodiment, the warpage of the wafer and the chip after the backside polishing has the same value as the backside thin film removal.

Another method of removing the backside thin film may be a Single Cleaning or Reactive Ion Etch (RIE) method.

Considering that the main materials causing the tensile warpage are nitride film and polysilicon, when wet dip is performed after the interlayer dielectric film deposition, the chucking error or defocusing problem as shown in FIG. Occurs when deviation is made.

In the first embodiment, the dummy film is formed to relax the tensile stress. In the second embodiment, the back film is removed immediately without forming the dummy film to relax the tensile stress, thereby preventing the warping of the wafer.

In the second embodiment, after the interlayer insulating layer is formed, the backside thin film is removed by dry etching or single cleaning. Accordingly, since the tensile stress on the back surface of the wafer is relaxed, improved wafer warping for each step as shown in FIG. 1 is obtained.

4A and 4B are diagrams illustrating a method of preventing warping of a wafer according to a second embodiment of the present invention. Hereinafter, for convenience of description, the wafer is turned over and described.

As shown in FIG. 4A, various thin films are formed on the front and backsides of the wafer 201 for a semiconductor device manufacturing process. For example, a front thin film is formed on the front surface of the wafer 201. The front thin film includes various thin films constituting a semiconductor chip, and includes a first polysilicon 202, a nitride film 204A, and a second polysilicon 205A. A backside thin film is formed on the backside of the wafer 201. The backside thin film includes at least one of an oxide film, a nitride film, and polysilicon. The backside thin film includes an oxide film 203, a nitride film 204B, and a second polysilicon 205B. The nitride films 204A and 204B and the second polysilicon 205A and 205B may be simultaneously formed on the front and rear surfaces of the wafer 201. The nitride films 204A and 204B include a low pressure nitride film. The low pressure nitride film is a nitride film deposited using Low Pressure Chemical Vapor Deposition (LPCVD). In addition to the oxide film 203, polysilicon may be included.

Subsequently, an interlayer insulating film 206 is formed on the entire surface of the wafer 201 on which various thin films are formed. The interlayer insulating film 206 includes an oxide film.

As described above, since the rear thin film formed on the rear surface of the wafer 201 includes the oxide film 203, the nitride film 204B, and the second polysilicon 205B, initial wafer warpage occurs due to tension. The initial wafer warpage H10 is about -200 mu m.

As shown in FIG. 4B, the backside thin film removing process 207 may be performed to remove all of the backside thin films of the wafer 201. At this time, the back film removal process 207 may include dry etching or single side cleaning.

First, dry etching includes reactive ion etching (RIE).

Reactive ion etching is performed for about 30 minutes based on CF 4 gas. This makes it possible to cleanly remove the oxide film 203, the nitride film 204B, and the second polysilicon 205B at the same time. The wafer warpage difference before and after removing the back film is about 160 μm (see FIG. 1).

Next, when applying Single Cleaning, an etchant corresponding to each component of the rear thin film should be used. For example, nitric acid (HNO 3 ) is used to remove the second polysilicon 205B. When removing the nitride film 204B, phosphoric acid (H 3 PO 4 @ 165 ° C.) at 165 ° C. is used. The oxide film 203 is removed using a BOE (Buffered Oxide Etchant) or hydrofluoric acid (HF) series.

Although the technical spirit of the present invention has been specifically recorded in accordance with the above-described preferred embodiments, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

101: wafer 102: first polysilicon
103: oxide film 104A, 104B: nitride film
105A, 105B: Second polysilicon 106: Interlayer insulating film
107 dummy film

Claims (14)

Preparing a wafer on which a front thin film and a back thin film are formed;
Forming a dummy film on the front thin film; And
Removing the rear thin film
A semiconductor device manufacturing method comprising a.
The method of claim 1,
The dummy film includes a film having a tensile stress.
The method of claim 1,
The dummy film includes a nitride film.
The method of claim 1,
The dummy film is a semiconductor device manufacturing method comprising a nitride film by the plasma chemical vapor deposition method.
The method of claim 1,
The back surface thin film includes at least one of an oxide film, polysilicon or a nitride film.
The method of claim 1,
Removing the rear thin film,
A method of manufacturing a semiconductor device that proceeds by wet etching.
Preparing a wafer on which a front thin film and a back thin film are formed; And
Removing the rear thin film
A semiconductor device manufacturing method comprising a.
The method of claim 7, wherein
Removing the rear thin film,
Method of manufacturing a semiconductor device using reactive ion etching (RIE).
The method of claim 7, wherein
The backside thin film includes at least one of an oxide film, a nitride film, and polysilicon, and the reactive ion etching uses CF 4 gas.
The method of claim 7, wherein
Removing the rear thin film,
A method for manufacturing a semiconductor device using single cleaning.
The method of claim 10,
The single side cleaning,
A semiconductor device manufacturing method using an etching agent for each component of the rear thin film.
The method of claim 10,
The rear thin film includes at least one of an oxide film, a nitride film, or polysilicon,
And removing the polysilicon using nitric acid, removing the nitride film using phosphoric acid, and removing the oxide film using BOE or hydrofluoric acid.
Preparing a wafer on which a front thin film and a back thin film are formed;
Removing the rear thin film; And
Polishing the back side of the wafer,
The removing of the backside thin film may include predicting wafer warpage using the physical information of the backside thin film, and removing the backside thin film in the step where the predicted wafer warpage causes.
Semiconductor device manufacturing method.
The method of claim 13,
Wherein said physical information includes stress, thickness, Poisson's ratio, and Young's modulus of said backside thin film.
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9978694B2 (en) 2016-09-05 2018-05-22 Samsung Electronics Co., Ltd. Semiconductor package and method of fabricating the same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9978694B2 (en) 2016-09-05 2018-05-22 Samsung Electronics Co., Ltd. Semiconductor package and method of fabricating the same

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