CN116384318A - Trigger conversion method and device based on data input end establishment time margin - Google Patents

Trigger conversion method and device based on data input end establishment time margin Download PDF

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CN116384318A
CN116384318A CN202310364560.4A CN202310364560A CN116384318A CN 116384318 A CN116384318 A CN 116384318A CN 202310364560 A CN202310364560 A CN 202310364560A CN 116384318 A CN116384318 A CN 116384318A
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trigger
setup
integrated circuit
setup time
data input
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贺彬广
吴振宇
刘必慰
胡春媚
宋睿强
梁斌
郭阳
韩雨
张沛
唐茜茜
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National University of Defense Technology
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/392—Floor-planning or layout, e.g. partitioning or placement
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/396—Clock trees
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/398—Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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Abstract

The application relates to a trigger conversion method and device based on a time margin established by a data input end. The method comprises the following steps: after the integrated circuit layout is completed, traversing the triggers in the integrated circuit to obtain the setup time timing margin of the data input end of each trigger and the setup time average value of the triggers in the integrated circuit. Setting a trigger replacement interval. The upper and lower limits of the trigger replacement interval are determined based on the established time average and a predetermined ratio. And if the setup time timing margin of the data input end of the current trigger is in the trigger replacement interval, replacing the current trigger with a high-performance trigger. A high performance trigger refers to a trigger whose setup time is less than the setup time of the current trigger. The method can reduce the area and the power consumption of the chip, thereby reducing the high-performance calculation cost.

Description

Trigger conversion method and device based on data input end establishment time margin
Technical Field
The present disclosure relates to the field of integrated circuits, and in particular, to a method and apparatus for switching flip-flops based on a time margin established at a data input.
Background
The rapid development of social informatization and artificial intelligence, supercomputers are advancing from the P-stage age to the E-stage age, the high-performance computing power of computers is called as an important basis of human productivity, and the study of Stanford university discovers that the demand of artificial intelligence for computing power is doubled every 3.4 months after 2012, the speed is superior to Moore's law (the number of transistors in a chip is doubled every 18 months), however, the energy efficiency of the chip is increasingly difficult by virtue of advanced technology bonus, the energy conservation and emission reduction requirements of carbon neutralization are increasingly severe, at present, the highest-speed computing chip of supercomputer Supercomputer Fugaku is manufactured by adopting a 7nm manufacturing technology, the peak performance is about 0.5 Eflow, the power consumption is about 30MW, and the energy efficiency ratio of double-precision floating point computing is about 16 Gflow/W. According to the electricity charge calculation of 0.6 yuan/degree, the electricity charge per year of Supercomputer Fugaku can reach 1.6 hundred million yuan. It follows that the high performance computing costs are enormous, and advanced chip design methods are urgently needed to reduce the high performance computing costs.
However, currently, the core computing part of most high-performance computing chips is a synchronous circuit, the basic structure of which comprises a transmitting trigger and a capturing trigger (namely UFF0 and UFF 1), a combinational logic (Combinational logic) and a clock tree, and the synchronous circuit works under the driving of a clock to meet the time sequence constraint establishment requirement, otherwise, the circuit has a functional failure, and when the time sequence constraint establishment violation occurs, an additional buffer and an inverter are needed to be inserted to reduce the data path delay, which increases the area and the power consumption of the chip, so that the high-performance computing cost is increased.
Disclosure of Invention
Accordingly, in view of the above-mentioned problems, it is desirable to provide a method and apparatus for switching a flip-flop based on a data input end setup time margin, which can dynamically adjust the performance of the flip-flop.
A method of trigger switching based on a data input establishing a time margin, the method comprising:
after the integrated circuit layout is completed, traversing the triggers in the integrated circuit to obtain the setup time timing margin of the data input end of each trigger and the setup time average value of the triggers in the integrated circuit.
Setting a trigger replacement interval. The upper and lower limits of the trigger replacement interval are determined based on the established time average and a predetermined ratio.
And if the setup time timing margin of the data input end of the current trigger is in the trigger replacement interval, replacing the current trigger with a high-performance trigger. A high performance trigger refers to a trigger whose setup time is less than the setup time of the current trigger.
In one embodiment, the method further comprises: after the integrated circuit is laid out through the integrated circuit development flow, traversing the triggers in the integrated circuit, constructing the setup time timing margin of the trigger data input end, and obtaining the setup time average value of the triggers in the integrated circuit.
In one embodiment, the preset ratio β is a ratio of a preset high performance trigger setup time to a current trigger setup time.
In one embodiment, the method further comprises: the trigger replacement interval is [ N, M ]]Determining the trigger by taking the negative number according to the established time average value and the preset ratioThe lower limit N of the substitution interval is avg (T setup ) Beta-1. Taking positive number according to the established time average value and preset ratio, determining that the upper limit M value of the trigger replacement interval is avg (T setup ) 1-beta. Wherein T is setup Is the setup time of the trigger.
In one embodiment, the method further comprises: and traversing the integrated circuit formed by the current trigger to obtain the power consumption data. And carrying out iterative optimization according to the power consumption data to determine the layout of the high-performance integrated circuit.
In one embodiment, the method further comprises:
setup slack＝T capture +T cycle -T setup -(T launch +T ck2q +T dp )
wherein setup slot is the setup time timing margin of the flip-flop data input, T capture To capture the delay of the clock, T cycle For clock period, T setup For the setup time of the flip-flop, T launch To delay the transmit clock, T ck2q For transmitting the delay from the clock end to the output end of the trigger, T dp Is the delay of the combinational logic.
In one embodiment, the development process of the integrated circuit includes: RTL design, logic synthesis, plug scan chain, chip layout, standard cell Placement, clock tree synthesis, routing, and area and power consumption assessment.
In one embodiment, an integrated circuit includes: flip-flops, combinational logic, and clock trees.
A trigger conversion device for establishing a time margin based on a data input, the device comprising:
and the acquisition time module is used for traversing the triggers in the integrated circuit after the layout of the integrated circuit is completed to obtain the time sequence margin of the setup time of the data input end of each trigger and the time average value of the setup time of the triggers in the integrated circuit.
And the replacement interval setting module is used for setting a trigger replacement interval. The upper and lower limits of the trigger replacement interval are determined based on the established time average and a predetermined ratio.
And the trigger replacing module is used for replacing the current trigger with the high-performance trigger if the time sequence allowance of the establishment time of the data input end of the current trigger is in the trigger replacing interval. A high performance trigger refers to a trigger whose setup time is less than the setup time of the current trigger.
In one embodiment, the high performance flip-flop is made up of very low threshold transistors, or custom designed.
According to the trigger conversion method and device based on the time margin established by the data input end, the time margin relationship between the establishment time of each trigger in the integrated circuit and the time margin established by the high-performance trigger is obtained, the time margin established by the data input end of the trigger is combined to be used as the basis for judging trigger replacement, the replacement interval of the trigger is constructed, when the time margin established by the data input end of the trigger is in the trigger replacement interval, the trigger is converted into the high-performance trigger, the power consumption data corresponding to the replaced trigger is counted, the replacement interval range of the trigger can be iterated and optimized from time to time according to the richness of computing resources, and the trigger with the lowest power consumption and the corresponding integrated circuit layout are determined, so that the high-performance integrated circuit with the lowest power consumption can be designed.
Drawings
FIG. 1 is a typical structural composition of a prior art digital circuit;
FIG. 2 is a flow chart of a method and apparatus for trigger switching based on a data input establishing a time margin in one embodiment;
FIG. 3 is a flow chart of integrated circuit development in the prior art;
FIG. 4 is an example of a capture flip-flop data input setup time timing margin in another embodiment, wherein the capture flip-flop UFF1 data input D setup time timing margin is-70 ps;
fig. 5 is a circuit after the capture flip-flop UFF1 is replaced with a high performance flip-flop in another embodiment;
FIG. 6 is an example of a capture-flip-flop data input setup time timing margin of 100ps in another embodiment, wherein the capture-flip-flop UFF1 data input D setup time timing margin is 100ps;
FIG. 7 is a flow chart illustrating a method for flip-flop transition based on a data input establishing a timing margin in one embodiment;
FIG. 8 is a block diagram of a trigger switch based on a data input establishing a time margin in one embodiment.
Detailed Description
In order to make the objects, technical solutions and advantages of the present application more apparent, the present application will be further described in detail with reference to the accompanying drawings and examples. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the present application.
The trigger conversion method based on the time margin established by the data input end can be applied to a digital integrated circuit shown in fig. 1, wherein a core computing part of the digital integrated circuit of a high-performance computer chip is a synchronous circuit, and the digital integrated circuit at least comprises a transmitting trigger UFF0, a capturing trigger UFF1, a combinational logic (Combinational logic) and a clock tree.
In one embodiment, as shown in fig. 2, a method for switching flip-flops based on a time margin established at a data input terminal is provided, and the method is applied to the digital integrated circuit in fig. 1, and is described as an example, and includes the following steps:
step 202, after the integrated circuit layout is completed, traversing the flip-flops in the integrated circuit to obtain a setup time timing margin of each flip-flop data input terminal and a setup time average value of the flip-flops in the integrated circuit.
The core computing parts of the high-performance computing chip are all digital synchronous circuits, the basic structure of which is shown in fig. 1, and the digital synchronous circuits comprise flip-flops (UFF 0 and UFF 1), combinational logic, clock trees and the like, wherein the flip-flop UFF0 is a transmitting flip-flop, and the flip-flop UFF1 is a capturing flip-flop. Specifically, as shown in FIG. 3, the layout of the digital integrated synchronous circuit is performed through the integrated circuit development flow, and the design and logic are performed according to RTLThe sequence of editing synthesis, inserting scan chain, chip layout, standard cell Placement, clock tree synthesis, wiring and area and power consumption evaluation is used for completing layout, and the time sequence constraint condition T is established launch +T ck2q +T dp ＜T capture +T cycle -T setup . In particular, the data transmitted by the transmitting flip-flop (UFF 0) is required to be stably established after a delay of a period of combinational logic (combinational logic) before the capturing clock reaches the capturing flip-flop UFF1, and additionally, the capturing clock is delayed by one clock period from the transmitting clock, so that the data can be correctly sampled by the capturing clock, and then the capturing flip-flops in the well-laid out digital synchronous circuit are traversed to obtain the establishing time T before the data reaches each capturing flip-flop setup Build setup time timing margin setup for capture trigger data input:
setup slack＝T capture +T cycle -T setup -(T launch +T ck2q +T dp )
wherein setup slot is the setup time timing margin of the flip-flop data input, T capture To capture the delay of the clock, T cycle For clock period, T setup For the setup time of the flip-flop, T launch To delay the transmit clock, T ck2q For transmitting the delay from the clock end to the output end of the trigger, T dp Is the delay of the combinational logic. Based on the number of capture triggers in the digital integrated synchronous circuit, the set-up time average avg (T setup )。
Step 204, setting a trigger replacement interval. The upper and lower limits of the trigger replacement interval are determined based on the established time average and a predetermined ratio.
The preset ratio beta is the ratio of the preset set-up time of the high-performance trigger to the set-up time of the current trigger, and the set-up time T of the high-performance trigger and the common trigger under different jump time and load conditions can be obtained through the circuit simulator spice setup Is a ratio beta of (c).
Specifically, the trigger replacement interval is [ N, M ]]Taking the negative number according to the established time average value and the preset ratio, and determining that the typical value of the lower limit N of the trigger replacement interval is avg (T setup ) Beta-1. Taking positive number according to the established time average value and preset ratio, determining the upper limit M typical value of the trigger replacement interval as avg (T setup ) 1-beta. Wherein T is setup Is the setup time of the trigger.
In step 206, if the setup time timing margin of the current trigger is within the trigger replacement interval, the current trigger is replaced with a high performance trigger. A high performance trigger refers to a trigger whose setup time is less than the setup time of the current trigger.
The high performance capture flip-flop may be composed of very low threshold transistors or may be custom designed. Specifically, for each capture trigger, judging whether the setup time timing margin setup of the data input end of the capture trigger is within a trigger replacement interval [ N, M ], if the setup time timing margin setup of the data input end of the capture trigger is within the trigger replacement interval [ N, M ], replacing the capture trigger with a high-performance trigger, otherwise, keeping unchanged. After the replacement, a digital synchronous circuit consisting of the current trigger, the combination logic and the clock tree is calculated, and the corresponding chip occupation area and power consumption data are obtained. According to the richness of the computing resources, the digital integrated synchronous circuit is subjected to iterative optimization of area and power consumption data, N and M can be finely adjusted near typical values of N and M, a trigger replacement interval [ N, M ] corresponding to a new time sequence allowance is obtained, and then a circuit design with the minimum area and power consumption is selected as a final design, so that the layout of the high-performance integrated circuit is obtained.
According to the trigger conversion method and device based on the time margin established by the data input end, the time margin relationship between the establishment time of each trigger in the integrated circuit and the time margin established by the high-performance trigger is obtained, the time margin established by the data input end of the trigger is combined to be used as the basis for judging trigger replacement, the replacement interval of the trigger is constructed, when the time margin established by the data input end of the trigger is in the trigger replacement interval, the trigger is converted into the high-performance trigger, the power consumption data corresponding to the replaced trigger is counted, the replacement interval range of the trigger can be iterated and optimized from time to time according to the richness of computing resources, and the trigger with the lowest power consumption and the corresponding integrated circuit layout are determined, so that the high-performance integrated circuit with the lowest power consumption can be designed.
For a register-to-register timing path with a negative setup time timing margin, its data path is delayed by T dp Tend to be correspondingly larger, which may cause setup time timing constraints to be unsatisfied, thus causing EDA tools to insert additional buffers and inverters at the place and route stage to reduce the data path delay T dp The additional inserted buffers and inverters increase the area and power consumption of the chip, which in turn increases the high performance computing cost. Converting capture flip-flops of such timing paths to a setup time T setup Smaller high performance capture flip-flops may make it easier to establish time-sequential constraints, which may reduce the number of additional inserted buffers and inverters, and thus the area and power consumption of the chip.
In one embodiment, after the integrated circuit is laid out through the integrated circuit development process, the flip-flops in the integrated circuit are traversed, the setup time timing margin of the flip-flop data input is constructed, and the setup time average of the flip-flops in the integrated circuit is obtained.
It is noted that for a register-to-register timing path with a negative setup time timing margin at the capture flip-flop data input, the data path delay T dp Tend to be correspondingly larger, which may cause setup time timing constraints to be unsatisfied, thus causing EDA tools to insert additional buffers and inverters at the place and route stage to reduce the data path delay T dp The additionally inserted buffers and inverters increase the chip area and power consumption, thereby increasing the high performance computation cost, and the capture flip-flops of such timing paths are replaced with the setup time T setup Smaller high performance flip-flops may make it easier to establish time timing constraints to meetIt follows that the number of extra inserted buffers and inverters can be reduced, thereby reducing the area and power consumption of the chip.
In one embodiment, the preset ratio β is a ratio of a preset high performance trigger setup time to a current trigger setup time.
It should be noted that, the setup time Tsetup of the high-performance capture trigger is smaller than that of the normal capture trigger, and the high-performance capture trigger may be formed by an extremely low threshold transistor or may be custom designed. Therefore, the high-performance capture trigger can flexibly adjust the hardware characteristics of the high-performance capture trigger according to the functional requirements of the high-performance computing chip, so that the method has wider adaptability.
In one embodiment, the trigger swap interval is [ N, M ]]Taking the negative number according to the established time average value and the preset ratio, and determining that the lower limit N value of the trigger replacement interval is avg (T setup ) Beta-1. Taking positive number according to the established time average value and preset ratio, determining that the upper limit M value of the trigger replacement interval is avg (T setup ) 1-beta. Wherein T is setup Is the setup time of the trigger.
In one embodiment, the integrated circuit of the current flip-flop is traversed to obtain the power consumption data. And carrying out iterative optimization according to the power consumption data to determine the layout of the high-performance integrated circuit.
In one of the embodiments of the present invention,
setup slack＝T capture +T cycle -T setup -(T launch +T ck2q +T dp )
wherein setup slot is the setup time timing margin of the flip-flop data input, T capture To capture the delay of the clock, T cycle For clock period, T setup For the setup time of the flip-flop, T launch To delay the transmit clock, T ck2q For transmitting the delay from the clock end to the output end of the trigger, T dp Is the delay of the combinational logic.
In one embodiment, the development process of the integrated circuit includes: RTL design, logic synthesis, plug scan chain, chip layout, standard cell Placement, clock tree synthesis, routing, and area and power consumption assessment.
In one embodiment, an integrated circuit includes: flip-flops, combinational logic, and clock trees.
It should be noted that, as shown in fig. 3, the development flow of the digital integrated synchronous circuit includes the flows of RTL design, logic synthesis, insertion scan chain, chip layout, standard cell layout, clock tree synthesis, wiring, etc. The energy consumption evaluation circuit comprises standard unit Placement, clock tree synthesis, wiring and other processes.
In another embodiment, as shown in fig. 7, a trigger conversion method flow for establishing a time timing margin based on a trigger data input terminal is added based on the existing integrated circuit development flow, and specific steps are as follows:
first, a high-performance capture trigger is prepared, the high-performance capture trigger is set up time T setup The capture trigger with smaller setup time than the common capture trigger can be formed by a very low threshold transistor or custom design. High-performance capture trigger and common capture trigger T under different jump time and load conditions obtained through circuit simulator spice setup Is a ratio beta of (c).
Step two, after the chip layout is completed, traversing the setup time timing margin of the data input end of each trigger in the design to obtain setup time timing margin setup and T of each trigger setup Average avg (T) setup )。
Third step, setting the conversion interval [ N, M ] of the capture trigger]When the time timing margin setup slot established at the capture trigger data input is located in the interval, the capture trigger is replaced with a high performance trigger. N is typically avg (T setup ) Typical values of M are avg (T setup )*(1-β)。
Fourth, for each capture trigger, judging whether the time timing margin established at the data input end of each capture trigger is within the conversion interval [ N, M ] of the capture trigger, if the time timing margin established at the data input end of the trigger is within the conversion interval [ N, M ] of the capture trigger, replacing the capture trigger with a high-performance trigger, otherwise, keeping unchanged.
And fifthly, completing the follow-up standard unit Placement, clock tree synthesis and wiring, and obtaining the area and power consumption data of the chip.
And sixthly, according to the richness of the computing resources, the N and M can be finely adjusted near the typical values of the N and M, so that a new conversion interval [ N, M ] of the capture trigger is obtained. And repeating the fourth step and the fifth step to obtain the area and power consumption data of the chip corresponding to the conversion interval [ N, M ] of each capture trigger.
And seventhly, selecting the design of the capture trigger with the minimum area and power consumption as the final design of the digital integrated synchronous circuit according to the area and power consumption data of the chip corresponding to the conversion interval [ N, M ] of each capture trigger.
It should be understood that, although the steps in the flowcharts of fig. 2, 3, and 7 are shown in order as indicated by the arrows, these steps are not necessarily performed in order as indicated by the arrows. The steps are not strictly limited to the order of execution unless explicitly recited herein, and the steps may be executed in other orders. Moreover, at least some of the steps in fig. 2, 3, 7 may include multiple sub-steps or multiple stages, which are not necessarily performed at the same time, but may be performed at different times, which are not necessarily performed sequentially, but may be performed alternately or alternately with other steps or at least a portion of the sub-steps or stages of other steps.
In one embodiment, as shown in FIG. 4, the data input of the transmitting flip-flop UFF0 needs to pass through 2 inverters and 1 AND gate to reach the next capturing flip-flop, the path is longer, the capturing flip-flop UFF1 data input establishes a timing margin of-70 ps, as shown in FIG. 5, if the transition interval [ N, M ] of the capturing flip-flop UFF1]Is [ -80ps,80ps]As the capture trigger UFF1 number is shown in fig. 3The time timing margin is established to be-70 ps according to the input end, and falls in the conversion interval [ N, M ] of the capture trigger UFF1]In, therefore, the capture flip-flop UFF1 is replaced from a normal capture flip-flop to a high-performance capture flip-flop due to the setup time T of the high-performance capture flip-flop setup The setup time is 70ps less than that of a normal capture flip-flop, and the setup time margin of the data input terminal of the high-performance capture flip-flop UFF1 becomes 0ps.
In another embodiment, as shown in fig. 6, the transmitting flip-flop UFF0 reaches the next capturing flip-flop only by passing through 1 inverter, the path is shorter, the setup time timing margin of the data input terminal of the capturing flip-flop UFF1 is 100ps, therefore, the setup time timing margin of the data input terminal of the capturing flip-flop UFF1 does not fall within the transition interval [ -80ps,80ps ] of the capturing flip-flop, so the capturing flip-flop UFF1 remains unchanged as a normal capturing flip-flop, and needs not to be replaced with a high-performance flip-flop.
In one embodiment, as shown in fig. 8, there is provided a flip-flop conversion apparatus for establishing a timing margin based on a data input terminal, comprising: acquiring an establishment time module, a replacement interval setting module and a trigger replacement module, wherein:
and the acquisition time module is used for traversing the triggers in the integrated circuit after the layout of the integrated circuit is completed to obtain the time sequence margin of the setup time of the data input end of each trigger and the time average value of the setup time of the triggers in the integrated circuit.
And the replacement interval setting module is used for setting a trigger replacement interval. The upper and lower limits of the trigger replacement interval are determined based on the established time average and a predetermined ratio.
And the trigger replacing module is used for replacing the current trigger with the high-performance trigger if the time sequence allowance of the establishment time of the data input end of the current trigger is in the trigger replacing interval. A high performance trigger refers to a trigger whose setup time is less than the setup time of the current trigger.
In one embodiment, the high performance flip-flop is made up of very low threshold transistors, or custom designed.
For a specific definition of the trigger switching device based on the data input end setup time margin, reference may be made to the definition of the trigger switching method based on the data input end setup time margin hereinabove, and the description thereof will not be repeated. The above-described respective modules in the trigger conversion apparatus for establishing a time margin based on the data input terminal may be implemented in whole or in part by software, hardware, and combinations thereof. The above modules may be embedded in hardware or may be independent of a processor in the computer device, or may be stored in software in a memory in the computer device, so that the processor may call and execute operations corresponding to the above modules.
It will be appreciated by those skilled in the art that the structure shown in fig. 8 is merely a block diagram of some of the structures associated with the present application and is not limiting of the computer device to which the present application may be applied, and that a particular computer device may include more or fewer components than shown, or may combine certain components, or have a different arrangement of components.
Those skilled in the art will appreciate that implementing all or part of the above described methods may be accomplished by way of a computer program stored on a non-transitory computer readable storage medium, which when executed, may comprise the steps of the embodiments of the methods described above. Any reference to memory, storage, database, or other medium used in the various embodiments provided herein may include non-volatile and/or volatile memory. The nonvolatile memory can include Read Only Memory (ROM), programmable ROM (PROM), electrically Programmable ROM (EPROM), electrically Erasable Programmable ROM (EEPROM), or flash memory. Volatile memory can include Random Access Memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in a variety of forms such as Static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double Data Rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous Link DRAM (SLDRAM), memory bus direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM), among others.
The technical features of the above embodiments may be arbitrarily combined, and all possible combinations of the technical features in the above embodiments are not described for brevity of description, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.
The above examples merely represent a few embodiments of the present application, which are described in more detail and are not to be construed as limiting the scope of the invention. It should be noted that it would be apparent to those skilled in the art that various modifications and improvements could be made without departing from the spirit of the present application, which would be within the scope of the present application. Accordingly, the scope of protection of the present application is to be determined by the claims appended hereto.

Claims (10)

1. A method for flip-flop transition based on a data input establishing a time margin, the method comprising:
traversing the triggers in the integrated circuit after the integrated circuit layout is completed to obtain the setup time timing margin of each trigger data input end and the setup time average value of the triggers in the integrated circuit;
setting a trigger replacement interval; the upper limit and the lower limit of the trigger replacement interval are determined according to the established time average value and a preset ratio;
if the time sequence allowance of the setup time of the data input end of the current trigger is in the trigger replacement interval, replacing the current trigger with a high-performance trigger; the high-performance trigger refers to a trigger with a trigger setup time less than the current trigger setup time.
2. The method of claim 1, wherein traversing the flip-flops in the integrated circuit after the integrated circuit layout is completed to obtain a setup time timing margin for each of the flip-flop data inputs and a setup time average for the flip-flops in the integrated circuit comprises:
after the integrated circuit is laid out through an integrated circuit development flow, traversing the trigger in the integrated circuit, constructing the setup time timing margin of the trigger data input end, and obtaining the setup time average value of the trigger in the integrated circuit.
3. The method of claim 2, wherein the predetermined ratio β is a ratio of a predetermined high performance trigger setup time to a current trigger setup time.
4. A method according to claim 3, wherein the upper and lower limits of the trigger replacement interval are determined from the set-up time average and a predetermined ratio, comprising:
the trigger replacing interval is [ N, M ]]Taking the negative number according to the established time average value and the preset ratio, and determining that the lower limit N value of the trigger replacement interval is avg (T setup ) (β -1); taking positive number according to the established time average value and the preset ratio, and determining that the upper limit M value of the trigger replacement interval is avg (T setup ) (1- β); wherein T is setup Is the setup time of the trigger.
5. The method of claim 4, wherein if the setup time timing margin of the current trigger data input is within the trigger replacement interval, replacing the current trigger with a high performance trigger, further comprising, after the step:
traversing the integrated circuit formed by the current trigger to obtain power consumption data; and performing iterative optimization according to the power consumption data to determine the layout of the high-performance integrated circuit.
6. The method of claim 5, wherein the step of constructing the setup time timing margin for the trigger data input comprises:
setup slack＝T capture +T cycle -T setup -(T launch +T ck2q +T dp )
wherein setup slot is the setup time timing margin of the flip-flop data input, T capture To capture the delay of the clock, T cycle For clock period, T setup For the setup time of the flip-flop, T launch To delay the transmit clock, T ck2q For transmitting the delay from the clock end to the output end of the trigger, T dp Is the delay of the combinational logic.
7. The method according to any one of claims 1 to 6, wherein the integrated circuit development process includes: RTL design, logic synthesis, plug scan chain, chip layout, standard cell Placement, clock tree synthesis, routing, and area and power consumption assessment.
8. The method of any of claims 1 to 6, wherein the integrated circuit comprises: flip-flops, combinational logic, and clock trees.
9. Trigger switching device for establishing a time margin based on a data input, said device comprising:
the method comprises the steps of acquiring a setup time module, wherein the setup time module is used for traversing the triggers in the integrated circuit after the layout of the integrated circuit is completed to obtain a setup time timing margin of each trigger data input end and a setup time average value of the triggers in the integrated circuit;
the replacement interval setting module is used for setting a trigger replacement interval; the upper limit and the lower limit of the trigger replacement interval are determined according to the established time average value and a preset ratio;
the trigger replacing module is used for replacing the current trigger with a high-performance trigger if the time sequence allowance of the establishment time of the data input end of the current trigger is in the trigger replacing interval; the high-performance trigger refers to a trigger with a trigger setup time less than the current trigger setup time.
10. The apparatus of claim 9, wherein the high performance flip-flop is comprised of an extremely low threshold transistor or is custom designed.
CN202310364560.4A 2023-04-06 2023-04-06 Trigger conversion method and device based on data input end establishment time margin Pending CN116384318A (en)

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