CN116381469B - Method and device for testing chip power consumption channel measurement information cross-validation - Google Patents
Method and device for testing chip power consumption channel measurement information cross-validation Download PDFInfo
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Abstract
The application relates to a chip power consumption channel measurement information cross-validation testing method and device, which relate to the technical field of chip testing, and are characterized in that q kinds of testing plaintext with different hamming weights are input into M chips to be tested with the same batch and model to execute encryption operation, and a power consumption leakage curve of each chip to be tested in operation is collected; averaging the power consumption leakage curves under the plaintext of each hamming weight test, and performing discrete fourier transform on the average power consumption leakage curve to obtain a power spectrum density curve; extracting peak characteristics of the power spectrum density curve to obtain peak power key points; the peak power key points under the plaintext of the same hamming weight test of different chips to be tested are subjected to exclusive or operation, and each chip to be tested is subjected to batch cross-validation, so that batch cross-validation based on power consumption signals is realized, and the improvement of the test efficiency is facilitated.
Description
Technical Field
The application relates to the technical field of chip testing, in particular to a method and a device for testing cross-validation of chip power consumption channel information.
Background
As the complexity of the chip is higher, more and more modules are inside the chip, the manufacturing process is more and more advanced, the corresponding failure modes are more and more, and how to test the whole chip completely and effectively, the proportion that needs to be considered in the design process is more and more.
Currently, to save cost and test time, sampling tests are generally employed to determine chip reliability and whether design goals are met. The test method cannot ensure the quality of the whole batch of chips and is easy to miss.
In view of this, the present application has been made.
Disclosure of Invention
In order to solve the technical problems, the application provides a chip power consumption channel information cross-validation testing method and device, which realize batch cross-validation based on power consumption signals and are beneficial to improving testing efficiency; and the average power consumption leakage trace is subjected to discrete Fourier transform to obtain a power spectrum density curve, the power spectrum density curve is subjected to peak characteristics, the peak characteristics are subjected to exclusive OR operation, and the testing accuracy is improved while the operand is reduced.
The application provides a chip power consumption channel information cross-validation testing method, which comprises the following steps:
s1, building a testing device and setting testing parameters;
s2, inputting q kinds of test plaintext with different hamming weights into M identical batches of chips to be tested with the same model to execute encryption operation, and collecting a power consumption leakage curve of each chip to be tested in operation;
s3, averaging the power consumption leakage curves under the plaintext of each hamming weight test to obtain an average power consumption leakage trace;
s4, performing discrete Fourier transform on the average power consumption leakage trace to obtain a power spectrum density curve;
s5, extracting peak characteristics of the power spectrum density curve to obtain peak power key points;
s6, performing exclusive OR operation on peak power key points under the same Hamming weight test plaintext of different chips to be tested, and performing batch cross verification on the chips to be tested;
wherein M, q is an integer greater than 3.
Optionally, after S4 and before S5, the method further includes: and adopting a Gaussian noise reduction algorithm to perform noise reduction pretreatment on the power spectrum density curve.
Optionally, S5 includes:
and (3) carrying out peak characteristic extraction on the power spectrum density curve by adopting a linear discriminant analysis algorithm with supervised machine learning, and extracting peak power key points corresponding to the peak weight capable of reflecting the power spectrum density information.
Optionally, the step S6 includes:
s61, performing exclusive OR operation on peak power key points of the same Hamming weight test plaintext from different chips to be tested, and if the exclusive OR result is logic 0, passing the test; if the exclusive or result is a logic 1, the test result is an error; if the exclusive or result of the peak power key point under any hamming weight test plaintext is logic 1, the test result is more error;
s62, dividing the chip to be tested with the test result of error into two equal parts, repeating the steps S2-S6, and gradually narrowing the test range until the fault chip is found out.
Optionally, the step S3 includes:
s23, controlling each chip to be tested to respectively execute the same encryption operation on each Hamming weight test plaintext (k)>20 F (f=8, 16, 32, 64) times averaging the curves corresponding to the encryption process, each curve having p points；
S24, calculating average power consumption leakage trace of each chip to be tested under the category of the hamming weight value q (q= 0,1,2,3,4,5,6,7,8):
。
optionally, the test parameters include: supply voltage, input signal timing, oscilloscope input impedance, sampling frequency, sampling count, bandwidth, time reference, and trigger mode.
The application provides a chip power consumption channel information cross-validation testing device, which comprises:
the metal contact of the test motherboard is connected with a pin of the chip to be tested;
the current probe is connected with the test motherboard and is used for sequentially transmitting the acquired signals to the oscilloscope and the test platform through the high-frequency signal wire;
the test platform is used for executing:
inputting q kinds of test plaintext with different hamming weights into M identical batches of chips to be tested with the same model to execute encryption operation, and collecting a power consumption leakage curve of each chip to be tested in operation;
averaging the power consumption leakage curves under each hamming weight test plaintext to obtain an average power consumption leakage trace;
performing discrete Fourier transform on the average power consumption leakage trace to obtain a power spectrum density curve;
extracting peak characteristics of the power spectrum density curve to obtain peak power key points;
and carrying out exclusive OR operation on peak power key points under the plaintext of the same hamming weight test of different chips to be tested, and carrying out batch cross verification on the chips to be tested.
The chip power consumption side channel information cross-validation test technology provided by the application can effectively improve the efficiency and the accuracy of chip function test when testing a large number of vehicle-standard chips of the same batch and the same model. The test of a large number of chips can be completed rapidly and accurately without much professional knowledge of operators. Further, for enterprises, the earlier the chip faults are found, the production and manufacturing cost can be reduced, and precious time is striven for design and manufacturing. By monitoring the power consumption of a chip when it is performing performance tests, its power consumption level during operation can be determined, which is important to help an enterprise determine whether the chip is suitable for mobile devices or other power consumption sensitive applications. Meanwhile, enterprises can be helped to find out chip-level safety defects, avoid safety risks and perfect product functions, and corresponding test technical methods and guarantees are provided for the development of vehicle-mounted safety chips and the rapid landing of national security technologies in the chips.
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In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings that are needed in the description of the embodiments or the prior art will be briefly described, and it is obvious that the drawings in the description below are some embodiments of the present application, and other drawings can be obtained according to the drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic flow chart of a method for testing cross-validation of chip power consumption channel measurement information according to an embodiment of the present application.
Detailed Description
In order to make the objects, technical solutions and advantages of the present application more apparent, the technical solutions of the present application will be clearly and completely described below. It will be apparent that the described embodiments are only some, but not all, embodiments of the application. All other embodiments, which can be made by one of ordinary skill in the art without undue burden from the application, are within the scope of the application.
Fig. 1 is a flowchart of a chip power consumption channel measurement information cross-validation test method according to an embodiment of the present application, including the following operations:
s1, building a testing device and setting testing parameters.
The testing device comprises a testing motherboard, a current probe, a high-frequency signal wire, a testing platform and an oscilloscope. And mounting the chip to be tested on a chip test motherboard, wherein the metal contact of the test motherboard is connected with the pin of the mounted chip to be tested. The current probe is connected with the test motherboard and is used for sequentially transmitting the acquired signals to the oscilloscope and the test platform through the high-frequency signal wire, and the test platform executes the following steps after receiving the signals:
inputting q kinds of test plaintext with different hamming weights into M identical batches of chips to be tested with the same model to execute encryption operation, and collecting a power consumption leakage curve of each chip to be tested in operation; averaging the power consumption leakage curves under each hamming weight test plaintext to obtain an average power consumption leakage trace; performing discrete Fourier transform on the average power consumption leakage trace to obtain a power spectrum density curve; extracting peak characteristics of the power spectrum density curve to obtain peak power key points; and carrying out exclusive OR operation on peak power key points under the plaintext of the same hamming weight test of different chips to be tested, and carrying out batch cross verification on the chips to be tested.
And setting test parameters of the chip to be tested on the test platform. Such as supply voltage, input signal timing, oscilloscope input impedance, sampling frequency, number of samples, bandwidth, time reference, trigger mode, etc.
And supplying power to the chip to be tested, and starting to collect the power consumption leakage curve after waiting for a period of time.
S2, inputting q kinds of test plaintext with different hamming weights into M identical batches of chips to be tested in the same model to execute encryption operation, and collecting power consumption leakage curves of each chip to be tested in operation. Wherein M, q is an integer greater than 3.
Based on the hamming weight model, an input test plaintext of the chip to be tested is set. The first 8 bits of the plaintext to be encrypted are respectively set as follows: 00000000, 00000001, 00000011, 00000111, 00001111, 00011111, 00111111, 01111111, 11111111. Namely, the hamming weights corresponding to the first byte of the 9 groups of plaintext are respectively: 0. 1,2,3,4,5,6,7,8, 9 hamming weight categories total.
M (M is the maximum value of the number of chips which can be accommodated by the test system) chips with the same batch and the same model are placed in the device, and the function test is executed. The test system inputs 9 groups of plaintext into chips to be tested according to the user setting and the sequence to execute encryption operation, acquires the power consumption leakage curve of each chip in operation through a current probe, and transmits the power consumption leakage curve to a test platform to wait for subsequent analysis; the power consumption leakage curve is displayed on an oscilloscope.
The principle of chip cross-validation based on power consumption is: in the process of executing the same password operation instruction by the chip, the power consumption radiation leakage depends on the Hamming weight of the data processed in the chip, the data with the same Hamming weight value can generate almost the same power consumption radiation leakage, and the data with different Hamming weight values can generate obviously different power consumption radiation leakage.
And S3, averaging the power consumption leakage curves under the plaintext of each Hamming weight test to obtain an average power consumption leakage trace.
S33、Controlling each chip to be tested to respectively execute the same encryption operation on each hamming weight test plaintext>20 F (f=8, 16, 32, 64) times averaging the curves corresponding to the encryption process, each curve having p points；
Averaging F times can improve the signal to noise ratio. The processed 9 groups of hamming weight data can cause obvious difference of corresponding operation time on the electromagnetic radiation curves, and the corresponding average electromagnetic radiation curves also have obvious difference, wherein the difference of the average electromagnetic radiation curves of any two of the 9 categories is not 0.
S34, calculating average power consumption leakage trace of each chip to be tested under the category of the hamming weight value q (q= 0,1,2,3,4,5,6,7,8):
the upper computer/test platform reads the calculated average curve from the oscilloscope, and the related calculation parameters can be directly set in the oscilloscope parameters to automatically calculate the average so as to reduce errors. Such as an average of 8/16/32/64 times.
S4, performing discrete Fourier transform on the average power consumption leakage trace to obtain a power spectrum density curve.
And performing discrete Fourier transform on the average power consumption leakage trace. The Parseval theorem is adopted, the discrete Fourier transform of the finite sequence is orthogonal transform, the Parseval energy conservation theorem is satisfied, and the energy of the sequence in the time domain is equal to the energy of the transform domain. Therefore, the frequency composition of the signal and the component size of each frequency can be more intuitively reflected on the frequency domain through the Fourier transform.
And (5) solving a power spectrum density curve of the result after the fast Fourier transform. The time difference of the signals in the time domain is embodied as a difference in phase in the frequency domain. And in the process of converting the time domain signal into the frequency domain signal by utilizing the fast Fourier transform and simultaneously solving the power spectrum density of the frequency domain signal, the phase difference is eliminated, thereby realizing the alignment of the signals.
Optionally, a Gaussian noise reduction algorithm is adopted to perform noise reduction pretreatment on the power spectrum density curve, so that the signal to noise ratio is improved.
S5, extracting peak characteristics of the power spectrum density curve to obtain peak power key points.
And (3) carrying out peak feature extraction on the power spectrum density curve by adopting a Linear Discriminant Analysis (LDA) algorithm with supervised machine learning so as to reduce the number of features and extract peak power key points corresponding to the peak weight capable of reflecting the power spectrum density information. The method comprises the following specific steps:
(1) Inputting a data set, in particular a power spectrum density curve; (2) Extracting an independent variable and a dependent variable, wherein the independent variable is frequency, and the dependent variable is the size of a component corresponding to each frequency; (3) partitioning the training set and the test set, in this example at 8:2, dividing the ratio of the two parts; (4) Establishing a model, and introducing a linear discriminant analysis function into python to perform data dimension reduction; (5) Fitting and converting data, performing fitting and conversion on input data, and obtaining an output sample set; (6) evaluating the model.
S6, performing exclusive OR operation on peak power key points under the same Hamming weight test plaintext of different chips to be tested, and performing batch cross verification on the chips to be tested.
S61, performing exclusive OR operation on peak power key points of the same Hamming weight test plaintext from different chips to be tested, and if the exclusive OR result is logic 0, passing the test; if the exclusive or result is a logic 1, the test result is an error; if the exclusive or result of the peak power key point under any hamming weight test plaintext is logic 1, the test result is more error; s62, dividing the chip to be tested with the test result of error into two equal parts, and repeating the steps S2-S6 in parallel for the two equal parts of chips to be tested, so as to gradually reduce the test range until the fault chip is found out.
Specifically, after feature extraction, the M chips to be tested obtain peak power key points corresponding to 9M power spectrum density curves. And performing exclusive OR operation on peak power key points corresponding to the power spectrum density curves from different chips and the same hamming weight model in a cross verification module.
The exclusive or operation refers to the output result of any two chips to be tested when executing the internal algorithm, and the exclusive or operation is carried out one by one according to the sequence. The exclusive OR principle is as follows:
0 ^ 0 = 0 ,
0 ^ 1 = 1,
1 ^ 0 = 1 ,
1 ^ 1 = 0 ,
stopping the exclusive or operation when the bitwise exclusive or result first appears 1, and considering at least one of the two chips to be detected as abnormal, and recording the detection result as error; if the exclusive or result is 0, the two chips to be tested pass the test.
And all chips to be tested pass through the test system, and then the test is finished.
The application realizes batch cross verification based on the power consumption signals, and is beneficial to improving the test efficiency; moreover, the average power consumption leakage trace is subjected to discrete Fourier transform to obtain a power spectrum density curve, the peak characteristic is carried out on the power spectrum density curve, and the power consumption characteristic is accurately expressed by using smaller data volume; the peak value characteristics are subjected to exclusive OR operation, so that the operation quantity is reduced, and meanwhile, the test accuracy is improved.
It is noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of the present application. As used in this specification, the terms "a," "an," "the," and/or "the" are not intended to be limiting, but rather are to be construed as covering the singular and the plural, unless the context clearly dictates otherwise. The terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method or apparatus comprising such elements.
It should also be noted that the positional or positional relationship indicated by the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. are based on the positional or positional relationship shown in the drawings, are merely for convenience of describing the present application and simplifying the description, and do not indicate or imply that the apparatus or element in question must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as limiting the present application. Unless specifically stated or limited otherwise, the terms "mounted," "connected," and the like are to be construed broadly and may be, for example, fixedly connected, detachably connected, or integrally connected; can be mechanically or electrically connected; can be directly connected or indirectly connected through an intermediate medium, and can be communication between two elements. The specific meaning of the above terms in the present application will be understood in specific cases by those of ordinary skill in the art.
Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present application, and not for limiting the same; although the application has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some or all of the technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the essence of the corresponding technical solutions from the technical solutions of the embodiments of the present application.
Claims (7)
1. The method for testing the cross-validation of the chip power consumption channel measurement information is characterized by comprising the following steps of:
s1, building a testing device and setting testing parameters;
s2, inputting q kinds of test plaintext with different hamming weights into M identical batches of chips to be tested with the same model to execute encryption operation, and collecting a power consumption leakage curve of each chip to be tested in operation;
s3, averaging the power consumption leakage curves under the plaintext of each hamming weight test to obtain an average power consumption leakage trace;
s4, performing discrete Fourier transform on the average power consumption leakage trace to obtain a power spectrum density curve;
s5, extracting peak characteristics of the power spectrum density curve to obtain peak power key points;
s6, performing exclusive OR operation on peak power key points under the same Hamming weight test plaintext of different chips to be tested, and performing batch cross verification on the chips to be tested;
wherein M, q is an integer greater than 3.
2. The method of claim 1, further comprising, after S4 and before S5: and adopting a Gaussian noise reduction algorithm to perform noise reduction pretreatment on the power spectrum density curve.
3. The method of claim 1, wherein S5 comprises:
and (3) carrying out peak characteristic extraction on the power spectrum density curve by adopting a linear discriminant analysis algorithm with supervised machine learning, and extracting peak power key points corresponding to the peak weight capable of reflecting the power spectrum density information.
4. The method according to claim 1, wherein S6 comprises:
s61, performing exclusive OR operation on peak power key points of the same Hamming weight test plaintext from different chips to be tested, and if the exclusive OR result is logic 0, passing the test; if the exclusive or result is a logic 1, the test result is an error; if the exclusive or result of the peak power key point under any hamming weight test plaintext is logic 1, the test result is more error;
s62, dividing the chip to be tested with the test result of error into two equal parts, repeating the steps S2-S6, and gradually narrowing the test range until the fault chip is found out.
5. The method according to claim 1, wherein S3 comprises:
s33, controlling each chip to be tested to each HammingThe weight test plaintext executes the same encryption operation k times respectively, and the curves corresponding to the encryption process are averaged F times, each curve has p pointst i1 ，t i2 ，…，t ip The method comprises the steps of carrying out a first treatment on the surface of the Wherein k is>20；F=8，16，32，64；1≤i≤k；
S34, calculating average power consumption leakage trace of each chip to be tested under the category of the hamming weight value q:
wherein ,q=0,1,2,3,4,5,6,7,8。
6. the method of claim 1, wherein the test parameters comprise: supply voltage, input signal timing, oscilloscope input impedance, sampling frequency, sampling count, bandwidth, time reference, and trigger mode.
7. A chip power consumption channel measurement information cross-validation testing device, comprising:
the metal contact of the test motherboard is connected with a pin of the chip to be tested;
the current probe is connected with the test motherboard and is used for sequentially transmitting the acquired signals to the oscilloscope and the test platform through the high-frequency signal wire;
the test platform is used for executing:
inputting q kinds of test plaintext with different hamming weights into M identical batches of chips to be tested with the same model to execute encryption operation, and collecting a power consumption leakage curve of each chip to be tested in operation;
averaging the power consumption leakage curves under each hamming weight test plaintext to obtain an average power consumption leakage trace;
performing discrete Fourier transform on the average power consumption leakage trace to obtain a power spectrum density curve;
extracting peak characteristics of the power spectrum density curve to obtain peak power key points;
and carrying out exclusive OR operation on peak power key points under the plaintext of the same hamming weight test of different chips to be tested, and carrying out batch cross verification on the chips to be tested.
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