CN111289874A - Robustness testing method, system and device for power semiconductor chip - Google Patents
Robustness testing method, system and device for power semiconductor chip Download PDFInfo
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Abstract
The invention relates to the field of chip testing, and particularly discloses a robustness testing method of a power semiconductor chip. The method can discover defects on the thermoelectric robustness of the chip earlier, discover deeper robustness problems (such as abnormal concentration of heat and uneven heat dissipation) in time, and quantitatively obtain basic data (such as temperature gradient and change along with time) rather than qualitatively; compared with the traditional aging method, the method has the advantages that the detection period of each batch of days or even tens of days is longer, the robustness test of the chip can be completed by the data acquired within tens of minutes to hours, more time is saved, and the production efficiency is effectively improved.
Description
Technical Field
The invention relates to the field of chip testing, in particular to a robustness testing method, system and device for a power semiconductor chip.
Background
For power devices such as LDMOS \ VDMOS \ IGBT and the like, the robustness (namely robustness) of a semiconductor chip is a very important index, the robustness of the power device is often related to the temperature distribution of the device, the power devices such as LDMOS \ VDMOS \ IGBT and the like have high power, the internal or external temperature of the device in a working state can change along with the accumulation of heat, and the change of the temperature can adversely affect the working state of the device, namely a thermoelectric coupling phenomenon. In the case of an IGBT, the internal temperature of the IGBT is increased due to the heat accumulation, and the current is increased along with the increase of the internal temperature, and the current is further increased to increase the power and increase the internal temperature, so that the IGBT falls into a vicious circle and finally directly causes the device to be burnt. In order to ensure reliable operation of electronic components, it is necessary to ensure sufficient robustness of the electronic components during the production process.
At present, the robustness of a semiconductor chip is mainly performed through an aging test, namely, the semiconductor chip to be tested is placed in an aging test device, whether the semiconductor chip to be tested has normal electrical performance is detected through an IV detection module, and a CV detection module is added to the semiconductor chip to be tested for expensive and precise equipment to ensure the reliability of the semiconductor chip to be tested. However, for power devices such as LDMOS \ VDMOS \ IGBT and the like, what affects the reliability of the semiconductor chip to be tested is the problem of temperature accumulation caused by high power, and the reliability of the semiconductor chip to be tested is judged by detecting the electrical property, and the semiconductor chip to be tested can be reflected by the electrical property abnormality only after a long enough aging time.
Disclosure of Invention
The invention provides a robustness testing method of a power semiconductor chip, which aims to solve the problem that the test period is long in the prior art that the robustness of the semiconductor chip to be tested is judged by detecting the electrical property of the semiconductor chip to be tested in the aging process, and can shorten the test time.
The technical scheme adopted by the invention is as follows:
a robustness testing method of a power semiconductor chip comprises the following steps:
s11: acquiring an infrared image of a semiconductor chip to be detected;
s12: acquiring infrared information of Y points in the infrared image space region;
s13: respectively calculating the temperature information of the Y points;
s14: respectively calculating the temperature gradient of the Y points;
s15: dividing the whole space area of the infrared image into i small areas;
s16: acquiring the maximum temperature gradient in each small region, and configuring the maximum temperature gradient in each small region as the temperature gradient of each small region;
s17: counting the temperature gradients of the small regions, drawing a first histogram, wherein the horizontal axis of the first histogram is the temperature gradient, the vertical axis of the first histogram is the number of the small regions corresponding to the temperature gradient, and the first histogram is sorted from large to small according to the number to form a second histogram;
s18: fitting the second histogram by using Rayleigh distribution to obtain sigma, wherein the Rayleigh distribution formula is as follows:
wherein x is a sampling value of the temperature gradient at a certain point, σ is the root mean square of the temperature gradient, and when σ is greater than a first set value, the semiconductor chip to be tested is judged to be abnormal.
The robustness testing method of the power semiconductor chip further comprises a physique screening algorithm, wherein the physique screening algorithm comprises the following steps:
s21: acquiring n infrared images in an aging period;
s22: executing the steps S12 to S18 on the n infrared images to obtain n Rayleigh distributions and parameters sigma thereof1、σ2...σnFor the parameter σ1、σ2...σnCounting is carried out, and a third histogram is drawn;
s23: using Gaussian distribution N (mu, theta)2) Fitting the third histogram to obtain theta, wherein mu is the expectation of the root mean square of the temperature gradient, and theta is the standard deviation of the root mean square of the temperature gradient;
s24: and comparing the theta value with a second set value, and classifying the quality of the semiconductor chip to be tested.
Further, a formula for calculating the temperature information of each point in the space region is as follows:
T(x,y)＝αK(x,y)+β，
the temperature information of the infrared image is obtained by performing linear mapping on the infrared image, wherein K (x, y) is infrared information of a point (x, y) in the infrared image, α is a first constant coefficient used for amplifying the infrared information, β is a second constant coefficient used for converting the temperature information into a positive value, and T (x, y) is temperature information of the infrared image subjected to linear mapping.
Further, the calculation formula of the temperature gradient of each point in the space region is as follows:
i and j are unit vectors in x, y directions,
is a partial differential operator, T is temperature information,
in the form of a vector, the vector,
absolute value of (2)
Is the temperature gradient.
Further, the robustness testing method of the power semiconductor chip further comprises the following steps:
s01, setting an excitation signal and the variation range and the variation process of the excitation signal;
s02: setting an environment temperature, a variation range and a variation process of the environment temperature;
s03: setting aging time, and acquiring and storing an infrared image of the semiconductor chip to be tested in an aging period;
s04: analyzing the electrical property test result of the semiconductor chip to be tested;
s041: if the electrical property of the semiconductor chip to be tested is normal, continuing to execute the step S11 to the step S14;
s042: and if the electrical property of the semiconductor chip to be tested is abnormal, ending the test.
The invention provides a robustness testing system of a power semiconductor chip, which aims to solve the problem that the robustness of the semiconductor chip to be tested is judged by detecting the electrical property of the semiconductor chip to be tested in the aging process in the prior art, so that the testing period is long.
A robustness testing system of a power semiconductor chip, comprising:
the image acquisition module is used for acquiring an infrared image of the semiconductor chip to be detected;
the information acquisition module is used for acquiring the infrared information of Y points in the infrared image space region;
the temperature information calculation module is used for calculating the temperature information of the Y points respectively;
the temperature gradient calculation module is used for calculating the temperature gradients of the Y points respectively;
the space region dividing module is used for dividing the whole space region of the infrared image into i small regions;
a small region temperature gradient obtaining module, configured to obtain a maximum temperature gradient in each small region, and configure the maximum temperature gradient in each small region as a temperature gradient of each small region;
the statistical module is used for counting the temperature gradients of the small regions, drawing a first histogram, wherein the horizontal axis of the first histogram is the temperature gradient, the vertical axis of the first histogram is the number of the small regions corresponding to the temperature gradient, and the first histogram is sorted from large to small according to the number to form a second histogram;
and the analysis module is used for fitting the second histogram by utilizing Rayleigh distribution to calculate the root mean square value of the temperature gradient, and when the root mean square value of the temperature gradient is greater than a first threshold value, the abnormality of the semiconductor chip to be detected is judged.
The invention provides a robustness testing device of a power semiconductor chip, which aims to solve the problem that the robustness of the semiconductor chip to be tested is judged by detecting the electrical property of the semiconductor chip to be tested in the aging process in the prior art, so that the testing period is long.
A robustness testing apparatus of a power semiconductor chip, comprising:
the signal generation module generates various excitation signals to impact the semiconductor chip to be tested;
the temperature control module is used for controlling and adjusting the environmental temperature of the semiconductor chip to be tested;
the electrical property detection module is used for detecting the electrical property of the semiconductor chip to be detected;
the infrared imaging module comprises a camera and is used for obtaining an infrared image of the excited semiconductor chip to be tested;
and the controller is used for processing the infrared image and judging whether the semiconductor chip to be detected is normal or not.
Compared with the prior art, the invention has the beneficial effects that:
when the power semiconductor chip works, a large amount of heat is dissipated, so that the temperature of the chip is high, the temperature change is more obvious, the internal defects, abnormal states and good and bad physique of the power semiconductor chip can be reflected by detecting the surface temperature change of the power semiconductor chip and processing the data, and the time for detecting the temperature change is far shorter than that of a long-time electrical aging test, so that the problem of long test time in the prior art is solved, and the test efficiency is improved.
Drawings
Fig. 1 is a first flowchart of a robustness testing method for a power semiconductor chip according to an embodiment of the present invention;
fig. 2 is a second flowchart of a robustness testing method for a power semiconductor chip according to an embodiment of the present invention;
fig. 3 is a flowchart of a robustness testing method for a power semiconductor chip according to an embodiment of the present invention;
FIG. 4 is a schematic diagram of an infrared image provided by an embodiment of the present invention;
FIG. 5 is a schematic diagram of a first schematic diagram provided in accordance with an embodiment of the present invention;
FIG. 6 is a diagram illustrating a second histogram according to an embodiment of the present invention;
FIG. 7 is a diagram of a third histogram according to an embodiment of the present invention;
fig. 8 is a schematic diagram of a robustness testing apparatus for a power semiconductor chip according to an embodiment of the present invention.
In the figure, 311 is a first isotherm, 312 is a second isotherm, 313 is a third isotherm, 314 is a fourth isotherm, Dt1 is a first temperature gradient, Dt2 is a second temperature gradient, and Dt3 is a third temperature gradient.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The embodiment of the invention provides a robustness testing method of a power semiconductor chip, which is characterized in that the semiconductor chip to be tested is placed in a robustness testing device, the robustness testing device can be used for carrying out aging test on the semiconductor chip to be tested, the robustness testing device comprises a signal generating module, a temperature control module and an infrared imaging module, the signal generating module provides an excitation signal for the semiconductor chip to be tested, the temperature control module enables the semiconductor chip to be tested to work at a set temperature, the infrared imaging module comprises a camera, the semiconductor chip to be tested is photographed through the camera in an aging period, and an infrared image corresponding to the semiconductor chip to be tested is obtained by utilizing a thermal imaging principle, specifically, as shown in figure 1, the method comprises the following steps:
s11: acquiring an infrared image of a semiconductor chip to be detected;
in the embodiment, the infrared imaging module acquires the infrared image, detects the infrared energy (heat) of the semiconductor chip to be detected through non-contact, converts the infrared energy (heat) into an electric signal, and further generates the infrared image and the infrared information of each pixel point of the infrared image.
S12: acquiring infrared information of Y points in an infrared image space region;
the more the number of the acquired infrared information is, the better the implementation is, the more the data is, the more accurate the subsequent statistical analysis is, and therefore, the number of the acquired infrared information is not limited.
S13: respectively calculating temperature information of Y points;
in the embodiment, temperature information corresponding to each point in an infrared image is obtained by linearly mapping the infrared information of each point in a space region of the infrared image one by one, specifically, the embodiment linearly amplifies the infrared information of each point in the space region, then corrects the linearly amplified infrared information to obtain a positive number of 0-100, and configures the positive number obtained by calculation as the temperature information, and the embodiment amplifies the infrared information to make the temperature information difference between two adjacent points more obvious;
specifically, the formula for calculating the temperature information of each point in the space region is as follows:
T(x,y)＝αK(x,y)+β，
where K (x, y) is infrared information of an (x, y) point in the infrared image, α is a first constant coefficient for amplifying the infrared information, β is a second constant coefficient for converting the temperature information into a positive value, and T (x, y) is temperature information of the infrared image subjected to linear mapping.
Specifically, in the present embodiment, the LDMOS semiconductor chip for a P-band radar is taken as an example for description, and after the processing in steps S11 to S13, an infrared image formed in the present embodiment is as shown in fig. 4, where the LDMOS semiconductor chip for a P-band radar is composed of 512 LDMOS units 314 (only 6 are shown here as an example), each LDMOS unit 314 generates heat, and the temperature changes due to the accumulation and dissipation of heat, and in the present embodiment, the temperature distribution of a spatial region is represented by a first isotherm 311, a second isotherm 312, a third isotherm 313, and a fourth isotherm 314.
S14: respectively calculating the temperature gradient of the Y points;
calculating the temperature gradient of each point in the infrared image plane after the processing of the step S11 to the step S13, wherein the calculation formula of the temperature gradient is as follows:
i and j are unit vectors in x, y directions,
is a partial differential operator, T is temperature information,
in the form of a vector, the vector,
absolute value of (2)
Is a temperature gradient.
Taking the LDMOS semiconductor chip for P-band radar as an example, the infrared image is subjected to temperature gradient calculation to form a temperature gradient distribution diagram as shown in fig. 3, in which Dt1 represents a first temperature gradient, Dt2 represents a second temperature gradient, and Dt3 represents a third temperature gradient.
S15: dividing the whole space area of the infrared image into i small areas;
s16: acquiring the maximum temperature gradient in each small area, and configuring the maximum temperature gradient in each small area as the temperature gradient of each small area;
s17: counting the temperature gradients of all the small regions, drawing a first histogram, as shown in fig. 5, wherein the horizontal axis of the first histogram is the temperature gradient, the vertical axis of the first histogram is the number of the small regions corresponding to the temperature gradient, and sorting the first histogram from large to small according to the number to form a second histogram, as shown in fig. 6;
s18: and fitting the second histogram by utilizing Rayleigh distribution to obtain sigma, wherein the Rayleigh distribution formula is as follows:
wherein, x is a sampling value of the temperature gradient at a certain point, sigma is the root mean square of the temperature gradient, and when sigma is larger than a first set value, the semiconductor chip to be tested is judged to be abnormal.
Specifically, the larger the σ value obtained by the rayleigh distribution in the present embodiment is, the larger the temperature change rate of the semiconductor chip under test is, and the temperature distribution of the semiconductor chip under test is not uniform.
Further, as shown in fig. 2, the robustness testing method for the power semiconductor chip further includes a physique screening algorithm, and the physique screening algorithm includes:
s21: acquiring n infrared images in an aging period;
s22: respectively executing the steps S12 to S18 on the n infrared images to obtain n Rayleigh distributions and parameters sigma thereof1、σ2...σnFor parameter σ1、σ2...σnPerforming statistics, and drawing a third histogram, as shown in fig. 7;
s23: using Gaussian distribution N (mu, theta)2) Fitting the third histogram to obtain theta, wherein mu is the expectation of the root mean square of the temperature gradient, and theta is the standard deviation of the root mean square of the temperature gradient;
s24: and comparing the theta value with a second set value, and classifying the quality of the semiconductor chip to be tested.
Specifically, in the embodiment, all infrared images in the whole aging process of the semiconductor chip to be tested are processed and analyzed, and then the value θ is obtained by using gaussian distribution, and when the value θ is smaller, it is indicated that the temperature of the semiconductor chip is more concentrated, the physique is better, and the quality of the semiconductor chip to be tested is convenient to classify subsequently.
It should be noted that the present embodiment determines the robustness of the semiconductor chip by performing a statistical analysis on the temperature gradient distribution, rather than performing a statistical analysis using the temperature distribution, for the following reasons:
1. in different semiconductor chips to be tested, the self-difference of the temperature distribution of the semiconductor chips to be tested is large, and the abnormal temperature of the semiconductor chips to be tested is easily covered by the self-temperature distribution difference as noise;
2. the temperature changes unobviously along with time, the obvious changes are difficult to observe in a short time, and the abnormity of the temperature along with time is difficult to discover;
3. in the process of data statistics by using temperature, because the temperature distribution difference of different semiconductor chips is large, when the statistics is performed by using the distribution such as normal distribution, the data dispersion is large, the fitting error is large, and the parameter value fluctuation is large;
therefore, the statistical analysis is carried out through the temperature gradient distribution, the distribution of temperature change is emphasized, the interference of temperature distribution difference noise among the semiconductor chips is avoided, and the temperature change details of the semiconductor chips are reflected effectively; meanwhile, the temperature gradient distribution among different semiconductor chips is more obvious along with the change of time, and the obvious change can be observed in a short time, so that the abnormality of the semiconductor chips can be detected in a short time; in addition, in the statistical process, the obtained data is less in spread, the rule is more obvious when the statistical method is used for distribution fitting, the fitting error is greatly reduced, and the higher accuracy rate is achieved on the final abnormal detection or physique screening.
Compared with the currently commonly used IV/CV detection method, the method can discover the defects of the device in robustness earlier and discover deeper robustness problems (such as uneven heat dissipation) in time by obtaining basic data (such as temperature gradient and change along with time) quantitatively but not qualitatively; compared with the traditional aging method, the method has the advantages that the detection period of each batch of days or even tens of days is longer, the robustness abnormity detection and the physique screening of the chip can be completed through data acquired from tens of minutes to several hours, more time is saved, and the production efficiency is effectively improved.
Further, as shown in fig. 3, the method for testing robustness of a power semiconductor chip further includes:
s01, setting the excitation signal and the variation range and the variation process of the excitation signal;
s02: setting the environment temperature, the variation range and the variation process of the environment temperature;
s03: setting aging time, and acquiring and storing an infrared image of the semiconductor chip to be tested in an aging period;
s04: analyzing the electrical property test result of the semiconductor chip to be tested;
s041: if the electrical property of the semiconductor chip to be tested is normal, continuing to execute the step S11 to the step S14;
s042: and if the electrical property of the semiconductor chip to be tested is abnormal, ending the test.
The present embodiment further provides a robustness testing system for a power semiconductor chip, including:
the image acquisition module is used for acquiring an infrared image of the semiconductor chip to be detected;
the information acquisition module is used for acquiring infrared information of each point Y in the infrared image space area;
the temperature information calculation module is used for calculating the temperature information of the Y points in a distributed manner;
the temperature gradient calculation module is used for calculating the temperature gradients of the Y points respectively;
the space region dividing module is used for dividing the whole space region of the infrared image into i small regions;
the small region temperature gradient acquisition module is used for acquiring the maximum temperature gradient in each small region and configuring the maximum temperature gradient in each small region as the temperature gradient of each small region;
the statistical module is used for counting the temperature gradients of all the small regions, drawing a first histogram, wherein the horizontal axis of the first histogram is the temperature gradient, the vertical axis of the first histogram is the number of the small regions corresponding to the temperature gradient, and the first histogram is sorted from large to small according to the number to form a second histogram;
and the analysis module is used for fitting the second histogram by utilizing Rayleigh distribution to calculate the root mean square value of the temperature gradient, and when the root mean square value of the temperature gradient is greater than the first threshold value, the abnormality of the semiconductor chip to be detected is judged.
As shown in fig. 8, the present embodiment further provides a robustness testing apparatus for a power semiconductor chip, including:
the signal generation module generates various excitation signals to impact the semiconductor chip to be tested;
the temperature control module is used for controlling and adjusting the environmental temperature of the semiconductor chip to be tested;
the electrical property detection module comprises an IV detection circuit and/or a CV detection circuit and is used for detecting the electrical property of the semiconductor chip to be detected;
the infrared imaging module comprises a camera and is used for obtaining an infrared image of the excited semiconductor chip to be tested;
and the controller is used for judging whether the semiconductor chip to be tested is normal or not.
Further, the present embodiment can adjust the excitation signal, adjust the temperature, control the aging time, and control the electrical detection module to perform the electrical performance test on the semiconductor chip through the controller, and analyze the test result.
Specifically, the signal generation module provided in this embodiment may further manually adjust the excitation signal, where the excitation signal includes, but is not limited to, a pulse signal and an AC signal, and according to the actual situation, the form and the signal parameters of the excitation signal may be flexibly selected.
Specifically, the signal generation module provided in this embodiment further includes a bias circuit, and when the LDMOS chip for the P-band radar is tested, the bias circuit is first used to set the LDMOS chip for the P-band radar to a quiescent operating point, and then an output excitation signal is used to impact the chip.
In summary, the robustness testing method for the power semiconductor chip provided by the embodiment can shorten the aging time, thereby improving the testing efficiency.
Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that changes, modifications, substitutions and alterations can be made in these embodiments without departing from the principles and spirit of the invention, the scope of which is defined in the appended claims and their equivalents.
Claims (7)
1. A robustness testing method of a power semiconductor chip is characterized by comprising the following steps:
s11: acquiring an infrared image of a semiconductor chip to be detected;
s12: acquiring infrared information of Y points in the infrared image space region;
s13: respectively calculating the temperature information of the Y points;
s14: respectively calculating the temperature gradient of the Y points;
s15: dividing the whole space area of the infrared image into i small areas;
s16: acquiring the maximum temperature gradient in each small region, and configuring the maximum temperature gradient in each small region as the temperature gradient of each small region;
s17: counting the temperature gradients of the small regions, drawing a first histogram, wherein the horizontal axis of the first histogram is the temperature gradient, the vertical axis of the first histogram is the number of the small regions corresponding to the temperature gradient, and the first histogram is sorted from large to small according to the number to form a second histogram;
s18: fitting the second histogram by using Rayleigh distribution to obtain sigma, wherein the Rayleigh distribution formula is as follows:
wherein x is a sampling value of the temperature gradient at a certain point, σ is the root mean square of the temperature gradient, and when σ is greater than a first set value, the semiconductor chip to be tested is judged to be abnormal.
2. The method for testing the robustness of a power semiconductor chip according to claim 1, wherein the method for testing the robustness of a power semiconductor chip further comprises a fitness screening algorithm, the fitness screening algorithm comprising:
s21: acquiring n infrared images in an aging period;
s22: executing the steps S12 to S18 on the n infrared images to obtain n Rayleigh distributions and parameters sigma thereof1、σ2...σnFor the parameter σ1、σ2...σnCounting is carried out, and a third histogram is drawn;
s23: using Gaussian distribution N (mu, theta)2) Fitting the third histogram to obtain theta, wherein mu is the expectation of the root mean square of the temperature gradient, and theta is the standard deviation of the root mean square of the temperature gradient;
s24: and comparing the theta value with a second set value, and classifying the quality of the semiconductor chip to be tested.
3. The method for testing the robustness of the power semiconductor chip as recited in claim 1, wherein the formula for calculating the temperature information of each point in the space region is as follows:
T(x,y)＝αK(x,y)+β，
the temperature information of the infrared image is obtained by performing linear mapping on the infrared image, wherein K (x, y) is infrared information of a point (x, y) in the infrared image, α is a first constant coefficient used for amplifying the infrared information, β is a second constant coefficient used for converting the temperature information into a positive value, and T (x, y) is temperature information of the infrared image subjected to linear mapping.
4. The method for testing the robustness of a power semiconductor chip according to claim 1, wherein the calculation formula of the temperature gradient at each point in the space region is as follows:
i and j are unit vectors in x, y directions,
is a partial differential operator, T is temperature information,
in the form of a vector, the vector,
absolute value of (2)
Is the temperature gradient.
5. The method for testing the robustness of a power semiconductor chip according to claim 1, wherein the method for testing the robustness of a power semiconductor chip further comprises:
s01, setting an excitation signal and the variation range and the variation process of the excitation signal;
s02: setting an environment temperature, a variation range and a variation process of the environment temperature;
s03: setting aging time, and acquiring and storing an infrared image of the semiconductor chip to be tested in an aging period;
s04: analyzing the electrical property test result of the semiconductor chip to be tested;
s041: if the electrical property of the semiconductor chip to be tested is normal, continuing to execute the step S11 to the step S14;
s042: and if the electrical property of the semiconductor chip to be tested is abnormal, ending the test.
6. A robustness testing system for a power semiconductor chip, comprising:
the image acquisition module is used for acquiring an infrared image of the semiconductor chip to be detected;
the information acquisition module is used for acquiring the infrared information of Y points in the infrared image space region;
the temperature information calculation module is used for calculating the temperature information of the Y points respectively;
the temperature gradient calculation module is used for calculating the temperature gradients of the Y points respectively;
the space region dividing module is used for dividing the whole space region of the infrared image into i small regions;
a small region temperature gradient obtaining module, configured to obtain a maximum temperature gradient in each small region, and configure the maximum temperature gradient in each small region as a temperature gradient of each small region;
the statistical module is used for counting the temperature gradients of the small regions, drawing a first histogram, wherein the horizontal axis of the first histogram is the temperature gradient, the vertical axis of the first histogram is the number of the small regions corresponding to the temperature gradient, and the first histogram is sorted from large to small according to the number to form a second histogram;
and the analysis module is used for fitting the second histogram by utilizing Rayleigh distribution to calculate the root mean square value of the temperature gradient, and when the root mean square value of the temperature gradient is greater than a first threshold value, the abnormality of the semiconductor chip to be detected is judged.
7. A robustness testing device of a power semiconductor chip is characterized by comprising:
the signal generation module generates various excitation signals to impact the semiconductor chip to be tested;
the temperature control module is used for controlling and adjusting the environmental temperature of the semiconductor chip to be tested;
the electrical property detection module is used for detecting the electrical property of the semiconductor chip to be detected;
the infrared imaging module comprises a camera and is used for obtaining an infrared image of the excited semiconductor chip to be tested;
and the controller is used for processing the infrared image and judging whether the semiconductor chip to be detected is normal or not.
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112067965A (en) * | 2020-09-15 | 2020-12-11 | 哈尔滨理工大学 | IGBT module health state monitoring system capable of predicting service life |
| CN112526310A (en) * | 2020-11-26 | 2021-03-19 | 中国科学院微电子研究所 | Radio frequency power LDMOS device packaging level robustness assessment method |
| CN112857595A (en) * | 2021-01-15 | 2021-05-28 | 苏州浪潮智能科技有限公司 | Aging chamber temperature detection method, system and medium |
| CN113655370A (en) * | 2021-08-13 | 2021-11-16 | 海光信息技术股份有限公司 | Method, device and system for determining abnormal test working condition of chip and related equipment |
-
2020
- 2020-02-20 CN CN202010105583.XA patent/CN111289874A/en not_active Withdrawn
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112067965A (en) * | 2020-09-15 | 2020-12-11 | 哈尔滨理工大学 | IGBT module health state monitoring system capable of predicting service life |
| CN112526310A (en) * | 2020-11-26 | 2021-03-19 | 中国科学院微电子研究所 | Radio frequency power LDMOS device packaging level robustness assessment method |
| CN112857595A (en) * | 2021-01-15 | 2021-05-28 | 苏州浪潮智能科技有限公司 | Aging chamber temperature detection method, system and medium |
| CN112857595B (en) * | 2021-01-15 | 2022-12-27 | 苏州浪潮智能科技有限公司 | Aging chamber temperature detection method, system and medium |
| CN113655370A (en) * | 2021-08-13 | 2021-11-16 | 海光信息技术股份有限公司 | Method, device and system for determining abnormal test working condition of chip and related equipment |
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