CN116367704A - Three-terminal memristor with heating electrode and manufacturing and operating method thereof - Google Patents
Three-terminal memristor with heating electrode and manufacturing and operating method thereof Download PDFInfo
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/20—Multistable switching devices, e.g. memristors
- H10N70/253—Multistable switching devices, e.g. memristors having three or more terminals, e.g. transistor-like devices
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/011—Manufacture or treatment of multistable switching devices
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/801—Constructional details of multistable switching devices
- H10N70/841—Electrodes
- H10N70/8413—Electrodes adapted for resistive heating
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Abstract
The invention discloses a three-terminal memristor with a heating electrode and a manufacturing and operating method thereof, and relates to the technical field of semiconductor devices, wherein the three-terminal memristor comprises a substrate, and the heating electrode, a bottom electrode, a resistance change structure and a top electrode which are sequentially arranged on the substrate from bottom to top; wherein, hinder the variable structure and include the variable layer at least, the heating electrode includes: a conductive layer, a dielectric layer, and a heat generating layer; the conductive layer is arranged on the substrate and is covered by the dielectric layer; a portion of the conductive layer exposed to the outside of the dielectric layer as a conductive portion electrically connected to the outside; the heat generating layer is arranged in the dielectric layer in a penetrating way and is respectively connected with the conducting layer and the bottom electrode; when a voltage pulse is applied between the conductive layer and the bottom electrode, the heat generating layer generates heat to heat the resistive layer, and the heating can promote the generation or migration of oxygen vacancies, so that the working voltage of the memristor is reduced.
Description
Technical Field
The invention relates to the technical field of semiconductor devices, in particular to a three-terminal memristor with a heating electrode and a manufacturing and operating method thereof.
Background
Currently, the implementation of in-house computing using memristors has been given widespread attention, which avoids power consumption and delay caused by data handling between the storage unit and the computing unit, and can efficiently implement applications such as artificial neural networks, machine learning, scientific computing, digital image processing, etc., thereby meeting increasing computing power demands.
Some types of memristors may implement resistance change based on oxygen vacancy formation of conductive filaments (e.g., conductive filament memristors), or based on oxygen vacancy migration (e.g., monolithic memristors). However, existing memristors suffer from the following problems:
for memristors based on formation of conductive filaments by oxygen vacancies, because the number of oxygen vacancies in metal oxides prepared by integrated circuit processes is small, it is difficult to form continuous conductive filaments, and thus a large operating voltage needs to be applied to form conductive filaments; there is also the problem of relatively high operating voltages for memristors based on oxygen vacancy migration.
In summary, the existing memristors based on oxygen vacancy formation conductive filaments or oxygen vacancy migration have the problem of higher working voltage.
Disclosure of Invention
The invention aims to provide a three-terminal memristor with a heating electrode, and a manufacturing and operating method thereof, which can promote generation or migration of oxygen vacancies through heating so as to reduce the working voltage of the memristor.
In order to achieve the above object, the present invention provides the following solutions:
a three-terminal memristor with a heater electrode, comprising: the device comprises a substrate, a heating electrode, a bottom electrode, a resistance change structure and a top electrode, wherein the heating electrode, the bottom electrode, the resistance change structure and the top electrode are sequentially arranged on the substrate from bottom to top; wherein the resistive structure at least comprises a resistive layer;
the heating electrode includes:
a conductive layer disposed on the substrate;
a dielectric layer; the conductive layer is partially covered by the dielectric layer, and a portion of the conductive layer exposed outside the dielectric layer serves as a conductive portion electrically connected to the outside; the dielectric layer is at least used for isolating the bottom electrode and the conductive layer;
the heat generating layer is arranged in the dielectric layer in a penetrating way and is respectively connected with the conducting layer and the bottom electrode; the heat generating layer is used for generating heat when electricity is supplied between the bottom electrode and the conductive part of the conductive layer so as to heat the resistance change layer.
Optionally, the heat generating layer has an area smaller than an area of the resistive layer.
Optionally, the orthographic projection of the heat generating layer on the substrate is located at a central position of the target overlapping portion; the target overlapping portion is: and the overlapping part of the conducting layer, the bottom electrode and the top electrode, which are orthographic projected on the substrate.
Optionally, the resistance of the heat generating layer is greater than that of the conductive layer and the bottom electrode.
Optionally, the material of the heat generating layer includes at least one of tungsten, titanium nitride, and tantalum nitride.
Optionally, the heating electrode further comprises:
a heat preservation layer; one surface of the heat preservation layer is contacted with the substrate, and the other surface of the heat preservation layer is contacted with the conductive layer and the dielectric layer.
Optionally, the three-terminal memristor is specifically an integral three-terminal memristor, and the resistive structure further includes a dielectric layer.
The invention also provides a three-terminal memristor with a heating electrode, comprising:
the device comprises a substrate, a heating electrode, a bottom electrode, a resistance change structure and a top electrode, wherein the heating electrode, the bottom electrode, the resistance change structure and the top electrode are sequentially arranged on the substrate from bottom to top; wherein the resistive structure at least comprises a resistive layer; the heating electrode includes:
a conductive layer disposed on the substrate;
a dielectric layer; the dielectric layer is at least used for isolating the bottom electrode and the conductive layer;
the heat generating layer is arranged in the dielectric layer in a penetrating way and is respectively connected with the conducting layer and the bottom electrode; the heat generating layer is used for generating heat when electricity is supplied between the bottom electrode and the conductive layer so as to heat the resistance change layer.
The invention also provides an operation method, which is applied to the three-terminal memristor, and comprises the following steps:
resistance state switching operation:
applying a voltage or current pulse between the bottom electrode and the heating electrode so that the temperature of the resistive switching structure above the heat generating layer reaches and remains within a preset range;
applying a positive voltage pulse between the top electrode and the bottom electrode when switching from a high resistance state to a low resistance state;
when switching from the low resistance state to the high resistance state, a negative voltage pulse is applied between the top electrode and the bottom electrode.
In order to achieve the above object, the present invention further provides a method for manufacturing a three-terminal memristor with a heating electrode, the method comprising:
preparing a conductive layer on a substrate;
preparing a dielectric layer covering the conductive layer;
manufacturing a window in the dielectric layer, and filling a heating material in the window to form a heat generating layer penetrating through the dielectric layer to obtain an intermediate preparation;
preparing a bottom electrode on the intermediate preparation; wherein the bottom electrode is isolated from the conductive layer by the dielectric layer; the heat generating layer is respectively connected with the conducting layer and the bottom electrode;
preparing a resistive switching structure on an intermediate preparation having a bottom electrode;
and preparing a top electrode on the resistive structure.
According to the specific embodiment provided by the invention, the invention discloses the following technical effects:
in the embodiment of the invention, the dielectric layer in the heating electrode isolates the bottom electrode from the conductive layer, and when a voltage or current pulse is applied between the conductive part of the conductive layer and the bottom electrode, a passage is formed between the conductive layer and the bottom electrode through the heat generating layer, so that the heat generating layer generates heat to heat the resistive structure (resistive layer) above.
Compared with the prior art, the embodiment of the invention increases the heating electrode to heat the resistance change structure by applying the working voltage between the bottom electrode and the top electrode. Heating may promote conductive filament formation or, alternatively, increase oxygen vacancy mobility. In this way, the working voltage between the top electrode and the bottom electrode can be relatively low, so that the three-terminal memristor claimed by the embodiment of the present invention is suitable for a scenario with lower working voltage.
Drawings
FIG. 1 is a top view of a three-terminal memristor with heating electrode provided by the present disclosure;
FIG. 2 is a cross-sectional view of a three-terminal memristor with heating electrode provided by the present disclosure;
FIG. 3 is a schematic diagram of a resistance state transition of an integrated memristor;
FIG. 4 is a schematic diagram showing the relationship between the memristor initialization voltage and the low-resistance switching voltage, and the highest temperature of the resistive switching layer;
FIG. 5 is a diagram showing the variation of the temperature of the resistive layer with respect to the voltage pulse of the heating electrode;
FIG. 6 is a schematic top view of the isothermal surface of the resistive switching layer;
FIG. 7 is a schematic diagram showing the probability of formation of conductive filaments versus position;
FIG. 8 is a cross-sectional view of another three-terminal memristor with a heater electrode provided by the present disclosure;
FIG. 9 is a cross-sectional view of yet another three-terminal memristor with heater electrode provided by the present disclosure;
FIG. 10 is a cross-sectional view of yet another three-terminal memristor with heater electrode provided in accordance with an embodiment of the present disclosure.
Symbol description:
the device comprises a substrate-0, a heating electrode-1, a conducting layer-11, a conducting part-110, a dielectric layer-12, a heat generating layer-13, a heat insulating layer-14, a first adhesion layer-15, a second adhesion layer-16, a bottom electrode-2, a conducting part-20, a resistance change structure-3, a resistance change layer-31, a dielectric layer-32 and a top electrode-4.
Detailed Description
Embodiments of the present invention are described below with reference to the accompanying drawings.
The invention aims to provide a three-terminal memristor with a heating electrode structure, which is used for heating a resistance change layer through a heating electrode to promote the generation or migration of oxygen vacancies so as to reduce the working voltage of the memristor.
As shown in fig. 1 and 2, the three-terminal memristor includes: a substrate 0, a heating electrode 1, a bottom electrode 2, a resistive switching structure 3 and a top electrode 4 which are arranged on the substrate 0 in sequence from bottom to top. Wherein the heating electrode 1, the bottom electrode 2 and the top electrode 4 are three terminals of the three-terminal memristor respectively. While the part of the dashed box in fig. 1 is actually covered by the resistive switching structure 3, now shown to show the connection between the memristor three terminals.
Wherein the resistive structure 3 comprises at least a resistive layer 31 (as shown in fig. 10).
The heating electrode 1 includes: a conductive layer 11, a dielectric layer 12 and a heat generating layer 13.
The conductive layer 11 is disposed on the substrate 0.
The conductive layer 11 is partially covered with the dielectric layer 12, and a portion of the conductive layer 11 exposed outside the dielectric layer 12 serves as a conductive portion 110 electrically connected to the outside. Alternatively, a part of the upper surface of the conductive layer 11 is covered with the dielectric layer 12, and the uncovered upper surface region is used as the conductive portion 110. The dielectric layer 12 is at least used to isolate the bottom electrode 2 from the conductive layer 11.
In addition, the conductive portion 110 is also exposed outside the resistive switching structure 3.
Specifically, referring to fig. 2, the dielectric layer 12, the resistive structure 3 and the conductive portion 110 form a via, a window or a trench structure. That is, the height of the conductive portion 110 with respect to the substrate 0 is lower than the height of the dielectric layer 12 and the resistive structure 3, and is surrounded by the dielectric layer 12 and the resistive structure 3.
In other embodiments of the present invention, referring to fig. 8, the dielectric layer 12, the resistive structure 3 and the conductive portion 110 may also form a step structure.
Those skilled in the art can flexibly design the position of the conductive part 110 as required, as long as it is exposed. Alternatively, referring to fig. 9, leads may be connected at the conductive layer 11, and electrical connection with the outside may be similarly achieved. In this case, the upper surface of the conductive layer 11 may not be exposed, i.e., the conductive portion 110 may not be exposed.
Similarly, referring to fig. 2 or 9, the bottom electrode 2 may also have a conductive portion 20, and the conductive portion 20 may also be exposed outside the resistive structure 3 to electrically connect the bottom electrode 2 with the outside. The conductive portion 20 may be a via, a window, or a step structure. Alternatively, a lead is connected to the bottom electrode 2, and electrical connection to the outside is also possible.
The heat generating layer 13 is penetratingly arranged in the dielectric layer 12 and is connected to the conductive layer 11 and the bottom electrode 2, respectively. When electricity is supplied between the bottom electrode 2 and the conductive layer 11 (e.g., the conductive portion 110), a path is formed between the conductive layer 11, the heat generating layer 13, and the bottom electrode 2, and the heat generating layer 13 generates heat to heat the resistive layer 31.
Specifically, a voltage pulse or a current pulse may be applied between the bottom electrode 2 and the conductive layer 11 (e.g., the conductive portion 110).
In one example, the resistance of the heat generating layer 13 is greater than the conductive layer 11 and the bottom electrode 2. The use of a material having a relatively low resistivity for the conductive layer 11 and the bottom electrode 2 can reduce the voltage drop caused by the parasitic resistance in series, and more voltage is applied to the heat generating layer 13, thereby improving the heating efficiency.
The three-terminal memristor structure can be respectively applicable to a conductive filament type memristor and an integral memristor.
In one embodiment, the area of the heat generating layer 13 is smaller than the area of the resistive layer 31. In this embodiment, since the area of the heat generating layer 13 is smaller than that of the resistive layer 31, the heat generating layer 13 generates heat to locally heat the resistive layer 31 above, which is also beneficial to the directional formation of conductive filaments when the three-terminal memristor is a conductive filament memristor, as will be further described later. Of course, for an integrated memristor, the area of the heat-generating layer 13 may also be smaller than the area of the resistive layer 31.
The embodiment of the invention also discloses an operation method for protecting the three-terminal memristor, which comprises the following steps:
resistance state switching operation:
step 001: a voltage or current pulse is applied between the bottom electrode 2 and the heating electrode 1 so that the temperature of the resistive switching structure 3 above the heat generating layer 13 reaches and remains within a preset range.
Specifically, the temperature of the resistive layer 31 may be brought to and maintained within a predetermined range.
The pulse waveform of the voltage pulse or the current pulse can be exemplified by rectangular wave, triangular wave or sine wave; the pulse waveforms are various and can be selected according to practical situations, and are not described in detail herein.
Exemplary of the preset range may be: 300K-1300K. K represents Kelvin.
Step 002: when switching from the low resistance state to the high resistance state, a negative voltage pulse is applied between the top electrode 4 and the bottom electrode 2.
Specifically, when the three-terminal memristor is a conductive filament-type memristor, step 001 and step 002 may be performed after initializing the conductive filament-type memristor.
The conductive filaments in the resistive layer 31 can be broken by applying negative voltage pulse, so that the resistance value of the conductive filament type memristor is increased; meanwhile, since the heating is performed in step 001, the oxygen vacancy recombination rate of the heated region is increased, so that the amplitude of the negative voltage pulse required at the time of switching (conversion) is relatively low, for example, -2V when not heated, and-1V after heated.
When the three-terminal memristor is particularly an integral memristor, the oxygen vacancy interface is far away from the bottom electrode 2 by applying negative voltage pulse, so that the resistance value of the integral memristor is increased; meanwhile, the amplitude of the negative voltage pulse required by switching is relatively low due to heating, for example, -3V when not heating and-2V after heating.
Step 003: when switching from the high-resistance state to the low-resistance state, a positive voltage pulse is applied between the top electrode 4 and the bottom electrode 2.
When the three-terminal memristor is a conductive filament memristor, steps 001 and 003 may be performed after initializing the conductive filament memristor.
The broken parts of the conductive filaments in the resistive layer are reconnected by applying positive voltage pulse, so that the resistance value of the conductive filament type memristor is reduced; meanwhile, as the heating temperature is raised, the oxygen vacancy generation rate of the heating area can be improved, so that the amplitude of positive voltage pulse required in switching is relatively low, for example, 2V when the heating area is not heated and 1V after the heating.
When the three-terminal memristor is an integral memristor, referring to fig. 3, by applying a positive voltage pulse, an oxygen vacancy interface (as shown by a dotted line in fig. 3) is pushed to a position closer to the bottom electrode 2, so that the resistance value of the integral memristor is reduced; meanwhile, the amplitude of the positive voltage pulse required by switching is relatively low due to heating temperature rise, for example, 3V when not heating and 2V after heating.
The order of step 002 and step 003 is merely illustrative, and the corresponding operation may be performed as needed in the actual operation process.
In addition, whether the resistance state switching is successful or not can be judged by reading the resistance value of the memristor; for example, when the memristor is switched from a low resistance state to a high resistance state, the resistance value of the memristor is read, and if the previous low resistance value (several kiloohms) is changed to the high resistance value (several tens kiloohms), the resistance state switching is successful. And vice versa.
The amplitude and the pulse width are changed for a plurality of times to carry out experiments, and the resistance value of the memristor is read to judge whether the switching is successful, so that the specific value or the range of the amplitude and the pulse width which can ensure the successful switching of the resistance state can be obtained.
And a voltage pulse amplitude and a pulse width value can be selected from the specific values or the value ranges, and positive and negative voltage pulses are applied based on the selected voltage pulse amplitude and pulse width value in the process of using the memristor so as to ensure that the resistance switching operation can be successful and further improve the working efficiency.
Of course, the voltage pulse amplitude and the pulse width can be set empirically, and will not be described here.
Further, since the conductive filament type memristor has no resistance change capability just after the preparation is completed, an initialization process is further required to form the conductive filament, and the initialization operation is specifically as follows:
step 01: a voltage or current pulse is applied between the bottom electrode 2 and the heating electrode 1 so that the temperature of the resistive switching structure 3 above the heat generating layer 13 reaches and remains within a preset range.
Step 01 can refer to step 001 described above, and will not be described herein.
Step 02: a positive voltage pulse is applied between the top electrode 4 and the bottom electrode 2 so that a conductive filament is formed on the resistive layer 31.
It should be noted that, in the prior art, when the initializing operation is performed, a higher voltage (for example, 4-5V) is generally required to be applied, in order to reduce the initializing voltage, in the embodiment of the present invention, the heat generating layer 13 is used to heat the resistive switching structure 3, so that the probability of generating oxygen vacancies is improved, and the conductive filaments are easier to form, so that the memristor claimed in all embodiments of the present invention only needs a relatively lower voltage (for example, 1-2V) to form the conductive filaments; for the same memristor, initialization is typically only required once.
Further, after the initialization operation is completed, whether the initialization is successful (conductive filament formation) can be judged by reading the resistance value of the memristor; for example: if a low resistance value (e.g., several kiloohms) indicates that the conductive filaments are formed, and if a high resistance value (e.g., several tens of kiloohms) indicates that the conductive filaments are not formed.
For an integrated memristor, no initialization is required, and the resistance value thereof can be continuously changed between 25kΩ and 250kΩ, for example; in addition, the heating of the resistive switching structure 3 improves the mobility of oxygen vacancies, so that the speed of resistive switching can be increased, and the operation time can be shortened.
In the embodiment of the invention, the heating electrode 1 is added on the basis of the existing memristors at two ends, so that the three-end memristor is formed. The following illustrates the working principle of the three-terminal memristor as follows:
applying a forward bias between the top electrode 4 and the bottom electrode 2, low-resistance switching (and initialization when in particular a conductive filament memristor) can be accomplished; the reverse bias voltage is applied between the top electrode 4 and the bottom electrode 2, so that the high-resistance switching can be completed; by applying a voltage pulse or a current pulse between the bottom electrode 2 and the heating electrode 1, joule heat can be generated in the heating layer 13, and the upper resistive structure 3 can be heated by heat conduction.
The embodiment of the invention further provides a manufacturing method of the three-terminal memristor, which exemplarily comprises the following steps:
step S01: a conductive layer 11 is prepared on a substrate 0.
Referring to fig. 10, exemplary substrate 0 materials may be: silicon.
The process for preparing the conductive layer 11 may have various options, for example, photolithography, physical vapor deposition, and lift-off processes may be selected to form the conductive layer 11. Alternatively, the conductive layer finished product may be directly adhered to the substrate 0, which is not described herein. The thickness of the conductive layer 11 is in the range of 30-100nm, for example.
Step S02: a dielectric layer 12 is prepared on the conductive layer 11.
The dielectric layer 12 may be formed by plasma enhanced chemical vapor deposition, or the dielectric layer 12 may be directly adhered to the conductive layer 11.
In one example, the dielectric layer 12 partially covers the conductive layer 11, and a portion of the conductive layer 11 exposed outside the dielectric layer 12 serves as a conductive portion 110 electrically connected to the outside.
As mentioned above, the dielectric layer 12 may electrically isolate the bottom electrode 2 from the conductive layer 11. In addition, the dielectric layer 12 may also serve as a thermal insulation, so that the heat generated by the heat generating layer 13 is more concentrated to flow to the resistive structure above, thereby promoting the generation of conductive filaments or the migration of oxygen vacancies. In terms of materials, one skilled in the art can select materials having insulating (or semi-insulating) insulating properties. For example, referring to fig. 10, the material of the dielectric layer 12 is silicon dioxide.
Step S03: a window is made in the dielectric layer 12 and filled with a heating material, forming a heat generating layer 13 penetrating the dielectric layer 12 and connected to the conductive layer 11.
In the preparation of the window in the dielectric layer 12, electron beam lithography and reactive ion etching may be used, or, in the case of pasting the dielectric layer finished product, the window may be directly reserved on the finished product.
In filling the heating material, the window of the dielectric layer 12 may be filled using any one of physical vapor deposition, chemical vapor deposition, and atomic layer deposition. Alternatively, the heat generating layer 13 of the same size may be directly adhered in the window. Alternatively, the dielectric layer 12 embedded with the heat generating layer 13 may be directly disposed on the conductive layer 11, so as to obtain a product with the heat generating layer 13 and the dielectric layer 12.
The product obtained after performing step S03 may be referred to as an intermediate preparation.
Step S04: the bottom electrode 2 is prepared on the intermediate preparation.
Wherein the bottom electrode 2 is isolated from the conductive layer 11 by a dielectric layer 12.
Since the heat generating layer 13 penetrating the dielectric layer 12 is formed in step S03, after the bottom electrode 2 is prepared, the heat generating layer 13 may be connected to the conductive layer 11 and the bottom electrode 2, respectively.
As mentioned above, the resistance of the heat generating layer 13 may be larger than that of the conductive layer 11 and the bottom electrode 2.
Further, the materials of the conductive layer 11 and the bottom electrode 2 may be selected from metal materials having a relatively low resistivity and a relatively high melting point, such as silver, copper, tungsten, and platinum. The material of the conductive layer 11 can be flexibly selected or designed by those skilled in the art as required, and will not be described here.
The material of the heat generating layer 13 (which may be referred to as a heating material) may be selected or designed to have a resistance value greater than that of the conductive layer 11 and the bottom electrode 2. For example, the material resistivity of the heat generating layer 13 ranges from 10 5 -10 6 Omega.m magnitude.
In addition, the person skilled in the art can consider both thermal stability and pore-filling ability. Therefore, in one example, the material of the heat generating layer 13 includes at least one of tungsten, titanium nitride and tantalum nitride, so as to satisfy the advantages of better thermal stability and good hole filling capability while having a resistance value larger than that of the conductive layer 11 and the bottom electrode 2. That is, the heat generating layer 13 may be a tungsten layer, a titanium nitride layer, or a tantalum nitride layer in particular; alternatively, the heat generating layer 13 may specifically include: a stacked titanium nitride layer and tantalum nitride layer. Of course, other materials than the examples described above may be selected as desired by those skilled in the art.
Further, to maintain a constant heating power, the total resistance of the heat generating layer 13 should be kept constant regardless of the material selected; the value range of the total resistance can be exemplified by: 50-200Ω. The thickness of the dielectric layer 12 directly determines the thickness, cross-sectional area and resistivity of the heat-generating layer 13, which all affect the total resistance of the heat-generating layer, and in the case of a certain cross-sectional area, different thicknesses of the dielectric layer should be selected when heating materials with different resistivity are used to form the heat-generating layer, and the following principles are followed: if a heating material with low resistivity is used, the thickness of the dielectric layer and the heat generating layer should be relatively large, while if a material with high resistivity is used, a smaller thickness should be designed.
Therefore, when heating materials with different resistivity are used to form the heat generating layer 13, the thickness of the dielectric layer 12 and the size of the window on the dielectric layer 12 should be flexibly selected; the thickness range of the dielectric layer 12 may be exemplified by: 10-200nm. Of course, if the window is larger or smaller, the thickness range of the dielectric layer 12 may be smaller or larger to ensure a fixed total resistance.
Step S05: a resistive switching structure 3 is prepared on an intermediate preparation with a bottom electrode 2.
Therein, in one example, the aforementioned conductive portion 110 is exposed outside the resistive switching structure 3.
It has been mentioned before that the resistive structure 3 comprises at least a resistive layer 31.
In one example, the resistive layer 31 is a metal oxide resistive layer. Specifically, the material of the metal oxide resistance change layer includes at least one of zirconium oxide, nickel oxide, titanium oxide, zinc oxide, tungsten oxide, and hafnium oxide.
Illustratively, the thickness of the resistive layer 31 may range from: 3-10nm.
As for the thickness of the bottom electrode 2, since the bottom electrode 2 is located between the heat generating layer 13 and the resistive layer 31, the heating efficiency of the resistive layer region above the heat generating layer 13 is directly affected, and thus the thickness of the bottom electrode 2 is critical.
Simulation results showed that the ratio of the maximum temperature of the resistive layer 31 to the maximum temperature of the heat generating layer 13 was about 60% when the thickness of the bottom electrode 2 was 40nm, and that the ratio of the maximum temperature of the resistive layer 31 to the maximum temperature of the heat generating layer 13 was about 90% when the thickness of the bottom electrode 2 was 10 nm; the thinner the bottom electrode 2, the higher the heat transfer efficiency, and the thickness of the bottom electrode 2 is as thin as possible from the viewpoint of heat transfer efficiency.
However, the bottom electrode 2 cannot be too thin. Because, if the thickness of the bottom electrode 2 is too thin, the parasitic resistance of the wire connection becomes large, which will cause more voltage drop on the wire than on the heat generating layer 13, but will affect (reduce) the heating power of the heat generating layer 13. Therefore, in summary, the thickness range of the bottom electrode 2 can be selected as: 10-40nm.
When the three-terminal memristor is a conductive filament-type memristor, the resistive layer 31 can enable the conductive filament to form or break under the action of an external electric field, so that the memristor function is realized.
When the three-terminal memristor is a monolithic three-terminal memristor, the resistive switching structure 3 includes the dielectric layer 32 (as shown in fig. 3) in addition to the resistive switching layer 31. Wherein the dielectric layer 32 is used to reduce the current.
Specifically, the dielectric layer 32 is disposed between the resistive layer 31 and the bottom electrode 2. The dielectric layer 32 may have a thickness in the range of 1-2nm, and the material may be an insulating medium such as silicon dioxide, for example.
Step S06: a top electrode 4 is prepared on the resistive switching structure 3.
Specifically, for the conductive filament type three-terminal memristor, the top electrode 4 exchanges oxygen ions with the resistive layer 31, so that formation or fracture of the conductive filament is realized, and the memristor function is realized in an auxiliary manner. Therefore, the material of the top electrode 4 should have a strong oxygen storage capacity.
For monolithic three-terminal memristors, no conductive path is formed between the top electrode 4 and the bottom electrode 2 of the monolithic memristor due to the presence of the dielectric layer 32, and carriers form a current by tunneling through the dielectric layer 32.
The person skilled in the art can flexibly select or design a material with a strong oxygen storage capacity as the preparation material of the top electrode 4 according to the need. In one example, the material of the top electrode 4 includes at least one of titanium nitride, tantalum titanium nitride, titanium, and tellurium. Examples of the thickness range of the top electrode 4 are as follows: 10-40nm.
The principle is described in detail below.
The relation between the oxygen vacancy generation probability in the memristor resistance change layer and the resistance change layer temperature can be referred to as the following formula:
wherein f is the oscillation frequency of oxygen atoms and electrons in the oxygen vacancies, E a Is the average activation energy of oxygen vacancy, alpha a Is the electric field enhancement factor, Z is the charge quantity, E is the unit charge quantity, E is the electric field strength, k B Is Boltzmann constant, T is the temperature of the resistive layer, dt is the differential of time, P g The probability of hole generation.
The formula is applicable to conductive filament type three-terminal memristors and integral memristors. From the above formula, the probability of generating oxygen vacancies in the resistive layer is proportional to the temperature, and the higher the temperature is, the larger the probability of generating oxygen vacancies is, so by heating the resistive layer, the electric field required for generating oxygen vacancies can be reduced, and the operating voltage of the memristor can be further reduced.
FIG. 4 shows the memristor initialization voltage and the low resistance switching voltage, which are respectively related to the highest temperature of the resistive layer, and it can be seen that the higher the resistive layer temperature is, the smaller the memristor initialization voltage and the low resistance switching voltage are, i.e. the smaller the voltage required for forming the conductive filament is.
FIG. 5 further shows the relationship between the highest temperature of the resistive layer and the voltage pulse (the voltage pulse is applied between the heating electrode 1 and the bottom electrode 2), T in FIG. 5 0 Is the highest temperature of the resistance change layer when no voltage pulse is applied, T 1 、T 2 And T 3 The highest temperature of the corresponding resistance change layer is obtained when voltage pulses with different time and amplitude are respectively applied. T is the same as 1 And T 2 The duration of the corresponding voltage pulses is deltat 1 But the amplitude value (one is V 1 One is V 2 ) Different; and T is 2 And T 3 The amplitude values of the corresponding voltage pulses are the same (all are V 2 ) But of different duration (Δt 3 >Δt 1 )。
Wherein FIG. 5 is a simulation result, T 0 At room temperature (300K), T 1 Is at 3832K, T 2 640K, T 3 981K; v (V) 1 1V, V 2 Is 2V, Δt 1 5ns, Δt 3 Is 10ns.
As can be seen by comparison, the higher the amplitude of the voltage pulse applied between the bottom electrode 2 and the heater electrode 1, the longer the pulse width, the higher the maximum temperature of the resistive layer 31. This is because the larger the voltage pulse amplitude is, the longer the pulse width is, the more heat is generated by the heat generating layer 13, and the faster the temperature response of the corresponding resistance change layer 31 is and the higher the maximum temperature is by heat conduction.
Based on the above formula and the relationship between the temperature and the voltage shown in fig. 4, in the embodiment of the present invention, the relationship between the generation rate of the oxygen vacancies of the resistive layer and the temperature of the resistive layer is utilized, and the resistive layer 31 is heated by the heating electrode 1, so that the generation probability of the oxygen vacancies can be improved, and further, the generation of the conductive filaments can be promoted for the conductive filament type memristor, so that the working voltage between the top electrode 4 and the bottom electrode 2 can be lower than that of the existing memristor, and therefore, the conductive filament type three-terminal memristor can be suitable for a low-voltage scenario.
While monolithic three-terminal memristors, while not producing conductive filaments, are also based on oxygen vacancies to achieve resistance changes. When the heating or the like is performed, the probability of oxygen vacancy generation can be increased. Further, since the drift rate of oxygen vacancies is affected by temperature, the increase in temperature increases the drift rate of oxygen vacancies, so that the migration capacity of oxygen vacancies can be improved by heating, and the time required for switching the resistance state can be shortened, for example, 100ns is required when not heating, and can be reduced to 20ns after heating.
The following describes a conductive filament type three-terminal memristor as an example.
The aforementioned mention of the heat generating layer 13 may be smaller in area than the memristor resistive layer 31, and if so, may also be beneficial for the directional formation of conductive filaments in the resistive layer of a conductive filament-type memristor. Referring now to the schematic diagram of the probability of forming conductive filaments and the positional relationship shown in fig. 7, the isothermal top plan view of the resistive switching layer shown in fig. 6 will be described:
the x-y plane in fig. 6 is a horizontal plane, that is, the upper surface or the lower surface of the resistive layer 31. The total of 5 isothermal surfaces on the horizontal plane are that the temperature from inside to outside is: t1, T2, T3, T4 and T5, the temperature value relationship is: t1> T2> T3> T4> T5.
Wherein T1 is 981K, T2 is 499K, T3 is 379K, T4 is 351K, T5 is 332K. FIG. 6 is a graph obtained based on the simulation result, in which a rectangular wave having a pulse width of 2V/10ns is applied.
Since the heat generating layer 13 has an area smaller than that of the memristor resistive layer 31, a portion of the area above it faces the resistive layer 31. The isothermal surface at which T1 is located in fig. 6 is the region of the resistive layer above the heat generating layer 13. Since the temperature T1 is highest, it is known that the temperature of the region corresponding to the upper portion of the heat generating layer 13 on the resistive layer 31 is higher than the temperature of the other regions of the resistive layer 31.
As can be seen in conjunction with fig. 7, in the x-y plane, there is a region of conductive filaments that has a significantly higher probability of forming than other regions of the resistive layer. This region is the region where the isothermal surface of T1 is located, that is, the region of the resistive layer above the heat generating layer 13 (may also be referred to as a heating region), where oxygen vacancies are more easily densely generated to form continuous conductive filaments, so that the fixed-point formation of conductive filaments can be achieved.
Fig. 7 corresponds to fig. 6, and is based on the same simulation result.
Therefore, when the memristor is programmed each time, the conductive filaments are more easily generated in a small area above the heat-generating layer 13, so that the formation position and the shape of the conductive filaments are relatively stable, and compared with the existing memristor formed relatively randomly by the conductive filaments, the characteristic deviation of the same memristor in multiple operations is smaller, and the consistency of the same memristor in multiple operations is improved.
In summary, in the embodiment of the invention, the area of the heat generating layer 13 is smaller than that of the memristor resistance changing layer 31, and the problem of poor consistency of the conventional conductive filament type memristor is solved.
Further, in other embodiments of the present invention, the orthographic projection of the heat generating layer 13 on the substrate 0 in all of the above embodiments is located at the center position of the target overlapping portion. The target overlapping portion is: the conductive layer 11, the bottom electrode 2 and the top electrode 4 are superimposed on the front projection of the substrate 0.
In one embodiment, referring to fig. 2, the heating electrode 1 in all the above embodiments further includes an insulating layer 14.
One side of the insulating layer 14 is in contact with the substrate 0, and the other side is in contact with the conductive layer 11 and the dielectric layer 12.
The heat-insulating layer 14 can reduce heat loss to the substrate 0 during heating, thereby improving the heating efficiency of the heat-generating layer 13.
The material of the insulating layer 14 can be flexibly selected by those skilled in the art as long as it is suitable for being provided on a substrate and has insulating properties. For example, silicon dioxide may be selected as the material for the thermal insulation layer 14.
In one example, the thickness of the insulating layer 14 may be illustratively greater than 300nm.
Further, the heating electrode 1 in all the above embodiments further includes a first adhesive layer 15.
The first adhesive layer 15 is disposed between the conductive layer 11 and the insulating layer 14. By providing the first adhesive layer 15, the stability of the device structure can be increased. The thickness range of the first adhesive layer 15 may be exemplified by: 2-10nm.
In one example, the first adhesion layer 15 is a titanium adhesion layer. Of course, other materials that can be used to adhere the conductive layer 11 to the insulating layer 14 may be selected by those skilled in the art.
In another embodiment, the heater electrode 1 of all the above embodiments may further comprise a second adhesive layer 16.
A second adhesion layer 16 is arranged between the dielectric layer 12 and the bottom electrode 2. The heat generating layer 13 is connected to the bottom electrode 2 through the second adhesive layer 16. In addition to increasing the stability of the device structure, the second adhesion layer should also be electrically conductive. The thickness range of the second adhesive layer 16 may be exemplified by: 2-10nm.
One skilled in the art can flexibly design the material of the second adhesion layer, for example, the second adhesion layer 16 is a titanium adhesion layer, and of course, other materials that can achieve adhesion between the dielectric layer 12 and the bottom electrode 2 and have conductivity properties may be selected.
Referring to fig. 10, a process flow of preparing a conductive filament type three-terminal memristor is further described below by taking a material of the resistive layer 31 as hafnium oxide, a material of the heat-generating layer 13 as a stack of titanium nitride and tantalum nitride, a material of the conductive layer 11 and the bottom electrode 2 as platinum, a material of the top electrode 4 as titanium nitride, and the like as an example.
In a first step, a layer of silicon dioxide having a thickness of 1 μm is thermally oxidized on a substrate 0 made of silicon as the heat-insulating layer 14.
Step two, photoetching is carried out on the heat preservation layer 14, and a physical vapor deposition and stripping process is utilized to sequentially generate a first titanium adhesion layer and a first platinum film with the thicknesses of 20 nanometers and 80 nanometers respectively from bottom to top; wherein a first titanium adhesion layer is used as the first adhesion layer 15 and a first platinum thin film is used as the conductive layer 11.
And thirdly, generating a layer of silicon dioxide (which can be called a dielectric layer precursor) with the thickness of 50 nanometers by utilizing plasma enhanced chemical vapor deposition.
The dielectric layer precursor covers the conductive layer 11 and the insulating layer 14, which will result in the dielectric layer 12 described above after subsequent processing steps.
And fourthly, forming a window on the dielectric layer precursor by utilizing electron beam lithography and reactive ion etching.
And fifthly, filling the window by utilizing a titanium nitride layer with the thickness of 50 nanometers by physical vapor deposition.
Step six, removing the titanium nitride layer outside the window by electron beam lithography and reactive ion etching to form a heat generating layer 13 penetrating the dielectric layer precursor and connected to the conductive layer 11.
The product obtained in step six may be referred to as an intermediate preparation.
And step seven, forming a bottom electrode pattern on the intermediate preparation through photoetching, sequentially generating a second titanium adhesion layer and a second platinum film with the thicknesses of 5 nanometers and 40 nanometers from bottom to top on the intermediate preparation with the bottom electrode pattern by physical vapor deposition, and obtaining the bottom electrode 2 through a stripping process.
Wherein a second titanium adhesion layer remaining on the intermediate preparation after the treatment using the lift-off process acts as the aforementioned second adhesion layer 16; the second platinum film, which remains on the intermediate preparation after the treatment using the lift-off process, serves as the bottom electrode 2.
Step eight, using atomic layer deposition, a 5 nm hafnium oxide film is coated on the upper surface of the intermediate preparation containing the bottom electrode 2.
The hafnium oxide film is then passed through a manager to act as the aforementioned resistive layer 31. The hafnium oxide film may also be referred to as a resistive layer precursor.
And step nine, generating a titanium nitride film with the thickness of 80 nanometers on the resistive layer precursor by physical vapor deposition.
And step ten, processing the titanium nitride film on the resistive layer precursor by utilizing photoetching and reactive ion etching to obtain the top electrode 4.
Specifically, a top electrode pattern may be prepared on a titanium nitride film using a photoresist, then titanium nitride not covered by the top electrode pattern is etched away using reactive ions, and then the photoresist is removed, thereby obtaining the top electrode 4.
Step eleven, the conductive portion 20 of the bottom electrode 2 and the conductive portion 110 of the heating electrode 1 are prepared by photolithography and reactive ion etching, respectively.
Specifically, photoresist may be used to form a conductive portion pattern on the resistive layer precursor, where the conductive portion pattern has a hollowed-out area, which may be referred to as a first hollowed-out area and a second hollowed-out area, where the first hollowed-out area is located above the bottom electrode 2 and the second hollowed-out area is located above the conductive layer 11.
Removing the precursor material of the resistive layer in the first hollowed-out area by utilizing reactive ion etching to expose a part of the bottom electrode 2, thereby obtaining the conductive part 20;
the dielectric layer precursor material and the resistive layer precursor material in the second hollowed-out region are removed by reactive ion etching, so that a portion of the conductive layer 11 is exposed, thereby obtaining the conductive portion 110.
After the eleventh step, the dielectric layer 12, the resistive layer 31, the conductive portion 20, and the conductive portion 110 are obtained.
The structure of the integral three-terminal memristor, the manufacturing process and the like can refer to the conductive filament type three-terminal memristor, and only when the resistive switching structure 3 is prepared, the dielectric layer 32 is prepared in addition to the resistive switching layer 31, which is not described herein.
In summary, the three-terminal memristor and the manufacturing and operating methods of the three-terminal memristor provided in the above embodiments can solve the problem that the existing conductive filament-type memristor and the existing integral-type memristor have higher working voltage and the problem that the integral-type memristor has slower resistance state transformation; in addition, in some embodiments of the invention, the problem of poor consistency of the existing conductive filament memristors is also solved.
In the present specification, each embodiment is described in a progressive manner, and each embodiment is mainly described in a different point from other embodiments, and identical and similar parts between the embodiments are all enough to refer to each other. For the system disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant points refer to the description of the method section.
The principles and embodiments of the present invention have been described herein with reference to specific examples, the description of which is intended only to assist in understanding the methods of the present invention and the core ideas thereof; also, it is within the scope of the present invention to be modified by those of ordinary skill in the art in light of the present teachings. In view of the foregoing, this description should not be construed as limiting the invention.
Claims (10)
1. A three-terminal memristor with a heater electrode, the three-terminal memristor comprising: the device comprises a substrate, a heating electrode, a bottom electrode, a resistance change structure and a top electrode, wherein the heating electrode, the bottom electrode, the resistance change structure and the top electrode are sequentially arranged on the substrate from bottom to top; wherein the resistive structure at least comprises a resistive layer; the heating electrode includes:
a conductive layer disposed on the substrate;
a dielectric layer; the conductive layer is partially covered by the dielectric layer, and a portion of the conductive layer exposed outside the dielectric layer serves as a conductive portion electrically connected to the outside; the dielectric layer is at least used for isolating the bottom electrode and the conductive layer;
the heat generating layer is arranged in the dielectric layer in a penetrating way and is respectively connected with the conducting layer and the bottom electrode; the heat generating layer is used for generating heat when electricity is supplied between the bottom electrode and the conductive part of the conductive layer so as to heat the resistance change layer.
2. The three-terminal memristor with heating electrode of claim 1, wherein the heat-generating layer has an area smaller than an area of the resistive-switching layer.
3. The three-terminal memristor with heating electrode of claim 1, wherein the orthographic projection of the heat-generating layer on the substrate is located at a central position of a target overlap portion; the target overlapping portion is: and the overlapping part of the conducting layer, the bottom electrode and the top electrode, which are orthographic projected on the substrate.
4. The three-terminal memristor with heating electrode of claim 1, wherein the resistance value of the heat-generating layer is greater than the conductive layer and bottom electrode.
5. The three-terminal memristor with heating electrode of claim 1, wherein the material of the heat-generating layer comprises at least one of tungsten, titanium nitride, and tantalum nitride.
6. The three-terminal memristor with heating electrode of claim 1, wherein the heating electrode further comprises:
a heat preservation layer; one surface of the heat preservation layer is contacted with the substrate, and the other surface of the heat preservation layer is contacted with the conductive layer and the dielectric layer.
7. The three-terminal memristor with heating electrode of any one of claims 1-6, wherein the three-terminal memristor is embodied as a monolithic three-terminal memristor, and the resistance change structure further comprises a dielectric layer.
8. A three-terminal memristor with a heater electrode, comprising: the device comprises a substrate, a heating electrode, a bottom electrode, a resistance change structure and a top electrode, wherein the heating electrode, the bottom electrode, the resistance change structure and the top electrode are sequentially arranged on the substrate from bottom to top; wherein the resistive structure at least comprises a resistive layer; the heating electrode includes:
a conductive layer disposed on the substrate;
a dielectric layer; the dielectric layer is at least used for isolating the bottom electrode and the conductive layer;
the heat generating layer is arranged in the dielectric layer in a penetrating way and is respectively connected with the conducting layer and the bottom electrode; the heat generating layer is used for generating heat when electricity is supplied between the bottom electrode and the conductive layer so as to heat the resistance change layer.
9. A method of operation applied to the three-terminal memristor of any one of claims 1-8, the method of operation comprising:
resistance state switching operation:
applying a voltage or current pulse between the bottom electrode and the heating electrode so that the temperature of the resistive switching structure above the heat generating layer reaches and remains within a preset range;
applying a positive voltage pulse between the top electrode and the bottom electrode when switching from a high resistance state to a low resistance state;
when switching from the low resistance state to the high resistance state, a negative voltage pulse is applied between the top electrode and the bottom electrode.
10. A method of fabricating a three-terminal memristor with a heater electrode, the method comprising:
preparing a conductive layer on a substrate;
preparing a dielectric layer on the conductive layer;
manufacturing a window in the dielectric layer, and filling a heating material in the window to form a heat generating layer penetrating through the dielectric layer to obtain an intermediate preparation;
preparing a bottom electrode on the intermediate preparation; wherein the bottom electrode is isolated from the conductive layer by the dielectric layer; the heat generating layer is respectively connected with the conducting layer and the bottom electrode;
preparing a resistive switching structure on an intermediate preparation having a bottom electrode;
and preparing a top electrode on the resistive structure.
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