CN116366899A

CN116366899A - Video clock generation method and device

Info

Publication number: CN116366899A
Application number: CN202310335582.8A
Authority: CN
Inventors: 殷礼权; 刘伟
Original assignee: Hongjing Microelectronics Technology Co ltd
Current assignee: Hongjing Microelectronics Technology Co ltd
Priority date: 2023-03-30
Filing date: 2023-03-30
Publication date: 2023-06-30

Abstract

The invention belongs to the technical field of multimedia, and particularly relates to a video clock generation method and device, wherein the method comprises the following steps: acquiring a clock to be adjusted and a basic clock; calculating a frequency compensation difference value according to a clock to be adjusted and a basic clock; calculating a target compensation parameter according to the reference compensation parameter and the frequency compensation difference value; shaping the clock to be adjusted according to the target compensation parameter to obtain a shaped clock; if the frequency difference value between the shaping clock and the basic clock is in a preset frequency range, determining the shaping clock as a target video clock; and if the frequency difference between the shaping clock and the basic clock is out of the preset frequency range, taking the shaping clock as a new clock to be adjusted, and returning to execute the step of calculating the frequency compensation difference of the round according to the clock to be adjusted and the basic clock. According to the embodiment of the disclosure, the relatively stable video clock can be generated under the condition that the proportional parameter fluctuates and changes in the actual transmission process of the signal source.

Description

Video clock generation method and device

Technical Field

The invention belongs to the technical field of multimedia, and particularly relates to a video clock generation method and device.

Background

A Display interface (DP) is a connection interface for transmitting a signal containing a video source to a Display, where the signal source transmitted by the DP includes a signal related to a video clock and the video source, and the video clock is used as a play time reference of each video frame in the video source. The DP signal source contains a proportion parameter which is not the video clock, but expresses the proportion relation between the signal clock and the video clock, and then the video clock is obtained through processing according to the proportion parameter.

However, in the actual transmission process of the signal source, the proportion parameters are fluctuated and changed in real time, if the proportion parameters are jumped greatly, the obtained video clock is jumped greatly, so that the video clock corresponding to the instant of the jump of the proportion parameters is jumped equally, and the video source is abnormal in playing.

Disclosure of Invention

The invention provides a video clock generation method and a video clock generation device, which are used for solving the problem that when a conventional signal receiving platform generates a video clock in a signal source, the obtained video clock also generates jump due to jump of a proportion parameter.

In a first aspect, the present disclosure provides a video clock generation method, the method comprising:

acquiring a clock to be adjusted and a basic clock;

calculating a frequency compensation difference value according to the clock to be adjusted and the basic clock;

calculating a target compensation parameter according to a reference compensation parameter and the frequency compensation difference value, wherein when the clock to be adjusted is a history shaping clock, the reference compensation parameter is a compensation parameter for adjusting the clock to be adjusted, the reference compensation parameter is calculated according to an adjusting base number, and the adjusting base number is calculated according to a system clock;

shaping the clock to be adjusted according to the target compensation parameter to obtain a shaped clock;

if the frequency difference value between the shaping clock and the basic clock is in a preset frequency range, determining the shaping clock as a target video clock;

and if the frequency difference value between the shaping clock and the basic clock is out of the preset frequency range, taking the shaping clock as a new clock to be adjusted, and returning to execute the step of calculating the frequency compensation difference value of the round according to the clock to be adjusted and the basic clock.

Optionally, before the obtaining the clock to be adjusted and the base clock, the method further includes:

after receiving a signal source, processing the signal source to obtain a proportion parameter and an analysis clock;

calculating to obtain an initial video clock according to the proportion parameter and the analysis clock, and taking the initial video clock as a first clock to be adjusted;

and carrying out frequency division processing on the analysis clock to obtain the basic clock.

Optionally, the video clock generating method further includes:

calculating according to the initial video clock and the system clock to obtain an adjustment base;

calculating according to the frequencies of the initial video clock and the basic clock to obtain an initial frequency compensation difference value;

and adding the adjustment base and the initial frequency compensation difference value to obtain an initial compensation parameter.

Optionally, when the clock to be adjusted is the first clock to be adjusted, the reference compensation parameter is the initial compensation parameter.

Optionally, the calculating the target compensation parameter according to the reference compensation parameter and the frequency compensation difference value includes:

and adding the reference compensation parameter and the frequency compensation difference value to obtain the target compensation parameter.

and subtracting a synchronous frequency difference from the sum of the reference compensation parameter and the frequency compensation difference to obtain the target compensation parameter, wherein the synchronous frequency difference is calculated according to a real-time synchronous signal corresponding to a signal source and a preset video line synchronous signal.

Optionally, when the signal source includes video synchronization indication information, the method further includes:

analyzing the signal source to obtain the real-time synchronous signal;

and calculating the difference value of the real-time synchronizing signal and the preset video line synchronizing signal to obtain the synchronizing frequency difference.

In a second aspect, the present disclosure provides a video clock generating apparatus, comprising:

the acquisition module is used for acquiring the clock to be adjusted and the basic clock;

the calculation module is used for calculating a frequency compensation difference value according to the clock to be adjusted and the basic clock;

the calculation module is further configured to calculate a target compensation parameter according to a reference compensation parameter and the frequency compensation difference value, and when the clock to be adjusted is a history shaping clock, the reference compensation parameter is a compensation parameter for adjusting the clock to be adjusted, the reference compensation parameter is calculated according to an adjustment base, and the adjustment base is calculated according to a system clock;

the adjusting module is used for shaping the clock to be adjusted according to the target compensation parameter to obtain a shaped clock;

the determining module is used for determining the shaping clock as a target video clock if the frequency difference value of the shaping clock and the basic clock is in a preset frequency range;

and the execution module is used for taking the shaping clock as a new clock to be adjusted if the frequency difference value between the shaping clock and the basic clock is out of the preset frequency range, and returning to execute the step of calculating the frequency compensation difference value of the round according to the clock to be adjusted and the basic clock again.

In a third aspect, the present disclosure provides an electronic device comprising:

at least one processor; and a memory communicatively coupled to the at least one processor;

wherein the memory stores one or more computer programs executable by the at least one processor, one or more of the computer programs being executable by the at least one processor to enable the at least one processor to perform a video clock generation method as described above.

In a fourth aspect, the present disclosure provides a computer readable storage medium having stored thereon a computer program which, when executed by a processor, implements a video clock generation method as described above.

According to the video clock generation method provided by the invention, a clock to be adjusted and a basic clock are obtained, a frequency compensation difference value is calculated according to the clock to be adjusted and the basic clock, a target compensation parameter is calculated according to a reference compensation parameter and the frequency compensation difference value, the clock to be adjusted is shaped according to the target compensation parameter, a shaped clock is obtained, if the frequency difference value between the shaped clock and the basic clock is in a preset frequency range, the shaped clock is determined to be the target video clock, if the frequency difference value between the shaped clock and the basic clock is out of the preset frequency range, the shaped clock is taken as a new clock to be adjusted, and the step of calculating the frequency compensation difference value of the round according to the clock to be adjusted and the basic clock is executed in a returning mode. The basic clock is obtained by frequency division processing based on an analysis clock, the analysis clock is analyzed by a signal source, and the system clock is a stable and unchanged clock, can be a crystal oscillator clock of the system, and can also be any other fixed clock. Therefore, the method for generating the video clock takes the generated shaping clock with the frequency difference value within the preset range as the target video clock, and uses the system clock in the video clock generating process, thereby ensuring the similarity of the frequency of the target video clock and the frequency of the base clock, ensuring the stability of the target video clock and further ensuring the normal play of the video source.

It should be understood that the description in this section is not intended to identify key or critical features of the embodiments of the disclosure, nor is it intended to be used to limit the scope of the disclosure. Other features of the present disclosure will become apparent from the following specification.

Drawings

Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The drawings are only for purposes of illustrating the preferred embodiments and are not to be construed as limiting the invention. Also, like reference numerals are used to designate like parts throughout the figures. In the drawings:

fig. 1 shows a flowchart of a video clock generation method provided by the invention.

Fig. 2 shows a circuit design diagram of a video clock generating method provided by the invention.

Fig. 3 shows a schematic diagram of a video clock generating apparatus provided by the present invention.

Fig. 4 shows a schematic structural diagram of an electronic device provided by the invention.

Detailed Description

For a better understanding of the technical solutions of the present disclosure, exemplary embodiments of the present disclosure will be described below with reference to the accompanying drawings, in which various details of the embodiments of the present disclosure are included to facilitate understanding, and they should be considered as merely exemplary. Accordingly, one of ordinary skill in the art will recognize that various changes and modifications of the embodiments described herein can be made without departing from the scope and spirit of the present disclosure. Also, descriptions of well-known functions and constructions are omitted in the following description for clarity and conciseness.

Embodiments of the disclosure and features of embodiments may be combined with each other without conflict.

As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. The terms "connected" or "connected," and the like, are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and the present disclosure, and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

The invention relates to a multimedia technology, in particular to a method for generating a video clock. In general, a Video clock (video_clock) generates an analysis clock by analyzing a signal source, and then divides the analysis clock to obtain a nonlinear clock, and the nonlinear clock is shaped into a linear clock, which is the Video clock. Based on this, in practical implementation, the present technology generally uses a nonlinear clock as a reference for verifying whether the video clock satisfies the system requirements.

For example, the parse clock may be implemented as link_clk. The nonlinear clock may be implemented as dll_clk.

The embodiment of the disclosure provides a video clock generation method, namely, a basic clock is obtained by analyzing and dividing a transmitted signal source, an initial video clock and target compensation parameters are obtained by system calculation, and the initial video clock is adjusted based on the target compensation parameters to obtain a target video clock with frequency approaching to the basic clock. The invention can generate the target video clock with the frequency approaching to the basic clock frequency of the signal source through the video clock generation technology.

Exemplary video clock generation methods illustrated by the present invention may be described below.

Referring to fig. 1, fig. 1 shows a flowchart of a video clock generating method according to an embodiment of the present invention, where the method includes:

step S11, obtaining a clock to be adjusted and a basic clock.

The clock to be adjusted may be a video clock to be output, and the video clock does not meet the output condition and needs to be adjusted continuously, so this example is called "clock to be adjusted". The base clock may be a nonlinear clock prior to shaping of the video clock. In connection with the above description, since the nonlinear clock is a reference for determining whether or not a clock signal to be output satisfies an output condition, the present embodiment refers to the nonlinear clock as a base clock.

In some implementations, the first video clock generated by the system, i.e., the initial video clock, typically does not meet the output condition, then the initial video clock is the first clock to be adjusted.

In another implementation manner, after any round of adjustment, the video clock which does not meet the condition is usually used as the clock to be adjusted of the next round, and the video clock which does not meet the condition is the clock to be adjusted, wherein the frequency difference between the video clock and the base clock after the previous round of adjustment is located outside the preset frequency range.

The initial video clock is obtained by processing a received signal source to obtain a proportion parameter and a parsing clock, and further calculating according to the proportion parameter and the parsing clock. The basic clock is obtained by frequency division processing of the analysis clock.

Step S12, calculating a frequency compensation difference value according to the clock to be adjusted and the basic clock.

The frequency compensation difference value is used for calculating a compensation parameter so as to compensate the frequency of the clock to be adjusted through the compensation parameter, so that the clock to be adjusted is adjusted, and the reshaped clock obtained after adjustment meets the output condition.

Step S13, calculating a target compensation parameter according to the reference compensation parameter and the frequency compensation difference value.

Optionally, when the clock to be adjusted is a history shaping clock, the reference compensation parameter is a compensation parameter obtained by adjusting the clock to be adjusted, the reference compensation parameter is obtained by calculating according to an adjustment base, and the adjustment base is obtained by calculating according to the initial video clock and the system clock. According to the description of the clock to be adjusted in step S11, the history shaping clock refers to the shaping clock that is obtained after each round of adjustment of the clock to be adjusted and does not meet the output condition and needs to be adjusted continuously.

Optionally, according to the description of the clock to be adjusted in step S11, the clock to be adjusted may also be the initial video clock, and the reference compensation parameter of the previous round does not exist, based on this, the embodiment may use the initial compensation parameter as the reference compensation parameter for adjusting the initial video clock. Optionally, when the clock to be adjusted is the first clock to be adjusted, the reference compensation parameter is the initial compensation parameter.

Optionally, after calculating an initial video clock, an adjustment base may be calculated according to the initial video clock and the system clock, and the adjustment base and the initial frequency compensation difference value may be added to obtain an initial compensation parameter.

The system clock may be, for example, a system crystal clock. It should be appreciated that the system clock may also be any other stable and constant clock signal. Therefore, according to the video clock generation method, before the video clock to be output (namely, the clock to be adjusted) is subjected to frequency compensation, the system clock is used for calculating the compensation parameter, and the accuracy of the compensation parameter can be ensured because the system clock is a stable and invariable clock of the system, so that the video clock to be output can be stably and accurately compensated, and the stability of the obtained target video clock can be ensured.

And step S14, shaping the clock to be adjusted according to the target compensation parameter to obtain a shaped clock.

The shaping comprises adjusting the frequency of the clock to be adjusted according to the target compensation parameter. The shaping clock is a video clock obtained after shaping the clock to be adjusted.

The dll_clk and the video_clk are input to a frequency comparator module, and the frequency comparator module calculates a signed clock difference, that is, a frequency compensation difference, so that whether the video_clk frequency is larger or smaller than the dll_clk frequency can be determined, and the adjustment direction of the clock to be adjusted can be determined according to the comparison result. Optionally, the shaping mode may include adjusting a preset frequency trimming interval period or frequency trimming once.

Optionally, the frequency fine adjustment interval period or the frequency fine adjustment once size can be configured in a customized manner.

For example, the frequency fine adjustment interval period represents how often the frequency compensation difference is updated, and the user can customize several interval periods to correspond to different frequency difference ranges.

Illustratively, the frequency fine-tuning once size represents an adjusted step size, and the user can customize a number of step sizes corresponding to different frequency difference ranges.

And S15, if the frequency difference value between the shaping clock and the basic clock is in a preset frequency range, determining the shaping clock as a target video clock.

The frequency difference between the shaping clock and the basic clock is within a preset frequency range, which indicates that the shaping clock is a video clock meeting a stable condition, that is, the shaping clock can be used as a target video clock meeting an output condition.

And S16, if the frequency difference value between the shaping clock and the basic clock is out of the preset frequency range, taking the shaping clock as a new clock to be adjusted, and returning to execute the step of calculating the frequency compensation difference value of the round according to the clock to be adjusted and the basic clock.

The difference between the frequencies of the shaping clock and the basic clock is outside the preset frequency range, which indicates that the shaping clock still does not meet the stable condition, and then the shaping clock needs to be continuously adjusted. Based on the above, the shaping clock can be used as a new clock to be adjusted, and the adjustment process is repeatedly performed until the target video clock meeting the output condition is obtained.

It is noted that step S13 to step S16 are a closed-loop clock feedback adjustment process, the frequency compensation difference is calculated between the base clock obtained by frequency division and the clock to be adjusted, whether the shaping clock frequency is larger or smaller than the base clock frequency is determined according to the frequency compensation difference, then the target compensation parameter is obtained according to the reference compensation parameter and the frequency compensation difference, and the frequency fine adjustment of the clock to be adjusted is reduced or increased based on the target compensation parameter until the clock to be adjusted meets the output condition.

The implementation manner corresponding to fig. 1 is only one exemplary implementation manner of the present invention, and in other implementation manners, if the system has a requirement for detecting stable synchronization of the video clock, the embodiment of the present invention may further include: and subtracting the synchronous frequency difference from the sum of the reference compensation parameter and the frequency compensation difference to obtain the target compensation parameter.

The synchronization frequency difference is calculated according to a real-time synchronization signal corresponding to the signal source and a preset video line synchronization signal. Specifically, analyzing the signal source to obtain the real-time synchronous signal; and calculating the difference value of the real-time synchronizing signal and the preset video line synchronizing signal to obtain the synchronizing frequency difference.

By adopting the implementation mode, the obtained target compensation parameters comprise the video line synchronization factors, and further, the video clock adjusted according to the target compensation parameters refers to the video line synchronization factors, so that the obtained target video clock can also meet the requirement of realizing video line synchronization under the condition of meeting the stability condition.

Referring to fig. 2, fig. 2 shows a circuit design diagram of a video clock generation method of the present invention, which can support the operation of the video clock generation method illustrated in fig. 1.

As shown in fig. 2, the circuit design diagram of the video clock generation method may include: a parsing module 21, a digital frequency dividing module 22, a frequency comparator 23, an analog phase locked loop (Phase Locked Loop, PLL) 24 and a line synchronization signal (Htotal) comparator 25.

The parsing module 21 is configured to parse a signal source, obtain a scale parameter and a parsing clock of the signal source, and input the scale parameter and the parsing clock to the digital frequency division module 22. In this example, the signal source is, for example, a DP signal source, and the analysis clock is, for example, link_clk.

The digital frequency division module 22 is configured to divide the analysis clock (link_clk) analyzed by the analysis module 21 to obtain a base clock (dll_clk) (i.e. the implementation of step S11 above), and input the link_clk to the frequency comparator 23.

The frequency comparator 23 is configured to compare whether the frequency difference between the base clock and the clock to be adjusted is within a preset frequency range (i.e. the implementation of steps S12 to S15). In this example, the clock to be adjusted is video_clk input to the frequency comparator in fig. 2.

In other implementations, the frequency comparator 23 is further configured to calculate a frequency compensation difference, i.e. an m_fn value compensation, according to the synchronous frequency difference, the dll_clk, and the video_clk calculated in the previous round, and input the m_fn value compensation to the analog phase-locked loop 24. The implementation of the frequency comparator 23 to calculate the compensation of the value m_fn is described in detail in the above step S12, and will not be described in detail here.

The analog pll 24 is configured to calculate a target compensation parameter according to the value compensation of m_fn, the initial value of m_fn (i.e. the adjustment base) and the crystal oscillator (i.e. the system clock), and then shape the clock to be adjusted according to the target compensation parameter to obtain a shaped clock (i.e. the implementation manners of steps S12 to S14). The implementation manner of the analog pll 24 to calculate the target compensation parameter according to the value of m_fn, the initial value of m_fn, and the crystal oscillator is described in step S13, which is not described in detail herein.

Fig. 2 is, for example, a system with stable Video line synchronization requirements, where the real-time Htotal value in fig. 2 refers to the real-time synchronization signal, and the reconstructed Video Htotal value refers to the preconfigured Video line synchronization signal. The line synchronization signal comparator 25 is then used to calculate the difference between the real time Htotal value and the reconstructed Video Htotal value, i.e. the synchronization frequency difference between the real time synchronization signal and the Video line synchronization signal, and the synchronization frequency difference is input to the frequency comparator 23.

The invention also provides a module/unit for executing the software, the hardware or the combination of the software and the hardware of the implementation steps corresponding to the implementation steps.

Fig. 3 shows a schematic diagram of a video clock generating apparatus provided by the present invention. Referring to fig. 3, a video clock generating apparatus includes: the device comprises an acquisition module 31, a calculation module 32, an adjustment module 33, a determination module 34 and an execution module 35. Wherein each unit module is configured to perform part or all of the steps of the video clock generation method shown in fig. 1.

For example, an obtaining module 31 is configured to obtain a clock to be adjusted and a base clock; the calculating module 32 is configured to calculate a frequency compensation difference according to the clock to be adjusted and the base clock, and calculate a target compensation parameter according to a reference compensation parameter and the frequency compensation difference; the adjusting module 33 is configured to shape the clock to be adjusted according to the target compensation parameter, so as to obtain a shaped clock; a determining module 34, configured to determine the shaped clock as a target video clock if a frequency difference between the shaped clock and the base clock is within a preset frequency range; and the execution module 35 is configured to return to execute the step of calculating the frequency compensation difference value of the present round according to the clock to be adjusted and the base clock again by taking the shaping clock as a new clock to be adjusted if the frequency difference value of the shaping clock and the base clock is outside the preset frequency range.

Specifically, the details of the foregoing embodiments are not described herein.

Fig. 4 shows a schematic structural diagram of an electronic device according to the present invention, and the embodiment of the present invention is not limited to the specific implementation of the electronic device. Referring to fig. 4, the electronic device includes:

at least one processor 401; a memory 402 communicatively coupled to the at least one processor; a communication interface 403; and a communication bus 404.

Wherein:

processor 401, memory 402, and communication interface 403 accomplish communication with each other via communication bus 404.

A communication interface 403 for interaction with other devices such as an analog PLL module with a frequency comparator or other module, etc.

The memory 402 stores one or more computer programs 405 executable by the at least one processor 401, the one or more computer programs 405 being executable by the at least one processor 401 to enable the at least one processor 401 to perform the operations corresponding to the video clock generation method embodiments described above.

Embodiments of the present application provide a non-volatile computer storage medium storing at least one executable instruction that may perform the video clock generation method of any of the above-described method embodiments. The executable instructions may be particularly useful for causing a processor to perform the operations corresponding to the method embodiments described above.

Those of ordinary skill in the art will appreciate that all or some of the steps, systems, functional modules/units in the apparatus, and methods disclosed above may be implemented as software, firmware, hardware, and suitable combinations thereof. In a hardware implementation, the division between the functional modules/units mentioned in the above description does not necessarily correspond to the division of physical components; for example, one physical component may have multiple functions, or one function or step may be performed cooperatively by several physical components. Some or all of the physical components may be implemented as software executed by a processor, such as a central processing unit, digital signal processor, or microprocessor, or as hardware, or as an integrated circuit, such as an application specific integrated circuit. Such software may be distributed on computer-readable storage media, which may include computer storage media (or non-transitory media) and communication media (or transitory media).

The term computer storage media includes both volatile and nonvolatile, removable and non-removable media implemented in any method or technology for storage of information such as computer readable program instructions, data structures, program modules or other data, as known to those skilled in the art. Computer storage media includes, but is not limited to, random Access Memory (RAM), read Only Memory (ROM), erasable Programmable Read Only Memory (EPROM), static Random Access Memory (SRAM), flash memory or other memory technology, portable compact disc read only memory (CD-ROM), digital Versatile Discs (DVD) or other optical disc storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other medium which can be used to store the desired information and which can be accessed by a computer. Furthermore, as is well known to those of ordinary skill in the art, communication media typically embodies computer readable program instructions, data structures, program modules or other data in a modulated data signal such as a carrier wave or other transport mechanism and may include any information delivery media.

The computer readable program instructions described herein may be downloaded from a computer readable storage medium to a respective computing/processing device or to an external computer or external storage device over a network, such as the internet, a local area network, a wide area network, and/or a wireless network. The network may include copper transmission cables, fiber optic transmissions, wireless transmissions, routers, firewalls, switches, gateway computers and/or edge servers. The network interface card or network interface in each computing/processing device receives computer readable program instructions from the network and forwards the computer readable program instructions for storage in a computer readable storage medium in the respective computing/processing device.

Computer program instructions for performing the operations of the present disclosure can be assembly instructions, instruction Set Architecture (ISA) instructions, machine-related instructions, microcode, firmware instructions, state setting data, or source or object code written in any combination of one or more programming languages, including an object oriented programming language such as Smalltalk, c++ or the like and conventional procedural programming languages, such as the "C" programming language or similar programming languages. The computer readable program instructions may be executed entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer or entirely on the remote computer or server. In the case of a remote computer, the remote computer may be connected to the user's computer through any kind of network, including a Local Area Network (LAN) or a Wide Area Network (WAN), or may be connected to an external computer (for example, through the Internet using an Internet service provider). In some embodiments, aspects of the present disclosure are implemented by personalizing electronic circuitry, such as programmable logic circuitry, field Programmable Gate Arrays (FPGAs), or Programmable Logic Arrays (PLAs), with state information of computer readable program instructions, which can execute the computer readable program instructions.

The computer program product described herein may be embodied in hardware, software, or a combination thereof. In an alternative embodiment, the computer program product is embodied as a computer storage medium, and in another alternative embodiment, the computer program product is embodied as a software product, such as a software development kit (Software Development Kit, SDK), or the like.

Various aspects of the present disclosure are described herein with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems) and computer program products according to embodiments of the disclosure. It will be understood that each block of the flowchart illustrations and/or block diagrams, and combinations of blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer-readable program instructions.

These computer readable program instructions may be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions/acts specified in the flowchart and/or block diagram block or blocks. These computer readable program instructions may also be stored in a computer readable storage medium that can direct a computer, programmable data processing apparatus, and/or other devices to function in a particular manner, such that the computer readable medium having the instructions stored therein includes an article of manufacture including instructions which implement the function/act specified in the flowchart and/or block diagram block or blocks.

The computer readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other devices to cause a series of operational steps to be performed on the computer, other programmable apparatus or other devices to produce a computer implemented process such that the instructions which execute on the computer, other programmable apparatus or other devices implement the functions/acts specified in the flowchart and/or block diagram block or blocks.

The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods and computer program products according to various embodiments of the present disclosure. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of instructions, which comprises one or more executable instructions for implementing the specified logical function(s). In some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.

Example embodiments have been disclosed herein, and although specific terms are employed, they are used and should be interpreted in a generic and descriptive sense only and not for purpose of limitation. In some instances, it will be apparent to one skilled in the art that features, characteristics, and/or elements described in connection with a particular embodiment may be used alone or in combination with other embodiments unless explicitly stated otherwise. It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the scope of the disclosure as set forth in the appended claims.

Claims

1. A video clock generation method, the method comprising:

acquiring a clock to be adjusted and a basic clock;

2. The method of claim 1, further comprising, prior to the acquiring the clock to be adjusted and the base clock:

3. The method as recited in claim 1, further comprising:

calculating to obtain an initial frequency compensation difference value according to the frequency of the initial video clock and the frequency of the basic clock;

4. The method of claim 3, wherein the step of,

when the clock to be adjusted is the first clock to be adjusted, the reference compensation parameter is the initial compensation parameter.

5. The method of claim 1, wherein said calculating a target compensation parameter based on a reference compensation parameter and said frequency compensation difference comprises:

6. The method of claim 1, wherein said calculating a target compensation parameter based on a reference compensation parameter and said frequency compensation difference comprises:

7. The method of claim 6, wherein when video synchronization indication information is included in the signal source, further comprising:

analyzing the signal source to obtain the real-time synchronous signal;

8. A video clock generating apparatus, the apparatus comprising:

9. An electronic device, comprising:

wherein the memory stores one or more computer programs executable by the at least one processor, one or more of the computer programs being executable by the at least one processor to enable the at least one processor to perform the method of any one of claims 1 to 7.

10. A computer readable storage medium, on which a computer program is stored, which, when being executed by a processor, implements the method according to any one of claims 1 to 7.