CN116366032A

CN116366032A - Latch circuit, integrated circuit, and electronic device

Info

Publication number: CN116366032A
Application number: CN202310252245.2A
Authority: CN
Inventors: 唐超; 孔剑平; 胡楠; 王琪
Original assignee: Zhejiang Nanometer Technology Co ltd
Current assignee: Zhejiang Nanometer Technology Co ltd
Priority date: 2023-03-09
Filing date: 2023-03-09
Publication date: 2023-06-30

Abstract

The invention provides a latch circuit, an integrated circuit and an electronic device, the latch circuit comprising: a first flip-flop, a second flip-flop, a first latch, and a second latch; the first trigger is connected with the input end of the second trigger through a first latch and a second latch, the first latch is connected with the second latch through a non-critical path, and the second latch is connected with the first latch through a critical path; the enable terminal of each first latch and the enable terminal of each second latch are for receiving a clock signal, the duration of which is set to a high level being different from the duration of a low level. The latches with high level opening and low level opening are arranged in a crossing mode, so that clock borrowing can be adopted in a circuit with critical paths and non-critical paths alternately appearing, the clock period of the circuit is shortened, and the clock frequency is improved. The time sequence logic resource overhead is effectively reduced by replacing the trigger by the latch.

Description

Latch circuit, integrated circuit, and electronic device

Technical Field

The present invention relates to the field of latch technologies, and in particular, to a latch circuit, an integrated circuit, and an electronic device.

Background

Integrated circuits typically include combinational and sequential logic. The combinational logic does not include a storage element. The output of a given combinational logic circuit is therefore determined only by its current inputs. The sequential logic circuit includes memory elements whose outputs reflect the past order of their input values, with the result that the output of the sequential circuit is determined by its current input in combination with the data stored in its memory elements.

Commonly used sequential circuit storage elements include level sensitive latches and flip-flops. In a level sensitive latch, the latch output is controlled by the clock (enable) input level. When the clock signal is high, the output trace input value is latched. When the clock signal goes from high to low, the output state of the latch is frozen at the value before the transition, regardless of the value. The output of the latch remains in its frozen state as long as the clock signal is low.

The flip-flop is an edge-triggered device that changes state on a rising or falling edge of an enable signal, e.g., on a rising or falling edge of a clock signal. In a rising edge triggered flip-flop, the flip-flop samples its input state only on the rising edge of the clock signal. This sample value remains until the next rising edge of the clock signal. The flip-flop is made up of latches, so the latches are smaller in area and faster than the flip-flop.

At present, a circuit formed by latches generally has a problem that the clock period of the circuit is large, the clock frequency is small, and the precision is low.

Disclosure of Invention

Based on this, it is necessary to provide a latch circuit, an integrated circuit, and an electronic device in view of the above technical problems.

A latch circuit, comprising: a first flip-flop, a second flip-flop, at least one first latch and at least one second latch; wherein one of the first latch and the second latch is a high-level open latch, and the other of the first latch and the second latch is a low-level open latch;

the output end of the first trigger is connected with the input end of the second trigger sequentially through the first latches and the second latches, one second latch is arranged between two adjacent first latches, one first latch is arranged between two adjacent second latches, the output end of each first latch is connected with the input end of the second latch through a non-critical path, and the output end of each second latch is connected with the input end of the first latch through a critical path;

the enable terminal of each of the first latches and the enable terminal of each of the second latches are for receiving a clock signal, the clock signal being set to a high level for a duration different from a low level for a duration;

along a direction of data transmission, an arrival time of data from the first latch to the second latch is a first arrival time, an arrival time of data from the second latch to the first latch is a second arrival time, one of the first arrival time and the second arrival time is set to be greater than zero, and the other of the first arrival time and the second arrival time is set to be greater than a transparent time length of the first latch and a transparent time length of the second latch.

In one embodiment, the first latch is a high-level open latch and the second latch is a low-level open latch.

In one embodiment, the clock signal is set to a high level for a duration greater than a low level.

In one embodiment, the clock signal is set to: the duration of the high level is twice the duration of the low power.

In one embodiment, the first arrival time is set to be greater than zero and the second arrival time is set to be greater than a transparent time length of the first latch and a transparent time length of the second latch.

In one embodiment, the number of first latches is one more than the number of second latches.

In one embodiment, the output terminal of the first flip-flop is connected to the input terminal of one of the first latches through one of the critical paths, and the output terminal of the other of the first latches is connected to the input terminal of the second flip-flop through the other of the critical paths.

In one embodiment, the first latches and the second latches are equal in number, and each of the first latches is connected with one of the second latches.

An integrated circuit comprising a latch circuit as described in any one of the embodiments above.

An electronic device comprising an integrated circuit as described in the above embodiments.

The latch circuit, the integrated circuit and the electronic equipment adopt the cross arrangement of the latches with high level opening and low level opening, so that clock borrowing technology can be adopted in the circuit with the alternate critical paths and non-critical paths, the clock period of the circuit is shortened, and the clock frequency is improved. In addition, by using latches to replace flip-flops, sequential logic resource overhead can be effectively reduced, thereby reducing the cost and power consumption of the circuit.

Drawings

FIG. 1A is a schematic diagram of circuit element connections of a latch circuit during derivation of an embodiment;

FIG. 1B is a schematic diagram of the clock signal timing and data transfer in the latch circuit of the circuit of FIG. 1A in the derivation of the embodiment;

FIG. 1C is a schematic diagram of the clock signal timing and data transfer in the latch circuit of the circuit of FIG. 1A in another derivation of an embodiment;

FIG. 2A is a schematic diagram of circuit element connections of a latch circuit according to yet another embodiment;

FIG. 2B is a schematic diagram of the circuit of FIG. 2A in one embodiment with clock signal timing and data transfer in the latch circuit.

Detailed Description

In order to make the objects, technical solutions and advantages of the present application more apparent, the present application will be further described in detail with reference to the accompanying drawings and examples. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the present application.

Example 1

In this embodiment, as shown in fig. 2A, there is provided a latch circuit including: a first flip-flop, a second flip-flop, at least one first latch and at least one second latch; wherein one of the first latch and the second latch is a high-level open latch, and the other of the first latch and the second latch is a low-level open latch;

along the direction of data transfer, the arrival time of data from the first latch to the second latch is set to be greater than zero, and the arrival time of data from the second latch to the first latch is set to be greater than the transparent time length of the first latch and the transparent time length of the second latch.

In this embodiment, the first latch and the second latch are latches with different open levels, and in one embodiment, when the first latch is a latch with an open high level, the second latch is a latch with an open low level. In one embodiment, when the first latch is a low-level open latch, the second latch is a high-level open latch. The latch with high level open means that the latch is in a non-latching state, namely a transparent state when the latch receives a high level, the output is transparent to the input when the latch does not latch, the value output by the latch is the value of the input, and the output state of the latch is frozen at the value of the input when the latch with high level open receives a low level; similarly, a low-level open latch refers to a latch that is in an unlatched state, i.e., a transparent state, when the enable terminal receives a low level. Thus, in this embodiment, the transparent time length of the latch refers to the time length for which the latch remains in the transparent state for one period, or the time length for which the latch remains open for one period. As shown in fig. 1B, 1C, and 2B, in the timing of the clock signal, tran is an abbreviation of transparent, which indicates a transparent time length, and keeper is a latched time length.

In this embodiment, each first latch and each second latch are sequentially connected, and the first latch and the second latch are arranged in a quincuncial bamboo shape, so that a critical path and a non-critical path between the first latch and the second latch can also be alternately arranged. The Critical Path (CP) represents the worst-timing path in the entire circuit, and the most difficult path is the one that is decisive for the clock cycle requirements or the main frequency setting in the entire circuit. The critical path is CP, the Non-critical path is Non-CP, as shown in FIG. 1, the critical path includes CP0, CP1, CP2, CP3, and the Non-critical path includes Non-CP0, non-CP1.

Specifically, since the duration of the high level is different from the duration of the low level in each period of the clock signal, the time of the non-critical path of the next period can be borrowed when data is transmitted in the critical path, so that the data can be completely transmitted in the critical path, and since the duration of the high level is different from the duration of the low level, the duration of one of the high level or the low level can be reduced, so that the period of the clock signal is shortened, thereby improving the clock frequency.

In the above embodiment, the latches with high-level open and low-level open are arranged in a crossing manner, so that clock borrowing technology can be adopted in the circuit where the critical path and the non-critical path alternately appear, the clock period of the circuit is shortened, and the clock frequency is improved.

In addition, it is worth mentioning that in the conventional sequential circuit, flip-flops are mostly adopted to form a circuit, so that the problems of high sequential logic resource overhead, high power consumption and high manufacturing cost exist. In this embodiment, the latch is used to replace the flip-flop, so that the time sequence logic resource overhead can be effectively reduced, and the cost and the power consumption of the circuit are reduced.

For better illustrating the derivation process of the time of the critical path borrowing the non-critical path, please refer to fig. 1A to 1C, fig. 1A to 1C are the derivation processes of fig. 2A to 2B, and fig. 1A to 1C are not embodiments of the present application.

Referring to fig. 1A, the high-level open latch is LP, the low-level open latch is LN, the first latch includes LP1, LP2, and LP3, and the second latch includes LN1 and LN2. The output terminal Q of the first flip-flop is connected to the input terminal D of the first latch LP1 through the critical path CP0, the output terminal Q of the first latch LP1 is connected to the input terminal D of the second latch LN1 through the critical path CP1, the output terminal Q of the second latch LN1 is connected to the input terminal D of the first latch LP2 through the Non-critical path Non-CP0, and the subsequent elements of the circuit are connected as shown in fig. 1A, which is not described in detail herein.

The high-level latch and the low-level latch are staggered, and the arrangement sequence of the high-level latch and the low-level latch and the trigger is as follows: the DFF1, LP1, LN1, LP2, LN2, LP3, and DFF2 are alternately arranged, and the critical path, the Non-critical path, the high-level latch, the low-level latch, and the flip-flop are arranged in the order of DFF1, LP1, CP1, LN1, non-CP0, LP2, CP2, LN2, non-CP1, LP3, CP3, and DFF2. Referring to fig. 1B together, the clock signal can only conduct one data in one complete clock cycle, and is controlled by DFF1 of the first stage, and output is performed by DFF2.

Thus, as can be seen from the timing diagram of FIG. 1B:

1. since the latches are high and low staggered, the time left for each stage of latches to transfer is either the high duration or the low duration within a single clock cycle.

2. To simplify the analysis, assuming that the clock duty-cycle (clock duty-cycle) is 50%, i.e., the high and low durations are equal, the conduction time of each stage of latches is one-half of the clock period, i.e., 1/2T_period, and the corresponding hold time is also 1/2T_period.

3. Each stage of transmission path adopts the latest transmission period to transmit data.

4. From the analysis of the timing diagram of FIG. 1B, the arrival time of the data transmission between LP1 and LN1 cannot be greater than the duration of tran of the tran+LN1 of LP1, otherwise the data will not be captured correctly by LN 1.

It is noted that the duration of tran of the tran+Lp2, which has not been longer than LN1, must also be satisfied between LN1 and LP2, and that the calculation of the arrival times with LP1 and LP2 is simultaneously performed within the tran duration of LN1, and that the arrival time to each stage of transmission path is only one tran in length on average.

6. From the above analysis, the following can be concluded:

i. the data transmission time of the high-level and low-level interleaving circuit is half a clock period or equal to the high-level duration and the low-level duration in one clock period.

For the same combinational logic circuit, the clock period of the latch can in principle be only half that of the flip-flop in order to meet the critical path arrival requirements.

The throughput of the whole circuit is only half that of the flip-flop at this time.

To this end, adjustments are made to the circuit based on fig. 1A in the arrival times of critical and non-critical paths, as shown in fig. 1C:

1. because the high and low latches are staggered, the time left for each stage of latches to transfer is either the high duration or the low duration within a single clock cycle.

2. To simplify the analysis, it is first assumed that the clock duty cycle is 50%, i.e. the high level and the low level have equal duration, and then the conduction time of each stage of clock duty cycle is 1/2t_period, and the corresponding hold time is also 1/2t_period.

3. Each stage of transmission path jumps to the next transmission period to transfer data so as to reduce the requirement on T_period.

4. From the analysis of the timing diagram of FIG. 1C, it is seen that the maximum allowed arrival time between the flip-flop and the latch is one clock cycle.

5. To avoid two data transfers occurring in one transfer period, it is required that:

the arrival time arive time between dff1 and LP1 > t_tran (for critical paths, the arrival time arive time may require a complete t_period).

The arrival time arive time >0 between LP1 and LN1 is sufficient (irrespective of the device's requirement for hold).

Arrival time arive time > T_tran between LN1 and LP 2.

It follows that along the data transfer direction, the arrival time of the data from the high-level open latch to the low-level open latch is greater than zero, and the arrival time of the data from the low-level open latch to the low-level open latch is greater than zero, i.e., the arive time between LP and LN is >0, and the arive time between LN and LP is required to be greater than t_tran.

It should be noted that, in order to adjust the arrival time between LN and LP, the arrival time between LN and LP may be adjusted to change the arrival time by adjusting the data processed by the path between LN and LP and the data processed by the path between LN and LP. For example, the original process a+b+c is between LP and LN, and the process D between LN and LP is optimized to reduce the arrival time between LP and LN and increase the arrival time between LN and LP: between LP and LN is the treatment a, and between LN and LP is d+b+c, so that the arrival time between LP and LN is reduced and the arrival time between LN and LP is increased.

However, since data transmission takes one complete cycle, whether it is a critical path or a non-critical path, the clock frequency cannot be increased. Therefore, on the basis of the circuit and the clock signal, the transmission time on the non-critical path needs to be compressed to achieve the effect of increasing the clock frequency.

Example two

In this embodiment, the first latch is a high-level open latch, the second latch is a low-level open latch, the duration of the clock signal being set to be high is longer than the duration of the low level, the first arrival time is set to be greater than zero, and the second arrival time is set to be greater than the transparent time length of the first latch and the transparent time length of the second latch. In this embodiment, the output end of the first flip-flop is connected to the input end of the first latch through one of the critical paths, and the output end of the other first latch is connected to the input end of the second flip-flop through the other of the critical paths.

In this embodiment, as shown in fig. 2A, the number of the first latches is one more than the number of the second latches. In this embodiment, in the part of the circuit in which the first latch and the second latch are sequentially connected, two first latches are located at two ends of the circuit, so that the output end of the first latch is connected to the input end of the first latch located at the first position, and the output end of the first latch located at the end is connected to the input end of the second latch.

As shown in fig. 2A, the high-level open latch is LP, the low-level open latch is LN, the first latch includes LP1, LP2, LP3, and the second latch includes LN1, LN2. In this embodiment, the output terminal Q of the first flip-flop is connected to the input terminal D of the first latch LP1 through the critical path CP0, the output terminal Q of the first latch LP1 is connected to the input terminal D of the second latch LN1 through the Non-critical path Non-CP0, the output terminal Q of the second latch LN1 is connected to the input terminal D of the first latch LP2 through the critical path CP1, and the subsequent elements of the circuit are connected as shown in fig. 2A, which is not described in detail in this embodiment.

As shown in fig. 2B, in each period of the clock signal, the duration of the high level is longer than the duration of the low level, as can be seen from fig. 2B:

2. As can be seen from the analysis of the timing diagram in FIG. 1C, if the critical paths and the non-critical paths are staggered, and the requirement of the adjacent two-stage pipe on the arrival time arive time is combined, the optimization of the timing occupation can be realized by optimizing the duty ratio.

3. In this embodiment, it is assumed that the clock frequency of the original flip-flop is 500MHz, that is, the clock period t_period is 2ns, and CP1, CP2, CP3 are critical paths, and the arrival arive time of the critical paths is 2ns without considering other interference factors:

i. assuming that the arrival arive time of non-cp1 is 1ns, i.e., T_high is required to be equal to or greater than 1ns;

from the analysis of the timing diagram shown in FIG. 2B, CP1 can borrow clocks from non-CP1 (timing clock), and the maximum borrowing duration is the duration of low level;

the maximum required time for CP1 after clock borrowing is one high level duration and two low level durations, i.e. 1×t_high+2×t_low, requiring 1×t_high+2×t_low be greater than or equal to 2ns.

Combining the above conditions, it can be seen that the requirements of CP1 and non-CP1 can be met when t_high=1 ns & t_low=0.5 ns.

Thus, without changing the critical path arrival time, arive time, the clock period, T_period, is compressed from 2ns to 1.5ns, i.e., the frequency is increased from 500MHz to 666MHz.

It should be understood that the clock borrowing (Timing clock) technique is also called cycle stealing (cycle scaling) technique, mainly uses the level sensitive characteristic of the latch to obtain data through an active level, and keeps the latched data through an inactive level, so as to mainly solve the situation that the path Timing does not meet the circuit requirement.

In this embodiment, a non-critical path is between the high-level open latch and the low-level latch, a critical path is between the low-level open latch and the high-level latch, and the duration of the high level is longer than that of the low level, so that the critical path borrows the time of the non-critical path, and further the complete transmission requirement of the data of the critical path is satisfied.

In this embodiment, as shown in fig. 2B, the duration of the high level is twice the duration of the low level, i.e. t_high=2×t_low, where t_high=1ns and t_low=0.5 ns, and the critical path borrows the time of the non-critical path from the next clock cycle, so that the duration of the low level can be shortened to half of the original one while the duration of the high level remains unchanged, and thus, the clock frequency can be increased from 500MHz to 666MHz.

Example III

In a further embodiment, the first latch is a low-level open latch, the second latch is a high-level open latch, the clock signal is set to a low level for a duration greater than a high level for a duration, an arrival time of data from the first latch to the second latch is a first arrival time, an arrival time of data from the second latch to the first latch is a second arrival time, the second arrival time is set to be greater than zero, and the first arrival time is set to be greater than a transparent time length of the first latch and a transparent time length of the second latch.

In this embodiment, a non-critical path is between the low-level open latch and the high-level latch, a critical path is between the high-level open latch and the low-level latch, and the duration of the low level is longer than that of the high level, so that the critical path borrows the time of the non-critical path, and further the complete transmission requirement of the data of the critical path is satisfied.

In this embodiment, the number of the first latches is equal to the number of the second latches, so that the paths between the first flip-flop and the first latch can be reasonably set, and the path between the last second latch and the second flip-flop can be reasonably set, thereby achieving the result of the above embodiment.

Example IV

Please refer to fig. 1A and 1B, in this embodiment:

1. the latch staggered arrangement of high level and low level is adopted.

The critical path and non-critical path alternate.

3. Data transfer is not needed as much as possible among the pies of different stages.

4. Only one data can be conducted for a complete clock cycle, controlled by the DFF of the first stage.

5. The final output stage also employs DFF.

Referring to FIG. 1B,1. Because of the staggered high and low levels of latches, the time left for each stage of latches to transfer is either the high or low duration within a single clock cycle.

2. To simplify the analysis, it is first assumed that the clock duty-cycle is 50%, i.e., the high and low durations are equal, and then the conduction time of each stage latch is 1/2T_period, and the corresponding hold time is also 1/2T_period.

3. Each stage of LAT PIPE transfers data using the most recent transfer cycle.

4. From the above analysis of the timing diagrams, the arive time between LP1 and LN1 cannot be greater than the LP1 tran+LN1 tran duration, otherwise the data will not be captured correctly by LN 1.

The arive time relationship described in item3 must also be satisfied between LN1 and LP2, noting that LN1 tran is involved in the arive time calculation with LP1 and LP2 at the same time, and that there is virtually only one L tran given on average to the arive time of each stage of latch pipe.

6. From the above analysis, the following can be concluded:

i. the transmission time of the high-low level interleaved latch pipe is a clock half cycle, or a clock high-low level duration.

For the same combinational logic circuit, the clock period of the latch tape can be half of that of the flip-flop tape in principle in order to meet the arive time requirement of the critical path.

The entire tape is now through-flow half the flip-flop tape.

In combination with figure 1C on the basis of figure 1A,

1. because of the staggered high and low levels of latches, the time left for each stage of latches to transfer is either the high or low duration within a single clock cycle.

3. Every other LAT PIPE jumps to the next transfer cycle to transfer data to reduce the requirements for T_period.

4. From the above analysis of the timing diagrams, the maximum arive time allowed between the DFF and the LAT, and between the LAT and the LAT, is one clock cycle.

5. To avoid two data transfers occurring within one tran period, it is required that:

the arive time between DFF1 and LP1 > T_tran (for a critical path, an intact T_period may be required for the arive time).

The arive time >0 between LP1 and LN1 is sufficient (irrespective of the device's requirements for hold).

Arive time > T_tran between LN1 and LP 2.

Similarly, the arive time between LP and LN is >0, and the arive time between LN and LP is required to be greater than t_tran.

As shown in figures 2A and 2B,

2. As can be seen from the analysis of FIG. 1C, if the cross arrangement of the critical path and the non-critical path is realized and the requirement of the adjacent two-stage pipe on the arive time is combined, the performance can be optimized by optimizing the duty-cycle.

3. Assuming that the original DFF PIPE clock is 500MHz, i.e., T_period is 2ns, and CP1/CP2 is the most critical path, the arive time is 2ns without considering the uncertainty and setup requirements:

i. suppose that the arive time of non-cp1 is 1ns, i.e., T_high is required to be 1ns.

From the above analysis of the timing diagrams, CP1 can perform timing clock from non-CP1, and the maximum duration of the clock is the duration of the clock low level.

CP1 can use a maximum demand time of 1×t_high+2×t_low after timing narrow, i.e. 1×t_high+2×t_low is equal to or greater than 2ns.

Without changing the critical path arive time, T_period is compressed from 2ns to 1.5ns, i.e., the frequency is increased from 500MHz to 666MHz.

Example five

In this embodiment, an integrated circuit is provided that includes the latch circuit described in any of the embodiments above. In this embodiment, the integrated circuit is a semiconductor integrated circuit, and the latch circuit adopts a latch cross arrangement of high-level open and low-level open, so that clock borrowing technology can be adopted in a circuit in which a critical path and a non-critical path alternately appear, thereby shortening the clock period of the circuit and improving the clock frequency.

Example six

In this embodiment, an electronic device is provided, which includes the integrated circuit described in the above embodiment.

In the above embodiments, the latches with high-level open and low-level open are arranged in a crossing manner, so that clock borrowing technology can be adopted in the circuit where the critical path and the non-critical path alternately appear, the clock period of the circuit is shortened, and the clock frequency is improved.

The technical features of the above embodiments may be arbitrarily combined, and all possible combinations of the technical features in the above embodiments are not described for brevity of description, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.

The above examples merely represent a few embodiments of the present application, which are described in more detail and are not to be construed as limiting the scope of the invention. It should be noted that it would be apparent to those skilled in the art that various modifications and improvements could be made without departing from the spirit of the present application, which would be within the scope of the present application. Accordingly, the scope of protection of the present application is to be determined by the claims appended hereto.

Claims

1. A latch circuit, comprising: a first flip-flop, a second flip-flop, at least one first latch and at least one second latch; wherein one of the first latch and the second latch is a high-level open latch, and the other of the first latch and the second latch is a low-level open latch;

2. The latch circuit of claim 1 wherein the first latch is a high-level open latch and the second latch is a low-level open latch.

3. The latch circuit of claim 2 wherein the clock signal is set to a high level for a duration greater than a low level.

4. A latch circuit according to claim 3, wherein the clock signal is arranged to: the duration of the high level is twice the duration of the low power.

5. The latch circuit of claim 2 wherein the first arrival time is set to be greater than zero and the second arrival time is set to be greater than a transparent time length of the first latch and a transparent time length of the second latch.

6. A latch circuit according to any one of claims 2 to 5, wherein the number of first latches is one more than the number of second latches.

7. The latch circuit of claim 6 wherein the output of said first flip-flop is connected to the input of one of said first latches through one of said critical paths and the output of the other of said first latches is connected to the input of said second flip-flop through the other of said critical paths.

8. The latch circuit of claim 1 wherein the number of first latches and the number of second latches are equal and each first latch is connected to one of the second latches.

9. An integrated circuit comprising a latch circuit as claimed in any one of claims 1 to 8.

10. An electronic device comprising an integrated circuit as claimed in claim 9.