TWI771982B - A double-edge triggered flip-flop circuit and a shift register thereof - Google Patents

Abstract

A double-edge triggered flip-flop circuit and a shift register thereof are provided. The circuit flip-flop structure utilizes two parallel data paths, and can complete the signal trigger of opposite phase in a single time pulse signal under the condition of reducing reverse input trigger.

Description

Double edge-triggered flip-flop circuit and its shift register

The present application relates to a flip-flop circuit, and in particular, to a double-edge-triggered flip-flop circuit and a shift register thereof.

In the prior art, there are several ways to realize the double edge-triggered flip-flop. The first is to additionally provide an auxiliary circuit, generally a delayed XOR circuit, which generates an internal pulse signal at each clock signal edge. The second method is to duplicate the path so that the flip-flop can sample the data at each clock signal edge, that is, for the dual data path method, there are many designs for this, such as using transmission gate logic, pass transistor logic, etc.

Johnson et al. (T.A.Johnson and I.S.Kourtev, "A single latch, high speed double-edge triggered flip-flop (DETFF)," in Proc.Int.Conf.on Electronics, Circuits and Systems IEEE, pp.189-192, Jan. 2001.) developed a static double-edge-triggered flip-flop, which compared with a single-edge flip-flop (SETFF) at a fixed data throughput, the required operating frequency was reduced by nearly half, but its operating power consumption was not improved.

Hossain et al. (R. Hossain, L.D. Wronski, and A. Albicki, "Lowpower design using double edge trigger-ed flip-flops," IEEE Trans. on VLSI Systems., vol. 2, no. 2, pp. 261- 265, June 1994.) pointed out that the double-edge-triggered flip-flop can save energy significantly because its complexity is lower than that of the single-edge flip-flop (SETFF). However, this circuit needs to design the positive and negative input terminals, Therefore, a double-ended signal input circuit needs to be designed, the number of transistors cannot be reduced, and the manufacturing process is relatively complicated.

Sung et al. (Y.-Y.Sung and R.-C.Chang, "A novel CMOS double-edge triggered flipflop for low-power application," in Proc.IEEE Inter.Symp.on Circuits and Systems, pp:II -665, vol.2, May 2004.) designed a low-power double edge triggered data flip flop (DETFF), which uses a low-swing timing gating technology. However, this method uses multi-voltage transformers, which have the problems that low-voltage transformers occupy a larger area than ordinary transistors, and the subthreshold current increases.

In addition, the built-in self-test (BIST) is widely used in the testing of any VLSI circuit because it provides a wider range of low-power applications. Prayeen et al. (Y.G.Praveen Kumar, B.S.Kariyappa and M.Z.Kurian, "Implementation of power efficient 8-bit reversible linear feedback shift register for BIST," in Proc.Int.Conf.on Inventive Systems and Control (ICISC), pp.1 -5.Jan.2017.) developed a reversible linear phase shift register (8-bit), which reduces the power consumption of the register by 10% compared with the traditional LFSR. applicability is low.

Abhilash et al. (A. Bagalkoti, S.B. Shirol, S. Rama Krishna, P. Kumar and R.B.S, "Design and implementation of 8-bit LFSR, bit-swapping LFSR and weighted random test pattern generator: A performance improvement," in Proc .Int.Conf.on Intelligent Sustainable Systems (ICISS), pp.82-86, Feb.2019.) proposed an LFSR (8-bit) using a weighted random test pattern generator to improve the overall performance, which can be very Good for reducing latency, but ultimately leads to higher power consumption.

In order to solve the above problems, the present application proposes a double-edge-triggered flip-flop circuit and its shift register, which utilizes two parallel data paths. Signal triggering of the opposite phase is completed within the

The present application is achieved through the following technical solutions: a double-edge-triggered flip-flop circuit, comprising: first ends of a first transistor and a second transistor are connected to a data input end in common, and second ends are respectively connected to a first non-gate and the input end of the second non-gate; the second end of the third transistor and the fourth transistor are connected to the input end of the third non-gate, and the first end is respectively connected to the output end of the first non-gate and the second non-gate, The output terminal of the third non-gate is connected to the first data output terminal; the control terminals of the first transistor and the fourth transistor are connected to the first clock signal, and the control terminals of the second transistor and the third transistor are connected to the second clock signal signal, the first clock and the second clock are inverted.

Optionally, when the first clock signal is at a logic high potential and the second clock signal is at a logic low potential, the first transistor and the fourth transistor are connected, and the second transistor and the third transistor are disconnected; The data signal input from the input end passes through the first transistor, and is inverted by the first non-gate to form a first inversion signal, and the first inversion signal is stored at the node between the first non-gate and the third transistor.

Optionally, when the second clock signal becomes a logic high potential and the third transistor is turned on, the first inversion signal stored at the node between the first non-gate and the third transistor passes through the third transistor. The signal is inverted by the third non-gate for signal output through the first data output terminal.

Optionally, when the first clock signal is at a logic low potential and the second clock signal is at a logic high potential, the first transistor and the fourth transistor are disconnected, and the second transistor and the third transistor are connected; The data signal input from the input end passes through the second transistor, and is inverted by the second non-gate to form a second inversion signal, and the second inversion signal is stored in the node between the second non-gate and the fourth transistor.

Optionally, when the second clock signal becomes a logic high level and the fourth transistor is turned on, the second inversion signal stored at the node between the second non-gate and the fourth transistor passes through the fourth transistor. The signal is inverted by the third non-gate for signal output through the first data output terminal. Optionally, each non-gate is connected in parallel with a regenerative transistor, the first end of the regenerative transistor is connected to the power supply, the control end is connected to the output end of the non-gate, and the second end is connected to the input end of the non-gate.

Optionally, when the control terminal of the regenerative transistor obtains the flip signal of the output terminal of the non-gate connected in parallel, the regenerative transistor is turned on, and the power is transmitted to the input terminal of the non-gate through the regenerative transistor, so as to increase the output received by the non-gate. The signal strength of the data signal.

Optionally, the first transistor, the second transistor, the third transistor and the fourth transistor are three types of N-type metal oxide semiconductor transistors, P-type metal oxide semiconductor transistors, and complementary metal oxide semiconductor transmission gates. Any combination of components.

Optionally, the first clock signal is connected to the fourth reverse gate to generate the second clock signal.

In a second aspect, the present application discloses an N-bit shift register, which includes N flip-flop circuits, where N is a positive integer greater than 1, and each flip-flop circuit is as described in items 1 to 8 in the scope of the patent application. Any one of the items is formed; wherein, the input terminal of each flip-flop circuit is connected to the output terminal of the previous stage flip-flop circuit, and the output signals of each flip-flop circuit are combined to form N-bit displacement data, the first The input terminal of the stage flip-flop circuit is connected to the data input terminal, and the first clock signal and the second clock signal are respectively connected to each flip-flop circuit.

The beneficial effects of this application are:

(1) This application also adopts the double edge trigger design. Compared with the single edge trigger (SETFF) in fixed data throughput, it still has the advantage that the required operating frequency is reduced by nearly half. To input flip-flops, signals of opposite phases can be completed within a single clock signal. trigger.

(2) This case proposes that by removing the inverting input trigger by design, and at the same time regenerating the transistor to make the input end connected to the transistor, the signal passing through it is effectively enhanced, which can significantly maintain or improve the performance of the flip-flop.

(3) In terms of integrated circuit technology, on the premise of maintaining the performance of the flip-flop, the inverting input flip-flop is omitted, no additional delay circuit needs to be added, and the number of transistors is clearly reduced to reduce the core area, thereby reducing cost and power. consumption.

100:1 bit double edge-triggered flip-flop

110: Latch

120: Output Holder Circuit

MN11, MN12, MN13, MP11, MP12, MP13, MP14: Transistor

I11, I12, I13, I14, I15, I16: non-gate

N11, N12, N13, N14, N15: circuit nodes of 1-bit double edge-triggered flip-flop 100

200: Flip-flop circuit

MN21: first transistor

MN22: Second transistor

MN23: The third transistor

MN24: Fourth transistor

I21: The first non-gate

I22: Second non-gate

I23: The third non-gate

I24: Fourth non-gate

N21, N22, N23, N24, N25: circuit nodes of the flip-flop circuit 200

MP21, MP22, MP24: Regenerative transistors

MP23: Reset Transistor

300: Shift register

In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the accompanying drawings that need to be used in the description of the embodiments or the prior art. Obviously, the drawings in the following description are only the For some embodiments of the application, for those of ordinary skill in the art, other drawings can also be obtained according to these drawings without any creative effort.

[FIG. 1] is an exemplary flip-flop circuit; [FIG. 2] is a double-edge-triggered flip-flop circuit according to an embodiment of the present application; [FIG. 3] is a shift register according to an embodiment of the present application.

The technical solutions and advantages are clearer. The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not All examples. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative work fall within the protection scope of the present application.

FIG. 1 is an exemplary flip-flop circuit, which discloses the schematic design of the 1-bit dual-edge-triggered flip-flop described by Hossain et al. The 1-bit dual-edge-triggered flip-flop 100 consists of six transistors ( MN11, MN12, MN13, MP11, MP12, MP13), two latches 110 and an output holder circuit 120 connected to the power supply (VDD), the input node and output node of the non-gate I15 are respectively used as the data positive phase output (Q ) and the data inverted output (Qbar). Among them, the transistors (MN11, MN12, MN13) are NMOS transistors, the transistors (MP11, MP12, MP13) are PMOS transistors, and the latches are respectively composed of non-gate (I11) and non-gate (I12) and non-gate ( I13) and the non-gate (I14) are configured in a back-to-back configuration, and the output holder circuit 120 is composed of the non-gate I15 and the transistor MP14. When the clock signal (CK) goes from low to high, the upper path is holding data, while the lower path is sampling data. However, when the clock signal (CK) goes from high to low, the upper path is holding data, while the lower path is sampling data. However, when the clock goes from high to low, the upper path switches to sample data, and the lower path switches to hold data. The data non-inverting input (D) and the data inversion input (Dbar) can be generated through the non-gate (I16) with the data non-inverting input. The circuit nodes ( N11 , N12 , N13 , N14 , N15 ) of the 1-bit dual-edge-triggered flip-flop 100 are equivalent contacts representing connected elements. However, whether it is input through the normal phase (D) or the reverse phase (Dbar), it is necessary to switch the upper/lower path to complete the overall process of holding data and sampling data, which not only takes a long time, but also takes a long time to execute the data path. resulting in more power consumption.

FIG. 2 is a double edge-triggered flip-flop circuit 200 disclosed in the present application, which includes: the first ends of the first transistor MN21 and the second transistor MN22 are connected to the data input terminal (Din) in common, and the second ends are respectively connected to the data input terminal (Din). The input terminals of the first non-gate I21 and the second non-gate I22; the second terminals of the third transistor MN23 and the fourth transistor MN24 are connected to the input terminal of the third non-gate I23, and the first terminals are respectively connected to the following first non-gate I23. The gate I21 is connected to the output terminal of the second non-gate I22 below, and the output terminal of the third non-gate I23 below is connected to the first data output terminal; the control terminal of the first transistor MN21 below and the control terminal of the fourth transistor MN24 below are connected to the first clock pulse Signal (CK), the control terminals of the second lower transistor and the lower third transistor MN23 are connected to the second clock signal (CKB), and the lower first clock (CK) and the lower second clock (CKB) are in opposite phases. The circuit nodes (N21, N22, N23, N24, N25) of the flip-flop circuit 200 are equivalent contacts representing connected elements, and the subsequent simplified descriptions are node N21, node N22, node N23, node N24, and node N25.

In an embodiment of the present application, as mentioned above, the present application also has a dual data channel structure. The difference from the above example is that the present application omits the design of the inverting input trigger circuit, and uses the positive and negative phases of the clock to temporarily store data. work with sampling.

In an embodiment of the present application, when the first clock signal (CK) is at a logic high level and the second clock signal (CKB) is at a logic low level, the first transistor MN21 and the fourth transistor MN24 are turned on, The second transistor MN22 and the third transistor MN23 are disconnected; the data signal input from the data input terminal (Din) passes through the first transistor MN21 and is inverted by the first non-gate I21 to form a first inversion signal, and the first inversion signal is stored in A node N23 between the first non-gate I21 and the third transistor MN23.

In an embodiment of the present application, the node N24 between the second non-gate I22 and the fourth transistor MN24 temporarily stores the second inversion signal during the previous clock signal period, because the fourth transistor MN24 is connected to On, the second inversion signal will be forwarded to the third non-gate I23.

In an embodiment of the present application, when the second clock signal (CKB) becomes a logic high level and the third transistor MN23 is turned on, the node N23 stored between the first non-gate I21 and the third transistor MN23 The first inversion signal of , which passes through the third transistor MN23 and is inverted by the third non-gate I23 for signal output through the first data output terminal.

In an embodiment of the present application, when the first clock signal (CK) is at a logic low level and the second clock signal (CKB) is at a logic high level, the first transistor MN21 and the fourth transistor MN24 are turned off, The second transistor MN22 and the third transistor MN23 are turned on; the data input from the data input terminal (Din) The signal passes through the second transistor MN22 and is inverted by the second non-gate I22 to form a second inversion signal, and the second inversion signal is stored at the node N24 between the second non-gate I22 and the fourth transistor MN24.

In an embodiment of the present application, when the first clock signal (CK) becomes a logic high level and the fourth transistor (MN24) is turned on, the voltage stored between the second non-gate I22 and the fourth transistor MN24 The second inversion signal of the node (N24) passes through the fourth transistor MN24 and is inverted by the third non-gate I23 for signal output through the first data output terminal.

In an embodiment of the present application, the node N23 between the first non-gate I21 and the third transistor MN23 temporarily stores the first inversion signal during the previous clock signal period, because the third transistor MN23 is connected to On, the first inversion signal will be forwarded to the third non-gate I23.

In an embodiment of the present application, each non-gate (I21, I22, I23) is respectively connected in parallel with a regenerative transistor (MP21, MP22, MP24), as shown in FIG. 2, the first end of the regenerative transistor MP21 is connected to a power supply (VDD ), the control terminal is connected to the output terminal of the non-gate I21 (same node N23), the second terminal of the regeneration transistor MP21 is connected to the input terminal of the non-gate I21 (same node N21); the first terminal of the regeneration transistor MP22 is connected to the power supply (VDD ), the control terminal is connected to the output terminal of the non-gate I22 (same node N24), the second terminal of the regeneration transistor MP22 is connected to the input terminal of the non-gate I22 (same node N22); the first terminal of the regeneration transistor MP24 is connected to the power supply (VDD ), the control terminal is connected to the output terminal of the non-gate I23 (same as the first data output terminal Q), and the second terminal of the regenerative transistor MP24 is connected to the input terminal of the non-gate I23 (same as the node N25 and the second data output terminal Qbar).

In an embodiment of the present application, when the control terminal of the regenerative transistors (MP21, MP22, MP24) obtains the inversion signal of the output terminals of the non-gates (I21, I22, I23) connected in parallel, the regenerative transistors (MP21, MP22) , MP24) is turned on, the power supply (VDD) is transmitted to the input terminal of the non-gate (I21, I22, I23) through the regeneration transistor (MP21, MP22, MP24), so as to increase the received by the non-gate (I21, I22, I23) The signal strength of the data signal.

That is, the dual path model disclosed in this application enables the flip-flop circuit to sample data on each clock signal edge. When the clock signal (CK) is at a logic high level, the first transistor MN21 and the fourth transistor MN24 are turned on, and the second transistor MN22 and the third transistor MN23 are turned off. The input signal (Din) passes through the first transistor MN21, and then the signal is inverted by the first non-gate I21. The toggle signal is stored at node N23 until the clock signal goes logic low. However, for the next half clock signal period, the clock signal CKB goes to a logic high level and the third transistor MN23 is turned on. Therefore, the previously stored inversion signal at the node N23 passes through the third transistor MN23 and is inverted by the third non-gate I23, and gives an output Q on reset. On the other hand, when the clock signal is logic low, the input signal (Din) passes through the second transistor MN22 and continues the same data processing as previously described. Regenerative transistor MP21, regenerative transistor MP22, and regenerative transistor MP24 are regenerative transistors associated with power supply VDD that help boost the signal and do not experience any voltage drop. Through this continuous process, the output Q is observed at each edge of the clock signal. Therefore, when the clock signal is inversely converted, the roles of the two channels are exchanged, showing alternate data sampling, temporary storage and transfer behavior.

In an embodiment of the present application, the first transistor MN21 , the second transistor MN22 , the third transistor MN23 and the fourth transistor MN24 are N-type metal-oxide-semiconductor transistors and P-type metal-oxide-semiconductor transistors , Complementary metal oxide semiconductor transmission gate any combination of three components.

2, the flip-flop circuit 200 further includes a reset transistor MP23, the first terminal of the reset transistor MP23 is connected to the power supply VDD, the second terminal of the reset transistor MP23 is connected to the node 25, and the control of the reset transistor MP23 The terminal is connected to the reset signal terminal (Reset), when the signal of the reset signal terminal (Reset) is a logic high level, the reset transistor MP23 is turned on, and the first data output terminal (Q) of the entire flip-flop circuit 200 The output of the second data output terminal (Qbar) will be reset. For example, the first data output terminal (Q) continuously outputs 0, and the second data output terminal (Qbar) continuously outputs 1.

As shown in FIG. 2, in some embodiments, the first clock signal (CK) can be connected to the fourth flip gate (I24) to generate the second clock signal (CKB), and then the first clock signal (CK) and the second clock signal (CKB) are respectively connected to the control terminals of the transistors, so that the input circuit of the clock signal can be simplified.

f.C.V2 (1) Comparing Fig. 1 and Fig. 2, on the circuit node N11 of the 1-bit double edge-triggered flip-flop shown in Fig. 1, there are two gate capacitances (transistor MN12/transistor MP13 generated by the circuit operation) ) and two diffusion capacitors (generated by non-gate I11/non-gate I12). However, at the node N23 of the flip-flop circuit 200 shown in FIG. 2, there are two gate capacitors (generated by the first transistor MN21/regenerative transistor MP21) due to operation, but only one diffusion capacitor (generated by the first transistor MN21/regenerative transistor MP21). not gate I21). Therefore, the load of the node N23 decreases as the charging and discharging time decreases, resulting in a decrease in power and energy consumption. In digital CMOS circuits, the switching power is defined as: Psw

fCV2 (1)

2Cg+2Cdiff (2) where PSW is the switching power of the transistor, C is the capacitance, V is the power supply, and f is the frequency. Assuming the same f and V for both designs, the power at node N11 (Equation 2) and node N23 (Equation 3) can be expressed as: PN11

2Cg+2Cdiff (2)

2Cg+Cdiff (3) PN23

2Cg+Cdiff (3)

CG is the gate capacitance (0.4nF), Cdiff is the diffusion capacitance (0.25nF), and the ratios are 8:5. On the 0.18-μm CMOS fabrication process. It is concluded that PN11 is 1.2 times larger than PN23. During opposite phases of the clock, node N13 and node N24 consume the same amount of power. However, since the number of transistors used in the flip-flop appliance 200 shown in FIG. 2 of the present application is smaller than that of the circuit design in FIG. 1 , it helps to reduce power consumption.

FIG. 3 is a shift register according to an embodiment of the application, as shown in FIG. 3 , which discloses N Shift register 300 for bits. The shift register includes N flip-flop circuits 200, N is a positive integer greater than 1, and the output (Q) of each flip-flop circuit can represent a bit, such as the 0th stage of the flip-flop circuit to the 1st stage of the flip-flop circuit. The output of the 7-stage flip-flop (DETFF-0~DETFF-7) can form an 8-bit data signal. Each flip-flop circuit is formed as any one of the above-mentioned flip-flop circuits 200; wherein, the input end of each flip-flop circuit is connected to the output end of the previous-stage flip-flop circuit, and the output signal of each flip-flop circuit is N-bit displacement data is formed by combining, the input terminal of the 0th stage flip-flop circuit is connected to the data input terminal (Din), and the first clock signal (CK) and the second clock signal (CKB) are respectively connected to each Flip-flop circuit 200. The clock signal (Clock) is connected to the trigger signal input end of each flip-flop, and is triggered by an inverted clock. The reset signal line (Reset) is connected to the reset signal terminal (Reset) of each flip-flop circuit. As mentioned above, when the signal of the reset signal terminal (Reset) is at a logic high level, the reset transistor MP23 is turned on, and the first data output terminal (Q) and the second data output terminal (Q) of each flip-flop circuit ( The output of Qbar) will be reset. For example, the first data output terminal (Q1-Q7) of each flip-flop circuit continues to output 0, and the second data output terminal (Q7bar) of the seventh-level flip-flop of the highest level continues to output. The output is 1.

To sum up, the dual-edge-triggered flip-flop circuit and its shift register of the present application, (1) the present application also adopts the dual-edge-triggered design, which is compared with the single-edge flip-flop (SETFF) in a fixed data throughput , still has the advantage of reducing the required operating frequency by nearly half. It is also a dual data path method and reduces the reverse input trigger, and can complete the signal triggering of the opposite phase within a single clock signal. (2) This case proposes that by removing the inverting input trigger by design, and at the same time regenerating the transistor to make the input end connected to the transistor, the signal passing through it is effectively enhanced, which can significantly maintain or improve the performance of the flip-flop. (3) In terms of integrated circuit technology, on the premise of maintaining the performance of the flip-flop, the inverting input flip-flop is omitted, no additional delay circuit needs to be added, and the number of transistors is clearly reduced to reduce the core area, thereby reducing cost and power. consumption. (4) The design of the shift register proposed in this application can be applied to the current CMOS process (such as 90nm) to achieve.

The above embodiments are only used to illustrate the technical solutions of the present application, but not to limit them; although the present application has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: The recorded technical solutions are modified, or some technical features thereof are equivalently replaced; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions in the embodiments of the present application.

200: Flip-flop circuit

MN21: first transistor

MN22: Second transistor

MN23: The third transistor

MN24: Fourth transistor

I21: The first non-gate

I22: Second non-gate

I23: The third non-gate

I24: Fourth non-gate

N21, N22, N23, N24, N25: circuit nodes of the flip-flop circuit 200

MP21, MP22, MP24: Regenerative transistors

MP23: Reset Transistor

Claims (8)

A double-edge-triggered flip-flop circuit, comprising: first ends of a first transistor (MN21) and a second transistor (MN22) are commonly connected to a data input end (Din), and second ends are respectively connected to a first non-gate (I21) and the input terminal of the second non-gate (I22); the second terminal of the third transistor (MN23) and the fourth transistor (MN24) are connected to the input terminal of the third non-gate (I23), and the first terminal The output terminals of the first non-gate (I21) and the second non-gate (I22) are respectively connected, and the output terminal of the third non-gate (I23) is connected to the first data output terminal; each non-gate (I21, I22, I23) are respectively connected in parallel with regenerative transistors (MP21, MP22, MP24), the first end of the regenerative transistor is connected to the power supply (VDD), the control end is connected to the output end of the non-gate, and the second end is connected to the input end of the non-gate; the When the control terminal of the regenerative transistor obtains the inversion signal of the output terminal of the non-gate connected in parallel, the regenerative transistor is turned on, and the power (VDD) is transmitted to the input terminal of the non-gate through the regenerative transistor to increase the reception of the non-gate The signal strength of the data signal received; the control terminals of the first transistor (MN21) and the fourth transistor (MN24) are connected to the first clock signal (CK), the second transistor and the third transistor The control terminal of (MN23) is connected to the second clock signal (CKB), and the first clock (CK) and the second clock (CKB) are in opposite phases. The double edge-triggered flip-flop circuit of claim 1, wherein when the first clock signal (CK) is at a logic high level and the second clock signal (CKB) is at a logic low level, the first clock signal (CK) is at a logic high level. The transistor (MN21) and the fourth transistor (MN24) are connected, the second transistor (MN22) and the third transistor (MN23) are disconnected; the data signal input from the data input terminal (Din) passes through the The first transistor (MN21) is turned over by the first non-gate (I21) to form a first inversion signal, and the first inversion signal is stored between the first non-gate (I21) and the third transistor (MN23) node (N23). The double-edge-triggered flip-flop circuit as claimed in claim 2, wherein when the second clock signal (CKB) becomes a logic high level and the third transistor (MN23) is turned on, it is stored in the first The first inversion signal of the node (N23) between the non-gate (I21) and the third transistor (MN23), which passes through the third transistor (MN23) and is signaled by the third non-gate (I23) Inverted for signal output through the first data output terminal. The double edge-triggered flip-flop circuit of claim 1, wherein when the first clock signal (CK) is at a logic low level and the second clock signal (CKB) is at a logic high level, the first clock signal (CK) is at a logic high level. The transistor (MN21) and the fourth transistor (MN24) are disconnected, the second transistor (MN22) and the third transistor (MN23) are connected; the data signal input from the data input terminal (Din) passes through the The second transistor (MN22) is inverted by the second non-gate (I22) to form a second inversion signal, and the second inversion signal is stored between the second non-gate (I22) and the fourth transistor (MN24) node (N24). The double-edge-triggered flip-flop circuit as claimed in claim 4, wherein when the first clock signal (CK) becomes a logic high level and the fourth transistor (MN24) is turned on, it is stored in the second The second inversion signal of the node (N24) between the non-gate (I22) and the fourth transistor (MN24), which passes through the fourth transistor (MN24) and is signaled by the third non-gate (I23) Inverted for signal output through the first data output terminal. The double edge-triggered flip-flop circuit of claim 1, wherein the first transistor, the second transistor, the third transistor and the fourth transistor are N-type metal oxide semiconductor transistors , P-type metal oxide semiconductor transistor, complementary metal oxide semiconductor transmission gate, any combination of three components. The double edge-triggered flip-flop circuit of claim 1, wherein the first clock signal (CK) is connected to the fourth flip gate (I24) to generate the second clock signal (CKB). An N-bit shift register, comprising N flip-flop circuits, where N is a positive integer greater than 1, and each flip-flop circuit is formed according to any one of items 1 to 6 in the scope of the patent application; The input end of each flip-flop circuit is connected to the output end of the previous-stage flip-flop circuit, the output signals of each flip-flop circuit are combined to form N-bit displacement data, and the input of the first-stage flip-flop circuit The terminal is connected to the data input terminal (Din), and the first clock signal (CK) and the second clock signal (CKB) are respectively connected to each flip-flop circuit.

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