CN116366013A - CMOS power amplification and power control circuit and control method - Google Patents

CMOS power amplification and power control circuit and control method Download PDF

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Publication number
CN116366013A
CN116366013A CN202310125738.XA CN202310125738A CN116366013A CN 116366013 A CN116366013 A CN 116366013A CN 202310125738 A CN202310125738 A CN 202310125738A CN 116366013 A CN116366013 A CN 116366013A
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China
Prior art keywords
power
power amplifier
output
pmos tube
signal
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CN202310125738.XA
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Chinese (zh)
Inventor
盛怀茂
熊亮
张松柏
顾建忠
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Xinpu Technology Shanghai Co ltd
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Xinpu Technology Shanghai Co ltd
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
    • H03F3/21—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only
    • H03F3/211—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only using a combination of several amplifiers
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/66—Regulating electric power
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/52—Circuit arrangements for protecting such amplifiers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/189—High frequency amplifiers, e.g. radio frequency amplifiers
    • H03F3/19—High frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only
    • H03F3/193—High frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only with field-effect devices
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/189—High frequency amplifiers, e.g. radio frequency amplifiers
    • H03F3/19—High frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only
    • H03F3/195—High frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only in integrated circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
    • H03F3/21—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only
    • H03F3/213—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only in integrated circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/451—Indexing scheme relating to amplifiers the amplifier being a radio frequency amplifier
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D30/00—Reducing energy consumption in communication networks
    • Y02D30/70—Reducing energy consumption in communication networks in wireless communication networks

Abstract

The invention discloses a CMOS power amplifying and power controlling circuit and a control method, comprising a power controlling circuit, a first power amplifier, a second power amplifier and a third power amplifier; the first power amplifier, the second power amplifier and the third power amplifier are respectively connected with the power control circuit; the power control circuit receives the output voltage of the control chip and provides bias signals for the first power amplifier, the second power amplifier and the third power amplifier; the first power amplifier, the second power amplifier and the third power amplifier are sequentially connected, and the first power amplifier and the second power amplifier are driving stages and drive the third power amplifier to output radio frequency output signals. The invention adopts the power control circuit to provide bias signals for the three-stage power amplifier in the power amplifying circuit, and omits a low-voltage linear voltage stabilizer with larger size and reduces the manufacturing cost of a control chip under the condition of realizing good power control.

Description

CMOS power amplification and power control circuit and control method
Technical Field
The invention relates to the field of power amplifier design, in particular to a CMOS power amplifying and power control circuit and a control method.
Background
The radio frequency power amplifier applied to 2G communication requires accurate and real-time power control. In order to realize power control, a conventional power amplifier may use a low dropout linear regulator whose output voltage varies linearly with the output voltage Vramp of the control chip to supply power to the power amplifier circuit, as shown in fig. 1, after a first power amplifier stage1, a second power amplifier stage2 and a third power amplifier stage3 are sequentially connected, they are connected to a low dropout linear regulator LDO, and the low dropout linear regulator LDO provides sufficient current for the power amplifier, and the third power amplifier stage3 outputs a radio frequency output signal.
In order to provide sufficient current to the power amplifier circuit, the physical size of the low dropout linear regulator is typically relatively large, which increases the cost of the control chip. And under the condition of output mismatch, the traditional power amplifier can reflect radio frequency output signals, so that devices in the power amplifier bear excessive radio frequency voltage, and the devices break down and control chips burn out.
Disclosure of Invention
The invention aims to provide a CMOS power amplification and power control circuit and a control method adopting multi-stage amplifier mixed bias, which abandons the traditional low-dropout linear voltage regulator and reduces the design cost of a radio frequency control chip.
In order to solve the above technical problems, the present invention provides a CMOS power amplifying and power controlling circuit, comprising: a power control circuit, a first power amplifier, a second power amplifier, and a third power amplifier;
the first power amplifier, the second power amplifier and the third power amplifier are respectively connected with the power control circuit; the power control circuit receives the voltage signals output by the control chip and provides bias signals for the first power amplifier, the second power amplifier and the third power amplifier;
the first power amplifier, the second power amplifier and the third power amplifier are sequentially connected, and the first power amplifier and the second power amplifier drive the third power amplifier to output radio frequency output signals.
Further, the first power amplifier circuit comprises a first NMOS tube, a first PMOS tube and a first resistor;
the radio frequency input signal is connected with the grid electrode of the first NMOS tube, the grid electrode of the first PMOS tube and one end of the first resistor; the other end of the first resistor is connected with the drain electrode of the first NMOS tube and the drain electrode of the first PMOS tube, and is used as the output end of the first power amplifier to output a second radio frequency output signal; the source electrode of the first NMOS tube is connected with the bias signal; and the source electrode of the first PMOS tube is grounded.
Further, the second power amplifier comprises a second PMOS tube, a first inductor and a second resistor;
the grid electrode of the second PMOS tube receives the second radio frequency signal and is connected with one end of the second resistor, and the other end of the second resistor is connected with the bias signal; the drain electrode of the second PMOS tube is connected with one end of the first inductor and is used as the output end of the second power amplifier to output a third radio frequency signal, and the other end of the first inductor is connected with a power supply; and the source electrode of the second PMOS tube is grounded.
Further, the third power amplifier comprises a second inductor, a third resistor, a third PMOS tube and a fourth PMOS tube;
the grid electrode of the fourth PMOS tube receives the third radio frequency signal; the grid electrode of the fourth PMOS tube is connected with the third resistor and then receives the bias signal; the drain electrode of the fourth PMOS tube is connected with the source electrode of the third PMOS tube, and the source electrode of the fourth PMOS tube is grounded; the grid electrode of the third PMOS tube is connected with a first fixed bias voltage; the drain electrode of the third PMOS tube is connected with one end of the second inductor and is used as the output end of the third power amplifier to output the radio frequency output signal; the other end of the second inductor is connected with a power supply.
Further, the third power amplifier further includes a fifth PMOS MP5;
the grid electrode of the fifth PMOS tube MP5 is connected with a second fixed bias voltage; the source electrode of the fifth PMOS tube MP5 is connected with the drain electrode of the fourth PMOS tube; the drain electrode of the fifth PMOS tube MP5 is connected with one end of the second inductor and is used as the output end of the third power amplifier to output the fourth radio frequency output signal; the other end of the second inductor is connected with a power supply.
Further, the power control circuit also comprises an amplitude detection module, wherein the amplitude detection module is connected with the output end of the third power amplifier and the power control circuit; and the amplitude detection module compares the fourth radio frequency signal output by the third power amplifier with a set threshold value and controls the power control circuit to adjust the magnitude of the bias signal.
Further, the amplitude detection module comprises a sixth PMOS tube, a first capacitor and a fourth resistor;
the drain electrode of the sixth PMOS tube is connected with a power supply, the grid electrode of the sixth PMOS tube receives the fourth radio frequency output signal, the source electrode of the sixth PMOS tube is grounded through the fourth resistor and serves as an output end of the amplitude detection module, and the output end outputs an analog voltage signal; one end of the first capacitor is connected with the output end, and the other end of the first capacitor is grounded.
The invention also provides a CMOS power amplification and power control method, which adopts the CMOS power amplification and power control circuit and comprises the following steps:
the power control circuit receives the voltage signals output by the control chip and provides bias signals for the first power amplifier, the second power amplifier and the third power amplifier;
the first power amplifier controls the second power amplifier to drive the third power amplifier to output the fourth radio frequency output signal;
the amplitude detection module converts the fourth radio frequency output signal output by the third power amplifier into an analog voltage signal and inputs the analog voltage signal to the power control circuit, and a threshold value is arranged in the amplitude detection module; when the analog voltage signal exceeds the set threshold, the power control circuit adjusts the magnitude of the bias signal.
Further, the power control circuit provides a bias voltage or bias current for the first power amplifier, a bias voltage for the second power amplifier, and a bias current for the third power amplifier.
Further, the set threshold includes 5V.
Compared with the prior art, the invention has at least the following beneficial effects:
the invention discards the traditional method for supplying power to the power amplifier circuit by the low-voltage linear voltage stabilizer, adopts the power control circuit to provide bias signals for three power amplifiers in the power amplifier circuit, saves the low-voltage linear voltage stabilizer with larger size under the condition of realizing good power control, and reduces the manufacturing cost of a control chip.
Furthermore, the amplitude detection module designed in the invention can detect the radio frequency output signal output by the third power amplifier in real time, and if the radio frequency output signal is higher than the set threshold value, the bias signal can be adjusted to reduce the amplitude of the output signal of the third power amplifier, so that the breakdown of a device and the burning of a control chip caused by the overlarge output amplitude of the power amplifier are avoided.
Drawings
FIG. 1 is a circuit diagram of a conventional power amplifying circuit in the background art;
FIG. 2 is a block diagram of a CMOS power amplifier and power control circuit according to a first embodiment of the present invention;
fig. 3 is a schematic diagram of a first power amplifier according to a first embodiment of the invention;
fig. 4 is a schematic diagram of a second power amplifier according to an embodiment of the invention
Fig. 5 is a schematic diagram of a third power amplifier according to a first embodiment of the invention;
fig. 6 is a schematic diagram of a third power amplifier according to a first embodiment of the present invention;
FIG. 7 is a block diagram illustrating a CMOS power amplifier and power control circuit according to a first embodiment of the present invention;
FIG. 8 is a schematic diagram of an embodiment of an amplitude detection module;
FIG. 9 is a schematic diagram showing the relationship between the output power of the RF power amplifier and the output voltage signal of the control chip in the second embodiment of the present invention;
FIG. 10 is a graph showing the relationship between the voltage signal and the first bias current in the second embodiment of the present invention;
FIG. 11 is a graph showing the relationship between the voltage signal and the first and second bias voltages in the second embodiment of the present invention;
FIG. 12 is a graph showing the relationship between the voltage signal and the second bias current in the second embodiment of the present invention;
FIG. 13 is a graph showing the relationship between the output voltage of the control chip and the output RF output signal of the power amplifier according to the second embodiment of the present invention;
fig. 14 is a block diagram showing another CMOS power amplifying and power controlling circuit according to the first embodiment of the present invention.
Detailed Description
A CMOS power amplification and power control circuit and control method of the present invention will be described in conjunction with the schematic drawings, in which preferred embodiments of the present invention are shown, it being understood that one skilled in the art could modify the invention described herein while still achieving the advantageous effects of the invention. Accordingly, the following description is to be construed as broadly known to those skilled in the art and not as limiting the invention.
The invention is more particularly described by way of example in the following paragraphs with reference to the drawings. Advantages and features of the invention will become more apparent from the following description and from the claims. It should be noted that the drawings are in a very simplified form and are all to a non-precise scale, merely for convenience and clarity in aiding in the description of embodiments of the invention.
The invention provides a CMOS Power amplifying and Power controlling circuit, referring to FIG. 2, comprising a Power control circuit Power control & Bias, a first Power amplifier Stage1, a second Power amplifier Stage2 and a third Power amplifier Stage3.
The first Power amplifier Stage1, the second Power amplifier Stage2 and the third Power amplifier Stage3 are respectively connected with the Power control circuit Power control & Bias; after receiving the control signal Vramp output by the control chip, the Power control circuit Power control & Bias provides Bias signals for the first Power amplifier Stage1, the second Power amplifier Stage2 and the third Power amplifier Stage3.
The first power amplifier Stage1, the second power amplifier Stage2 and the third power amplifier Stage3 are sequentially connected, the first power amplifier Stage1 receives a radio frequency input signal RFIN, and the first power amplifier Stage1 and the second power amplifier Stage2 drive the third power amplifier Stage3 to output a radio frequency output signal RFOUT.
In the example, the method that the traditional low-voltage linear voltage stabilizer supplies power for the power amplifier circuit is abandoned, the bias signals are provided for three power amplifiers in the power amplifier circuit by adopting the power control circuit, and under the condition of realizing good power control, the low-voltage linear voltage stabilizer with a larger size is omitted, and the manufacturing cost of a control chip is reduced.
In a specific example, the Power control circuit Power control & Bias provides Bias currents for the first Power amplifier Stage1 and the third Power amplifier Stage 3; the Power control circuit Power control & Bias provides Bias voltage for the second Power amplifier Stage 2. That is, the first power amplifier Stage1 and the third power amplifier Stage3 receive the first bias current Ic1 and the second bias current Ic2, respectively, and the second power amplifier Stage2 receives the second bias voltage Vc2.
Preferably, referring to fig. 14, the Power control circuit Power control & Bias may further provide a first Bias voltage to the first Power amplifier Stage1, that is, the final output Power of the third Power amplifier Stage3 may be ensured to reach the desired target by adopting a mode that two first Power amplifiers Stage1 are connected in series with each other and then connected in series with the third Power amplifier Stage3.
Therefore, the Power control circuit Power control & Bias provides Bias signals for three Power amplifiers in the Power amplifying circuit, so that good Power control and amplification can be realized, a low-voltage linear voltage stabilizer with a larger size is omitted, and the manufacturing cost of a control chip is reduced.
Further, the Stage1 circuit of the first power amplifier includes a first PMOS transistor MP1, a first NMOS transistor MN1, and a first resistor R1.
Specifically, referring to fig. 3, a radio frequency input signal ROUT is connected to the gate of the first NMOS transistor MN1, the gate of the first PMOS transistor MP1, and one end of the first resistor; the other end of the first resistor is connected with the drain electrode of the first NMOS tube MN1 and the drain electrode of the first PMOS tube MP1, and is used as the output end of the first power amplifier Stage1 to output a second radio frequency output signal Vin2; the source electrode of the first NMOS tube MN1 is connected with the first bias current Ic; the source electrode of the first PMOS tube MP1 is grounded.
In addition, the source electrode of the first PMOS MP1 may be further connected to a first bias voltage Vc.
Further, the second power amplifier Stage2 includes a second PMOS transistor MN2, a first inductor L1, and a second resistor R2.
Specifically, as shown in fig. 4, the gate of the second PMOS MP2 receives the second rf output signal Vin2 and is connected to one end of the second resistor R2, and the other end of the second resistor R2 is connected to the second bias voltage Vc2; the drain electrode of the second PMOS tube MP2 is connected with one end of the first inductor L1 and is used as the output end of the second power amplifier Stage2 to output a third radio frequency output signal Vin3, and the other end of the first inductor L1 is connected with a power supply; and the source electrode of the second PMOS tube MP2 is grounded.
Further, the third power amplifier Stage3 includes a second inductor L2, a third resistor R3, a third PMOS transistor MP3, and a fourth PMOS transistor MP4.
Specifically, referring to fig. 5, the gate of the fourth PMOS MP4 receives the third rf output signal Vin3; the grid electrode of the fourth PMOS tube MP4 is connected with the third resistor R3 and then receives the second bias current Ic2; the drain electrode of the fourth PMOS tube MP4 is connected with the source electrode of the third PMOS tube MP3, and the source electrode of the fourth PMOS tube MP4 is grounded; the grid electrode of the third PMOS tube MP3 is connected with a first fixed bias voltage Vasc1; the drain electrode of the third PMOS MP3 is connected to one end of the second inductor L2, and is used as the output end of the third power amplifier Stage3, and outputs the fourth radio frequency output signal Vin4; the other end of the second inductor L2 is connected with a power supply.
In addition, the third power amplifier Stage3 may further be: the device comprises a second inductor L2, a third PMOS tube MP3, a fourth PMOS tube MP4 and a fifth PMOS tube MP5;
specifically, referring to fig. 6, the gate of the fifth PMOS MP5 is connected to the second fixed bias voltage Vcas2; the source electrode of the fifth PMOS tube MP5 is connected with the drain electrode of the fourth PMOS tube MP 4; the drain electrode of the fifth PMOS MP5 is connected to one end of the second inductor L2, and is used as the output end of the third power amplifier Stage3, and the output end outputs a fourth rf output signal Vin4; the other end of the second inductor L2 is connected with a power supply.
Further, referring to fig. 5 and fig. 6, the third bias voltage Vc3 is a bias voltage generated by the second bias current Ic2, and the third bias voltage drives the third power amplifier Stage1 to generate the fourth rf output signal Vin4.
And amplifying the radio frequency input signal Vin step by step through the PMOS tubes in the first power amplifier Stage1, the second power amplifier Stage2 and the third power amplifier Stage3, and providing enough power for a control chip.
Further, referring to fig. 7, the CMOS Power amplifying and Power controlling circuit Power control & Bias further includes a magnitude detecting module PD, where the magnitude detecting module PD is connected to the output end of the third Power amplifier Stage3 and the Power controlling circuit Power control & Bias; the amplitude detection module PD compares the fourth radio frequency output signal Vin4 output by the third Power amplifier Stage3 with a set threshold value, and controls the Power control circuit Power control & Bias to adjust the magnitude of the Bias signal until the radio frequency output signal ROUT meeting the condition is output.
In this example, referring to fig. 8, the amplitude detection module includes a sixth PMOS transistor MP6, a first capacitor C1, and a fourth resistor R4.
The drain electrode of the sixth PMOS MP6 is connected to the power supply, the gate electrode of the sixth PMOS MP6 is connected to the fourth rf output signal Vin4, and the source electrode of the sixth PMOS MP6 is grounded through the fourth resistor R4 and is used as the output end of the amplitude detection module PD, where the output end outputs an analog voltage signal; one end of the first capacitor C1 is connected with the output end, and the other end of the first capacitor C is grounded.
In a specific example, the radio frequency output signal ROUT is typically connected to a 50 ohm load through a radio frequency matching network consisting of a capacitor and an inductor.
The amplitude detection module PD detects the amplitude of the fourth radio frequency output signal Vin4 output by the third Power amplifier Stage3 in real time, if the amplitude is higher than a set threshold value, the Power control circuit Power control & Bias can adjust a Bias signal to reduce the amplitude of the fourth radio frequency signal Vin4 output by the third Power amplifier Stage3, and device breakdown and control chip burning caused by overlarge amplitude of the output of the Power amplifier are avoided.
Example two
The embodiment provides a CMOS power amplifying and power controlling method, which comprises the following steps:
after receiving the voltage signal Vramp output by the control chip SOC, the Power control circuit Power control & Bias provides Bias signals for the first Power amplifier Stage1, the second Power amplifier Stage2 and the third Power amplifier Stage3.
The first power amplifier Stage1 controls the second power amplifier Stage2 to drive the third power amplifier Stage3 to output a fourth radio frequency output signal Vin4.
The amplitude detection module PD converts the fourth radio frequency output signal Vin4 output by the third Power amplifier Stage3 into an analog voltage signal, and inputs the analog voltage signal to the Power control circuit Power control & Bias, and a threshold is set in the amplitude detection module PD; when the analog voltage signal exceeds the set threshold, the Power control circuit Power control & Bias adjusts the magnitude of the Bias signal.
Specifically, the rf power amplifier applied to 2G communication needs accurate and real-time power control, and the output power control is implemented by a control signal, where the control signal is a voltage signal Vramp output by the control chip SOC, and specifically, the relationship between the output power of the rf power amplifier and the control signal Vramp is shown in fig. 9.
Further, as shown in fig. 13, three points (Vcal, pcal), (Vrat, prat), and (Vsat, psa) in fig. 12 correspond to the calibration power, the rated power, and the saturated power, respectively. The control chip SOC will perform system calibration according to fig. 9, thereby precisely controlling the output power.
In this example, the first power amplifier Stage1, the second power amplifier Stage2, and the third power amplifier Stage3 are sequentially connected; the Power control circuit Power control & Bias provides Bias current for the first Power amplifier Stage1 and the third Power amplifier Stage 3; the Power control circuit Power control & Bias provides Bias voltage for the second Power amplifier Stage 2.
Preferably, the Power control circuit Power control & Bias may also provide a Bias voltage for the first Power amplifier Stage 1.
Specifically, the relationship between the bias signal and the voltage signal Vramp output by the control chip SOC is shown in fig. 10, 11 and 12, where the bias voltage and the bias current show a linear amplifying trend with the increase of the control chip SOC input voltage Vramp after the v_offset point. The control manner described in the above embodiment can ensure that the final output power of the third power amplifier Stage3 and the output voltage of the control chip SOC have a curve relationship as shown in fig. 12.
In a specific embodiment, the set threshold is 5V. It should be noted that the threshold is not limited thereto, and those skilled in the art can flexibly adjust the threshold according to actual needs.
Further, the Power control circuit Power control & Bias and the amplitude detection module PD form a feedback loop, and the amplitude detection module PD converts the fourth radio frequency output signal Vin4 output by the third Power amplifier Stage3 into an analog voltage signal and inputs the analog voltage signal to the Power control circuit Power control & Bias. When the Power control circuit Power control & Bias detects that the amplitude of the fourth radio frequency output signal Vin4 exceeds a certain threshold value, the module can automatically adjust the offset of the offset signal, so that the amplitude of the fourth radio frequency output signal Vin4 is reduced, an ideal radio frequency output signal VOUT is obtained, and device breakdown and control chip SOC burnout caused by overlarge output amplitude of a Power amplifier are avoided.
In summary, the method of supplying Power to the Power amplifier circuit by the conventional low-voltage linear voltage regulator is abandoned, the Power control circuit Power control & Bias is adopted to provide Bias signals for three Power amplifiers in the Power amplifier circuit, and under the condition of realizing good Power control, the low-voltage linear voltage regulator with larger size is omitted, and the manufacturing cost of the control chip SOC is reduced.
Further, the amplitude detection module designed in this example can detect the fourth radio frequency output signal Vin4 output by the third power amplifier Stage3 in real time, and if the fourth radio frequency output signal Vin4 is higher than the set threshold, the bias signal is adjusted to reduce the amplitude of the output signal of the third power amplifier Stage3, so as to avoid breakdown of devices and burning of the control chip caused by overlarge output amplitude of the power amplifier.
It will be apparent to those skilled in the art that various modifications and variations can be made to the present invention without departing from the spirit or scope of the invention. Thus, it is intended that the present invention also include such modifications and alterations insofar as they come within the scope of the appended claims or the equivalents thereof.

Claims (10)

1. A CMOS power amplifying and power controlling circuit is characterized by comprising a power controlling circuit, a first power amplifier, a second power amplifier and a third power amplifier;
the first power amplifier, the second power amplifier and the third power amplifier are respectively connected with the power control circuit; the power control circuit receives the voltage signals output by the control chip and provides bias signals for the first power amplifier, the second power amplifier and the third power amplifier;
the first power amplifier, the second power amplifier and the third power amplifier are sequentially connected, and the first power amplifier and the second power amplifier drive the third power amplifier to output radio frequency output signals.
2. The CMOS power amplifying and power controlling circuit of claim 1, wherein the first power amplifier circuit comprises a first NMOS transistor, a first PMOS transistor, and a first resistor;
the radio frequency input signal is connected with the grid electrode of the first NMOS tube, the grid electrode of the first PMOS tube and one end of the first resistor; the other end of the first resistor is connected with the drain electrode of the first NMOS tube and the drain electrode of the first PMOS tube, and is used as the output end of the first power amplifier to output a second radio frequency output signal; the source electrode of the first NMOS tube is connected with the bias signal; and the source electrode of the first PMOS tube is grounded.
3. The CMOS power amplifying and power controlling circuit according to claim 2, wherein the second power amplifier comprises a second PMOS transistor, a first inductor and a second resistor;
the grid electrode of the second PMOS tube receives the second radio frequency signal and is connected with one end of the second resistor, and the other end of the second resistor is connected with the bias signal; the drain electrode of the second PMOS tube is connected with one end of the first inductor and is used as the output end of the second power amplifier to output a third radio frequency signal, and the other end of the first inductor is connected with a power supply; and the source electrode of the second PMOS tube is grounded.
4. The CMOS power amplifying and power controlling circuit according to claim 3, wherein the third power amplifier comprises a second inductor, a third resistor, a third PMOS transistor and a fourth PMOS transistor;
the grid electrode of the fourth PMOS tube receives the third radio frequency signal; the grid electrode of the fourth PMOS tube is connected with the third resistor and then receives the bias signal; the drain electrode of the fourth PMOS tube is connected with the source electrode of the third PMOS tube, and the source electrode of the fourth PMOS tube is grounded; the grid electrode of the third PMOS tube is connected with a first fixed bias voltage; the drain electrode of the third PMOS tube is connected with one end of the second inductor and is used as the output end of the third power amplifier to output a fourth radio frequency output signal; the other end of the second inductor is connected with a power supply.
5. The CMOS power amplifying and power controlling circuit according to claim 4, wherein said third power amplifier further comprises a fifth PMOS transistor MP5;
the grid electrode of the fifth PMOS tube MP5 is connected with a second fixed bias voltage; the source electrode of the fifth PMOS tube MP5 is connected with the drain electrode of the fourth PMOS tube; the drain electrode of the fifth PMOS tube MP5 is connected with one end of the second inductor and is used as the output end of the third power amplifier to output the fourth radio frequency output signal; the other end of the second inductor is connected with a power supply.
6. The CMOS power amplifying and power controlling circuit according to claim 5, further comprising an amplitude detecting module, said amplitude detecting module being connected to an output of said third power amplifier and to said power controlling circuit; and the amplitude detection module compares the fourth radio frequency signal output by the third power amplifier with a set threshold value and controls the power control circuit to adjust the magnitude of the bias signal.
7. The CMOS power amplifying and power controlling circuit according to claim 6, wherein the amplitude detecting module comprises a sixth PMOS transistor, a first capacitor and a fourth resistor;
the drain electrode of the sixth PMOS tube is connected with a power supply, the grid electrode of the sixth PMOS tube receives the fourth radio frequency output signal, the source electrode of the sixth PMOS tube is grounded through the fourth resistor and serves as an output end of the amplitude detection module, and the output end outputs an analog voltage signal; one end of the first capacitor is connected with the output end, and the other end of the first capacitor is grounded.
8. A CMOS power amplification and power control method employing the CMOS power amplification and power control circuit according to any one of claims 1 to 7, comprising the steps of:
the power control circuit receives the voltage signals output by the control chip and provides bias signals for the first power amplifier, the second power amplifier and the third power amplifier;
the first power amplifier controls the second power amplifier to drive the third power amplifier to output the fourth radio frequency output signal;
the amplitude detection module converts the fourth radio frequency output signal output by the third power amplifier into an analog voltage signal and inputs the analog voltage signal to the power control circuit, and a threshold value is arranged in the amplitude detection module; when the analog voltage signal exceeds the set threshold, the power control circuit adjusts the magnitude of the bias signal.
9. The CMOS power amplification and power control method of claim 8, wherein the power control circuit provides a bias voltage or bias current for the first power amplifier, a bias voltage for the second power amplifier, and a bias current for the third power amplifier.
10. The CMOS power amplification and power control method of claim 8, wherein the set threshold comprises 5V.
CN202310125738.XA 2023-02-16 2023-02-16 CMOS power amplification and power control circuit and control method Pending CN116366013A (en)

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