CN116365610B

CN116365610B - New energy station power rapid control platform based on multi-core heterogeneous hardware platform

Info

Publication number: CN116365610B
Application number: CN202310621585.8A
Authority: CN
Inventors: 许一泽; 杨铎炯; 马溪原; 林振福; 陈炎森; 徐全; 聂智杰; 曾博儒; 王鹏宇; 葛俊; 潘世贤; 俞靖一; 张子昊; 程凯
Original assignee: Southern Power Grid Digital Grid Research Institute Co Ltd
Current assignee: Southern Power Grid Digital Grid Research Institute Co Ltd
Priority date: 2023-05-30
Filing date: 2023-05-30
Publication date: 2023-09-15
Anticipated expiration: 2043-05-30
Also published as: CN116365610A

Abstract

The application relates to a new energy station power rapid control platform and method based on a multi-core heterogeneous hardware platform. The method comprises the following steps: sending a calculation result data packet to the main chip and the auxiliary chip through the FPGA chip; inputting the calculation result data packet into an automatic power generation control calculation program loaded by a main chip through the main chip to obtain a first active output instruction, and sending the first active output instruction to a co-chip; inputting the calculation result data packet, the first active output instruction and preset primary frequency modulation calculation parameters into a primary frequency modulation calculation program loaded by the auxiliary chip through the auxiliary chip to obtain a second active output instruction; and inputting the calculation result data packet, the second active output instruction and the preset inertia control calculation parameter into an inertia control calculation program loaded by the auxiliary chip through the auxiliary chip to obtain a third active output instruction. By adopting the method, the power control efficiency of the new energy station can be improved.

Description

New energy station power rapid control platform based on multi-core heterogeneous hardware platform

Technical Field

The application relates to the technical field of new energy, in particular to a method, a device, a platform and a storage medium for quickly controlling power of a new energy station based on a multi-core heterogeneous hardware platform.

Background

With the development of new energy generating technology and the improvement of new energy generating capacity, the construction and operation of new energy stations are paid more attention.

At present, most of new energy station control systems adopt a single processor to control power. However, the single processor has limited computing power, and cannot meet the power control requirements of the new energy station on a large scale, high efficiency and high real-time, so that the power control efficiency of the new energy station is low, the full-field power cannot be reasonably distributed, and the operation of the new energy station is not stable enough.

Therefore, the conventional technology has a problem in that power control efficiency for the new energy station is not high.

Disclosure of Invention

In view of the foregoing, it is desirable to provide a method, an apparatus, a computer device, a computer readable storage medium, and a computer program product for fast power control of a new energy station based on a multi-core heterogeneous hardware platform, which can improve power control efficiency of the new energy station.

The method is characterized by being applied to a power distribution computing circuit, wherein the power distribution computing circuit comprises a main chip, a co-chip and an FPGA chip, and the method comprises the following steps:

Sending a calculation result data packet to the main chip and the auxiliary chip through the FPGA chip; the data in the calculation result data packet is obtained by calculating the acquired current and voltage analog signals through the FPGA chip;

inputting the calculation result data packet into an automatic power generation control calculation program loaded by a main chip through the main chip to obtain a first active output instruction, and sending the first active output instruction to a co-chip;

inputting the calculation result data packet, the first active output instruction and preset primary frequency modulation calculation parameters into a primary frequency modulation calculation program loaded by the auxiliary chip through the auxiliary chip to obtain a second active output instruction;

inputting the calculation result data packet, the second active output instruction and preset inertia control calculation parameters into an inertia control calculation program loaded by the auxiliary chip through the auxiliary chip to obtain a third active output instruction; the third active power output instruction is used for indicating active power distribution to each controlled device in the new energy station.

In one embodiment, the step of inputting the calculation result data packet, the first active output instruction and the preset primary frequency modulation calculation parameter to a primary frequency modulation calculation program loaded by the co-chip through the co-chip to obtain a second active output instruction includes:

Determining whether the current frequency is in the frequency adjustment dead zone range or not according to the real-time active power of the new energy station and the grid frequency deviation amount information of the new energy station through a primary frequency modulation calculation program; the real-time active power and the power grid frequency deviation amount information are determined according to the calculation result data packet;

under the condition that the current frequency exceeds the frequency adjustment dead zone range, determining a primary frequency modulation additional power instruction according to a preset primary frequency modulation calculation parameter by a primary frequency modulation calculation program;

and determining a second active output command according to the first active output command and the primary frequency modulation additional power command through a primary frequency modulation calculation program.

In one embodiment, the calculating result data packet, the second active output instruction and the preset inertia control calculating parameter are input to an inertia control calculating program loaded by the co-chip through the co-chip, so as to obtain a third active output instruction, which includes:

determining whether the current frequency change rate is in the frequency change rate regulation dead zone range or not according to the real-time active power of the new energy station and the power grid frequency change rate information of the new energy station through an inertia control calculation program; the power grid frequency change rate information is determined according to the calculation result data packet;

Under the condition that the current frequency change rate exceeds the frequency change rate regulation dead zone range, determining an inertia control additional power instruction according to preset inertia control calculation parameters by an inertia control calculation program;

and determining a third active output command according to the second active output command and the inertia control additional power command through an inertia control calculation program.

In one embodiment, the method further comprises:

decomposing a third active output instruction through a synergistic chip to obtain an active output instruction corresponding to each controlled device;

and sending each active output instruction to corresponding controlled equipment through the co-chip.

In one embodiment, the method further comprises:

collecting current and voltage analog signals of each controlled device and the grid-connected point in the new energy station through an FPGA chip to obtain a sampling result;

and inputting the sampling result into a fast Fourier transform calculation program built in an FPGA chip through the FPGA to obtain a calculation result data packet.

In one embodiment, the method further comprises:

inputting the calculation result data packet into an automatic voltage control calculation program loaded by the main chip through the main chip to obtain a reactive power output total instruction; the reactive power output total instruction is used for indicating reactive power distribution to each controlled device in the new energy station;

Decomposing the total reactive output command through the main chip to obtain a reactive output command corresponding to each controlled device;

and sending each reactive power output instruction to corresponding controlled equipment through the main chip.

In one embodiment, the method further comprises:

acquiring primary frequency modulation calculation parameters and inertia control calculation parameters through a main chip, and sending the primary frequency modulation calculation parameters and the inertia control calculation parameters to a co-chip;

and caching the primary frequency modulation calculation parameters and the inertia control calculation parameters through the co-chip.

The utility model provides a new energy station power quick control device based on heterogeneous hardware platform of multicore, its characterized in that is applied to power distribution calculation circuit, and power distribution calculation circuit includes main chip, cooperation chip and FPGA chip, and the device includes:

the sending module is used for sending the calculation result data packet to the main chip and the auxiliary chip through the FPGA chip; the data in the calculation result data packet is obtained by calculating the acquired current and voltage analog signals through the FPGA chip;

the first input module is used for inputting the calculation result data packet into an automatic power generation control calculation program loaded by the main chip through the main chip to obtain a first active output instruction, and sending the first active output instruction to the auxiliary chip;

The second input module is used for inputting the calculation result data packet, the first active output instruction and preset primary frequency modulation calculation parameters into a primary frequency modulation calculation program loaded by the auxiliary chip through the auxiliary chip to obtain a second active output instruction;

the third input module is used for inputting the calculation result data packet, the second active output instruction and the preset inertia control calculation parameter into an inertia control calculation program loaded by the auxiliary chip through the auxiliary chip to obtain a third active output instruction; the third active power output instruction is used for indicating active power distribution to each controlled device in the new energy station.

The new energy station power rapid control platform based on the multi-core heterogeneous hardware platform is characterized by comprising a power distribution computing circuit, wherein the power distribution computing circuit comprises a main chip, a co-chip and an FPGA chip;

the FPGA chip is used for sending the calculation result data packet to the main chip and the assistant chip; the data in the calculation result data packet is obtained by calculating the acquired current and voltage analog signals through the FPGA chip;

the main chip is used for inputting the calculation result data packet into an automatic power generation control calculation program loaded by the main chip to obtain a first active output instruction, and sending the first active output instruction to the auxiliary chip;

The auxiliary chip is used for inputting the calculation result data packet, the first active output instruction and preset primary frequency modulation calculation parameters into a primary frequency modulation calculation program loaded by the auxiliary chip to obtain a second active output instruction; inputting the calculation result data packet, the second active output instruction and preset inertia control calculation parameters into an inertia control calculation program loaded by the co-chip to obtain a third active output instruction; the third active power output instruction is used for indicating active power distribution to each controlled device in the new energy station.

A computer readable storage medium having stored thereon a computer program, characterized in that the computer program when executed by a processor realizes the steps of the above-mentioned method.

The method, the device, the computer equipment, the storage medium and the computer program product for quickly controlling the power of the new energy station based on the multi-core heterogeneous hardware platform send a calculation result data packet to the main chip and the auxiliary chip through the FPGA chip; the data in the calculation result data packet is obtained by calculating the acquired current and voltage analog signals through the FPGA chip; inputting the calculation result data packet into an automatic power generation control calculation program loaded by a main chip through the main chip to obtain a first active output instruction, and sending the first active output instruction to a co-chip; inputting the calculation result data packet, the first active output instruction and preset primary frequency modulation calculation parameters into a primary frequency modulation calculation program loaded by the auxiliary chip through the auxiliary chip to obtain a second active output instruction; inputting the calculation result data packet, the second active output instruction and preset inertia control calculation parameters into an inertia control calculation program loaded by the auxiliary chip through the auxiliary chip to obtain a third active output instruction; the third active power output instruction is used for indicating active power distribution to each controlled device in the new energy station; therefore, different calculation tasks can be realized through the FPGA chip, the main chip and the auxiliary chip, the advantages of different chip processors can be fully utilized, and the power can be rapidly and accurately calculated, so that the power control efficiency and the power control precision of each controlled device in the new energy station are improved, and the operation stability and the safety of the new energy station are favorably maintained.

Drawings

FIG. 1 is an application environment diagram of a new energy station power rapid control method based on a multi-core heterogeneous hardware platform in one embodiment;

FIG. 2 is a flow chart of a method for fast controlling power of a new energy station based on a multi-core heterogeneous hardware platform in an embodiment;

FIG. 3 is a schematic diagram of a CPU board in one embodiment;

FIG. 4 is a schematic diagram of a method for implementing power allocation for a new energy station in one embodiment;

FIG. 5 is a flow chart of a method for fast controlling power of a new energy station based on a heterogeneous multi-core hardware platform in another embodiment;

FIG. 6 is a block diagram of a fast power control device for a new energy station based on a heterogeneous multi-core hardware platform in one embodiment;

fig. 7 is an internal structural diagram of a computer device in one embodiment.

Detailed Description

The present application will be described in further detail with reference to the drawings and examples, in order to make the objects, technical solutions and advantages of the present application more apparent. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the application.

It should be noted that the terms "first," "second," and the like in the description and claims of the present disclosure and in the foregoing figures are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate such that the embodiments of the disclosure described herein may be capable of operation in sequences other than those illustrated or described herein. The implementations described in the following exemplary examples are not representative of all implementations consistent with the present disclosure. Rather, they are merely examples of apparatus and methods consistent with certain aspects of the present disclosure.

The method for rapidly controlling the power of the new energy station based on the multi-core heterogeneous hardware platform can be applied to an application environment shown in fig. 1. Wherein the power distribution circuit 102 communicates with the controlled device 104 via a data bus 106. The power distribution circuit 102 sends a calculation result data packet to the main chip and the auxiliary chip through the FPGA chip; the data in the calculation result data packet is obtained by calculating the acquired current and voltage analog signals through the FPGA chip; the power distribution circuit 102 inputs the calculation result data packet into an automatic power generation control calculation program loaded by the main chip through the main chip to obtain a first active output instruction, and sends the first active output instruction to the auxiliary chip; the power distribution circuit 102 inputs the calculation result data packet, the first active output instruction and preset primary frequency modulation calculation parameters to a primary frequency modulation calculation program loaded by the co-chip through the co-chip to obtain a second active output instruction; the power distribution circuit 102 inputs the calculation result data packet, the second active output instruction and preset inertia control calculation parameters to an inertia control calculation program loaded by the auxiliary chip through the auxiliary chip to obtain a third active output instruction; the third active power output instruction is used for indicating active power distribution to each controlled device in the new energy station. The power distribution circuit 102 distributes active power to each controlled device 104 in the new energy station according to the third active power output command. Wherein the power distribution circuit 102 may be a CPU circuit board, and the controlled device 104 may be, but is not limited to, various power devices.

In one embodiment, as shown in fig. 2, a method for quickly controlling power of a new energy station based on a heterogeneous multi-core hardware platform is provided, and the method is applied to the power distribution circuit 102 in fig. 1 for illustration, and includes the following steps:

step S202, sending a calculation result data packet to a main chip and a co-chip through an FPGA chip; the data in the calculation result data packet is obtained by calculating the acquired current-voltage analog signals through the FPGA chip.

The calculation result data packet may be a data packet obtained by acquiring and calculating current and voltage model signals of the controlled device and the grid-connected point by the FPGA chip. In practical application, the data in the calculation result data packet may be current voltage amplitude and frequency data obtained by inputting the acquisition signal to a fast fourier transform calculation program built in the FPGA chip.

The main chip can be an ARM Cortex-A main chip.

The co-chip can be an ARM Cortex-M co-chip.

In specific implementation, the power distribution circuit sends the calculation result data packet to the main chip and the auxiliary chip through the FPGA chip.

Step S204, the main chip inputs the calculation result data packet into an automatic power generation control calculation program loaded by the main chip to obtain a first active output instruction, and the first active output instruction is sent to the auxiliary chip.

The automatic power generation control calculation program can be an AGC power control calculation program, in practical application, the AGC power control calculation program can control the whole-field power to output according to a scheduling target power curve by combining a scheduling side target power curve forwarded by a comprehensive self-system, and the total active output total instruction Pagc of the wind power plant (photovoltaic power station) is obtained.

The first active output command may be a total full-field active output command Pagc output by the automatic power generation control calculation program.

In a specific implementation, the power distribution circuit inputs a calculation result data packet into an AGC power control calculation program loaded by the main chip through the main chip, and outputs a first active output instruction Pagc through the AGC power control calculation program.

In practical application, the main chip receives 1 group of data of current voltage effective values and 1 group of frequency data of current voltage waveforms sent by the FPGA every 50ms, so as to enter an AGC power control calculation program to calculate an active output total instruction, namely a first active output instruction Pagc. The main chip also transmits a first active output instruction Pagc to the auxiliary chip through Mailbox (hardware mechanism of inter-processor process synchronization and data exchange in the multiprocessor system) inter-core communication so as to calculate primary frequency modulation additional power. The real-time performance requirement of the AGC power control calculation program on the main chip is not high, and a time axis is not required to be unified with the co-chip during operation.

The AGC power control calculation is based on real-time active power output of an electric field, combines a dispatching side target power curve forwarded by a comprehensive self-system, considers the generating potential condition of a wind turbine generator, controls full-field power to output according to the dispatching target power curve, and obtains a full-field active output total instruction Pagc of the wind power field (photovoltaic power station), which is equivalent to a first active output instruction.

Step S206, the calculated result data packet, the first active output instruction and the preset primary frequency modulation calculation parameter are input into a primary frequency modulation calculation program loaded by the co-chip through the co-chip, and a second active output instruction is obtained.

The preset primary frequency modulation calculation parameter may be a calculation parameter required for calculating the primary frequency modulation additional power. The preset primary frequency modulation calculation parameters are sent by the main chip.

The primary frequency modulation calculation program may be a calculation program for outputting a primary frequency modulation additional power instruction.

The second active power output command may be a command in which a primary frequency modulation additional power command is superimposed on the first active power output command.

In a specific implementation, the power distribution circuit inputs a calculation result data packet, a first active output instruction Pagc and preset primary frequency modulation calculation parameters to a primary frequency modulation calculation program loaded by the co-chip to obtain a second active output instruction, wherein the second active output instruction (Pagc plus p 1) is the first active output instruction Pagc plus the primary frequency modulation additional power instruction p1.

In practical application, the primary frequency modulation calculation program in the co-chip outputs a second active output instruction (Pagc plus p 1) according to the data of 1 group of current voltage effective values and the frequency data of 1 group of current voltage waveforms sent by the FPGA chip (sent by the FPGA chip every 50 ms), the preset primary frequency modulation calculation parameter sent by the main chip, and the first active output instruction Pagc sent by the main chip. And the main chip sends a second active output instruction (Pagc plus p 1) to the auxiliary chip through Mailbox inter-core communication to carry out the calculation task of controlling the additional power by the inertia of the corresponding time axis.

Step S208, inputting the calculation result data packet, the second active output instruction and the preset inertia control calculation parameter into an inertia control calculation program loaded by the assistant chip through the assistant chip to obtain a third active output instruction; the third active power output instruction is used for indicating active power distribution to each controlled device in the new energy station.

The preset inertia control calculation parameter may be a calculation parameter required for calculating the inertia control additional power. The preset inertia control calculation parameters are sent by the main chip.

The inertia control calculation program may be a calculation program for outputting an inertia control additional power instruction.

The third active power output command may be a command in which a primary frequency modulation additional power command and an inertia control additional power command are superimposed on the basis of the first active power output command.

The new energy station can refer to a wind power station or a photovoltaic power station.

The controlled equipment can be various power equipment in the new energy station.

In a specific implementation, the power distribution circuit inputs a calculation result data packet, a second active output instruction (Pagc plus p 1) and preset inertia control calculation parameters to an inertia control calculation program loaded by the co-chip to obtain a third active output instruction, wherein the third active output instruction (Pagc plus p1 plus p 2) is the second active output instruction (Pagc plus p 1) plus an inertia control additional power instruction p2, and meanwhile, the third active output instruction (Pagc plus p1 plus p 2) can be the first active output instruction Pagc plus a primary frequency modulation additional power instruction p1 plus an inertia control additional power instruction p2.

In practical application, the final active output command is the algebraic sum of the AGC target power command and the additional control power command (the primary frequency modulation additional power command p1 and the inertia control additional power command p 2), and when the AGC target power command and the additional control power command are in a control direction opposite to each other, the additional control power command is locked, so that the final power command of the power control system is obtained. And finally, based on a final power instruction, combining the real-time state and the generating potential of each unit, distributing the full-field power among different units to obtain the control target power Pi and Qi of each unit.

In practical application, the inertia control calculation program in the co-chip outputs a third active output instruction (Pagc plus p1 plus p 2) according to the data of 1 group of current voltage effective values and the frequency data of 1 group of current voltage waveforms sent by the FPGA chip (sent by the FPGA chip every 50 ms), the preset inertia control calculation parameters sent by the main chip, and the second active output instruction (Pagc plus p 1). The third active force command is transmitted to the communication board card through the data bus, and is sent to each controlled device through an RJ45 (a data interface for data transmission) port.

The calculation of inertia control takes 100ms as a time window, data packet 1 and data packet 2 of two adjacent times transmitted by an FPGA chip are calculated and obtained, p2 is calculated by using frequency difference value F twice within 100ms, p2 is k multiplied by F, and k is an inertia control calculation parameter. After the calculation period of inertia control is finished, the calculation window is shifted to the right by 50ms, and then new calculation is started, namely, the data packet 2 and the data packet 3 which are transmitted by the FPGA chip and have two adjacent times are calculated and acquired, and the like.

For the convenience of understanding of those skilled in the art, the following exemplary provides a new energy station power fast control platform applicable to a new energy station power fast control method based on a multi-core heterogeneous hardware platform, and the platform is divided into three parts, namely an interface board card, a data bus and a CPU board card.

The interface board card adopts a modularized and expandable design and is divided into: the switch-in switch-out board card is used for receiving and transmitting switch-on/off IO signals and instructions; the network communication board card adopts communication based on TCP protocol and is used for receiving and transmitting device information and other data with low real-time requirements on the south and north devices; the AC/DC sampling board is used for collecting analog quantity of a measurement point PT (potential transformer) and a CT (current transformer), and voltage, current amplitude and frequency data with a time mark are obtained by sampling and calculating analog quantity voltage and current.

The CPU board card can be used as a power distribution circuit, and a plurality of heterogeneous processors are arranged on the CPU board card and are communicated through a Mailbox.

AMP (asymmetric multiprocessing) mode can be used on software based on the hardware basis of the CPU board. The AMP mode realizes high-efficiency communication and data exchange by independently running different operating systems or bare metal programs on a plurality of heterogeneous processors and simultaneously using mechanisms such as Mailbox, shared memory and the like, and finally realizes multi-core high-efficiency cooperative work. After the chip is electrified, ARM Cortex-A is used as a main CPU running first software, and a user can start a coprocessor (ARM Cortex-M) on the main CPU software to be in an idle state (standby state) by default, and the coprocessor continuously reads whether a flag in a system control module is set or not so as to determine whether the coprocessor is in the idle state (standby state) or jumps to a specified position to execute according to configuration.

When the novel energy station power rapid control platform is electrified on a chip, ARM Cortex-A is used as a main CPU to run Uboot (a section of bare metal program for starting an operating system kernel), and then the Uboot carries ARM Cortex-M bare metal program and FPGA bare metal program to the memory of each chip. After the bare engine program is carried, uboot continues to guide the subsequent processes of loading Linux and the like by the kernel of the operating system, wherein the starting time sequence is as the CPU board card module in FIG. 3.

In this embodiment, since the real-time requirement of AGC (Automatic Generation Control, automatic power generation control)/AVC (Automatic Voltage Control ) power control calculation is low and the real-time requirement of primary frequency modulation and inertia control technology is high, the AGC/AVC power control calculation is loaded on an ARM Cortex-a main chip, and is run on a Linux system, and the primary frequency modulation and inertia control function is loaded on an ARM Cortex-M co-chip, and is run as a bare system.

For the convenience of understanding of those skilled in the art, fig. 4 exemplarily provides a method schematic diagram for implementing power distribution to a new energy station through an ARM Cortex-a main chip and a Cortex-M co-chip on a CPU board.

The ARM Cortex-A main chip realizes AGC/AVC power control calculation, data analysis (advanced application) and parameter configuration management; the ARM Cortex-M co-chip realizes a primary frequency modulation function and an inertia control function; the FPGA chip realizes data acquisition and data processing.

The FPGA chip sends calculation result data packets of every 50ms to the ARM Cortex-A main chip and the ARM Cortex-M auxiliary chip (the sampling frequency of the FPGA chip is 10kHz, the calculation result data packets are sent to other upper functional chips once through the Mailbox of the chip every 50ms, which is equivalent to 500 times of sampling of each data packet, and the FPGA chip is synchronized with clocks when the ARM Cortex-M auxiliary chip carries out primary frequency modulation additional power calculation and inertia control additional power calculation).

The AVC calculation program of the ARM Cortex-A main chip outputs an AVC command (Qavc) according to the data packet of the calculation result, and the ARM Cortex-A main chip decomposes the AVC command Qavc into reactive commands Qi of each controlled device i, transmits the reactive commands Qi to the communication board through the data bus and sends the reactive commands Qi to each controlled device through the RJ45 port. The switch commands and switch measurement states shown in fig. 4 are also transmitted to the switch in/out board card via the data bus to interact with each controlled device by the hard-wired side.

The AGC calculation program of the ARM Cortex-A main chip outputs an active command 1Pagc (corresponding to a first active output command) according to a calculation result data packet, and the active command is sent to the ARM Cortex-M co-chip primary frequency modulation function module through Mailbox inter-core communication.

The primary frequency modulation calculation program in the ARM Cortex-M co-chip outputs an active command 2 (corresponding to a second active output command) according to the primary frequency modulation calculation parameters and the calculation result data packet in the parameter configuration management of the ARM Cortex-A main chip, and sends the active command 2 to the ARM Cortex-M co-chip inertia control function module through Mailbox inter-core communication.

The inertia control calculation program in the ARM Cortex-M co-chip outputs an active command 3 (equivalent to a third active output command) according to inertia control calculation parameters and calculation result data packets in parameter configuration management of the ARM Cortex-A main chip, and the active command 3 is transmitted to the communication board card through the data bus and is sent to the controlled equipment through the RJ45 port.

The method for realizing power distribution to the new energy station through the ARM Cortex-A main chip and the Cortex-M co-chip on the CPU board card has the advantages of simple communication, easy realization of programming, strong adaptability and the like.

In another embodiment, the step of inputting the calculation result data packet, the first active output instruction and the preset primary frequency modulation calculation parameter to the primary frequency modulation calculation program loaded by the co-chip through the co-chip to obtain the second active output instruction includes: determining whether the current frequency is in the frequency adjustment dead zone range or not according to the real-time active power of the new energy station and the grid frequency deviation amount information of the new energy station through a primary frequency modulation calculation program; the real-time active power and the power grid frequency deviation amount information are determined according to the calculation result data packet; under the condition that the current frequency exceeds the frequency adjustment dead zone range, determining a primary frequency modulation additional power instruction according to a preset primary frequency modulation calculation parameter by a primary frequency modulation calculation program; and determining a second active output command according to the first active output command and the primary frequency modulation additional power command through a primary frequency modulation calculation program.

The grid frequency deviation amount information may refer to a difference between an actual frequency and a nominal frequency.

The frequency adjustment dead zone range may be a frequency difference set to prevent unnecessary actions of the turbine tuning when the grid frequency difference is changed in a small range.

The primary frequency modulation additional power command may be a command for indicating that the grid frequency is differentially adjusted to mitigate the degree of change in the grid frequency.

In specific implementation, the power distribution circuit determines whether the current frequency is within a frequency adjustment dead zone range according to real-time active power of the new energy station and grid frequency deviation amount information of the new energy station through a primary frequency modulation calculation program in the co-chip, calculates a primary frequency modulation additional power instruction p1 of the new energy station (wind power plant/photovoltaic power plant) according to a preset primary frequency modulation calculation parameter through the primary frequency modulation calculation program under the condition that the current frequency exceeds the frequency adjustment dead zone range, and determines a second active power output instruction Pagc plus p1 according to the first active power output instruction Pagc and the primary frequency modulation additional power instruction Pagc through the primary frequency modulation calculation program.

In practical application, whether the current frequency is in the regulation dead zone range is analyzed according to the real-time power of the electric field and the frequency deviation amount information of the power grid and by combining an active-frequency droop control characteristic curve.

According to the technical scheme of the embodiment, whether the current frequency is in the frequency adjustment dead zone range is determined through a primary frequency modulation calculation program according to the real-time active power of the new energy station and the power grid frequency deviation amount information of the new energy station; the real-time active power and the power grid frequency deviation amount information are determined according to the calculation result data packet; under the condition that the current frequency exceeds the frequency adjustment dead zone range, determining a primary frequency modulation additional power instruction according to a preset primary frequency modulation calculation parameter by a primary frequency modulation calculation program; determining a second active output command according to the first active output command and the primary frequency modulation additional power command through a primary frequency modulation calculation program; therefore, the second active output command can be accurately determined, and more accurate power control is facilitated.

In another embodiment, the calculating result data packet, the second active output instruction and the preset inertia control calculating parameter are input to an inertia control calculating program loaded by the co-chip through the co-chip, so as to obtain a third active output instruction, including: determining whether the current frequency change rate is in the frequency change rate regulation dead zone range or not according to the real-time active power of the new energy station and the power grid frequency change rate information of the new energy station through an inertia control calculation program; the power grid frequency change rate information is determined according to the calculation result data packet; under the condition that the current frequency change rate exceeds the frequency change rate regulation dead zone range, determining an inertia control additional power instruction according to preset inertia control calculation parameters by an inertia control calculation program; and determining a third active output command according to the second active output command and the inertia control additional power command through an inertia control calculation program.

The grid frequency change rate information may refer to a change rate of the grid frequency.

The current frequency change rate may be a conversion rate of the current grid frequency.

The preset inertia control calculation parameter may be a calculation parameter required for calculating the inertia control additional power.

The inertia control additional power command may refer to a command for instructing a control power system to perform a quick response, among other things. The virtual inertia of the power system adopts a modern control technology, and the inertia response of the power system is realized through the quick response control of the power system, so that the stability and the reliability of the power system are improved.

In specific implementation, the power distribution circuit determines whether the current frequency change rate is within the frequency change rate adjustment dead zone range according to real-time active power of the new energy station and change rate information of the power grid frequency of the new energy station through an inertia control calculation program in the co-chip, and under the condition that the current frequency change rate is determined to exceed the frequency change rate adjustment dead zone range, the power distribution circuit calculates the required amount p2 of active output change of the new energy station (wind power station/photovoltaic power station) according to preset inertia control calculation parameters through the inertia control calculation program, namely determines an inertia control additional power instruction, and determines a third active output instruction Pagc plus p1 plus p2, namely a final active output total instruction according to the second active output instruction Pagc plus p1 and the inertia control additional power instruction p2 through the inertia control calculation program.

According to the technical scheme of the embodiment, whether the current frequency change rate is in the frequency change rate adjustment dead zone range is determined through an inertia control calculation program according to the real-time active power of the new energy station and the power grid frequency change rate information of the new energy station; the power grid frequency change rate information is determined according to the calculation result data packet; under the condition that the current frequency change rate exceeds the frequency change rate regulation dead zone range, determining an inertia control additional power instruction according to preset inertia control calculation parameters by an inertia control calculation program; determining a third active output command according to the second active output command and the inertia control additional power command through an inertia control calculation program; therefore, the third active output instruction can be accurately determined, active power can be accurately distributed to each controlled device, and accurate power control is facilitated.

In another embodiment, the method further comprises: decomposing a third active output instruction through a synergistic chip to obtain an active output instruction corresponding to each controlled device; and sending each active output instruction to corresponding controlled equipment through the co-chip.

In a specific implementation, the power distribution circuit decomposes the third active output instruction Pagc plus P1 plus P2 through the co-chip to obtain active output instructions P1, P2, … and Pn corresponding to each controlled device, wherein the sum of P1, P2, … and Pn is equal to Pagc plus P1 plus P2.

According to the technical scheme, the third active output instruction is decomposed through the synergistic chip, and the active output instruction corresponding to each controlled device is obtained; transmitting each active output instruction to corresponding controlled equipment through a co-chip; therefore, active power can be accurately distributed to each controlled device, and accurate power control is facilitated.

In another embodiment, the method further comprises: collecting current and voltage analog signals of each controlled device and the grid-connected point in the new energy station through an FPGA chip to obtain a sampling result; and inputting the sampling result into a fast Fourier transform calculation program built in the FPGA chip through the FPGA chip to obtain a calculation result data packet.

The fast fourier transform calculation program may be a program for calculating the collected current-voltage analog signal to obtain current-voltage effective value data and frequency data of a current-voltage waveform.

In the specific implementation, a power distribution circuit acquires current and voltage analog signals of each controlled device and a grid connection point in a new energy station through an FPGA chip to obtain a sampling result, and the power distribution circuit inputs the sampling result into a fast Fourier transform calculation program built in the FPGA chip through the FPGA chip to obtain a calculation result data packet.

In practical application, the sampling frequency of the FPGA chip is 10kHz, and each 50ms FPGA chip sends a calculation result data packet to other upper functional chips through the Mailbox, and each calculation result data packet contains 500 sampling calculation results. The data packet sampling result acquired by the FPGA chip is required to be input into a built-in fast Fourier transform calculation program, 500 times of acquisition signals are filtered to obtain 1 group of data of current voltage effective values, and in addition, the data packet sampling result acquired by the FPGA chip is input into a built-in frequency calculation program to obtain 1 group of frequency data of current voltage waveforms.

According to the technical scheme, current and voltage analog signals of all controlled devices and the grid-connected points in the new energy station are collected through an FPGA chip, and a sampling result is obtained; inputting the sampling result into a fast Fourier transform calculation program built in the FPGA chip through the FPGA chip to obtain a calculation result data packet; therefore, the initial data obtained by sampling can be preprocessed and calculated in advance, so that the calculation programs in the main chip and the auxiliary chip can utilize the calculated data to further process the data, the data processing efficiency is improved, and the rapid power control is facilitated.

In another embodiment, the method further comprises: inputting the calculation result data packet into an automatic voltage control calculation program loaded by the main chip through the main chip to obtain a reactive power output total instruction; the reactive power output total instruction is used for indicating reactive power distribution to each controlled device in the new energy station; decomposing the total reactive output command through the main chip to obtain a reactive output command corresponding to each controlled device; and sending each reactive power output instruction to corresponding controlled equipment through the main chip.

The automatic voltage control calculation program can be an AVC power control instruction, in practical application, the AVC power control instruction can control the whole-field reactive power installation and scheduling target instruction to process according to real-time reactive power output of an electric field, and the scheduling side target voltage/target reactive power forwarded by a comprehensive self-system is combined, so that the generating potential of reactive power supplies in the electric field is considered, and the whole-field reactive power supply installation and scheduling target instruction is controlled to process, thereby obtaining the total whole-field reactive power processing instruction Qagc of the wind power field (photovoltaic power station).

The reactive power output total command may be the full-field reactive power processing total command Qagc.

The reactive power output command can be a reactive power output command corresponding to each controlled device after the total reactive power output command is decomposed.

In a specific implementation, a power distribution circuit inputs a calculation result data packet to an AVC power control calculation program loaded on a main chip through the main chip to obtain a reactive output total instruction Qagc, the power distribution circuit decomposes the reactive output total instruction Qagc through the main chip to obtain reactive output instructions Q1, Q2, … and Qn corresponding to each controlled device, and the power distribution circuit sends the reactive output instructions Q1, Q2, … and Qn to the controlled devices 1, 2, … and n through the main chip respectively.

In practical application, the main chip receives 1 group of data of current voltage effective values and 1 group of frequency data of current voltage waveforms sent by the FPGA every 50ms, so as to enter an AVC power control calculation program to calculate a reactive output total instruction Qavc. The main chip also decomposes the total reactive output command Qavc into reactive processing commands Qi of each controlled device i, and then transmits the reactive processing commands Qi to the communication board card through the data bus, and the reactive processing commands Qi are sent to each controlled device through the RJ45 port. The real-time performance requirement of the AVC power control calculation program on the main chip is not high, and a time axis is not required to be unified with the co-chip during operation.

The AVC power control calculation is based on real-time reactive power output of an electric field, combines dispatching side target voltage/target reactive power forwarded by a comprehensive self-system, considers the generating potential of reactive power sources in the electric field, and controls the whole-field reactive power source to install and dispatch target instructions for processing, so as to obtain a whole-field reactive processing total instruction Qagc of the wind power field (photovoltaic power station).

According to the technical scheme, the main chip inputs the calculation result data packet into an automatic voltage control calculation program loaded by the main chip to obtain a reactive output total instruction; the reactive power output total instruction is used for indicating reactive power distribution to each controlled device in the new energy station; decomposing the total reactive output command through the main chip to obtain a reactive output command corresponding to each controlled device; transmitting each reactive output instruction to corresponding controlled equipment through a main chip; therefore, reactive power can be accurately distributed to each controlled device, and accurate power control is facilitated.

In another embodiment, the method further comprises: acquiring primary frequency modulation calculation parameters and inertia control calculation parameters through a main chip, and sending the primary frequency modulation calculation parameters and the inertia control calculation parameters to a co-chip; and caching the primary frequency modulation calculation parameters and the inertia control calculation parameters through the co-chip.

In the specific implementation, the power distribution circuit acquires the primary frequency modulation calculation parameter and the inertia control calculation parameter through the main chip, and sends the primary frequency modulation calculation parameter and the inertia control calculation parameter to the auxiliary chip, and the power distribution circuit loads the primary frequency modulation calculation parameter and the inertia control calculation parameter through the auxiliary chip cache.

According to the technical scheme, primary frequency modulation calculation parameters and inertia control calculation parameters are obtained through a main chip, and the primary frequency modulation calculation parameters and the inertia control calculation parameters are sent to a co-chip; caching primary frequency modulation calculation parameters and inertia control calculation parameters through a co-chip; therefore, the manually configured calculation parameters can be received, and the corresponding calculation parameters are cached, so that the efficient real-time calculation of the co-chip is facilitated.

In another embodiment, as shown in fig. 5, a method for quickly controlling power of a new energy station based on a heterogeneous multi-core hardware platform is provided, and the method is applied to the power distribution circuit 102 in fig. 1 for illustration, and includes the following steps:

step S502, sending a calculation result data packet to a main chip and a co-chip through an FPGA chip; the data in the calculation result data packet is obtained by calculating the acquired current-voltage analog signals through the FPGA chip.

Step S504, the main chip inputs the calculation result data packet into an automatic power generation control calculation program loaded by the main chip to obtain a first active output instruction, and sends the first active output instruction to the auxiliary chip.

Step S506, determining whether the current frequency is in the frequency adjustment dead zone range according to the real-time active power of the new energy station and the grid frequency deviation amount information of the new energy station by a primary frequency modulation calculation program; the real-time active power and the grid frequency deviation amount information are determined according to the calculation result data packet.

Step S508, determining a primary frequency modulation additional power instruction according to a preset primary frequency modulation calculation parameter by a primary frequency modulation calculation program under the condition that the current frequency exceeds the frequency adjustment dead zone range.

Step S510, determining a second active output command according to the first active output command and the primary modulation additional power command by a primary modulation calculation program.

Step S512, inputting the calculation result data packet, the second active output instruction and the preset inertia control calculation parameter into an inertia control calculation program loaded by the co-chip through the co-chip to obtain a third active output instruction; the third active power output instruction is used for indicating active power distribution to each controlled device in the new energy station.

It should be noted that, the specific limitation of the above steps may be referred to the specific limitation of a method for quickly controlling power of a new energy station based on a multi-core heterogeneous hardware platform.

It should be understood that, although the steps in the flowcharts related to the embodiments described above are sequentially shown as indicated by arrows, these steps are not necessarily sequentially performed in the order indicated by the arrows. The steps are not strictly limited to the order of execution unless explicitly recited herein, and the steps may be executed in other orders. Moreover, at least some of the steps in the flowcharts described in the above embodiments may include a plurality of steps or a plurality of stages, which are not necessarily performed at the same time, but may be performed at different times, and the order of the steps or stages is not necessarily performed sequentially, but may be performed alternately or alternately with at least some of the other steps or stages.

Based on the same inventive concept, the embodiment of the application also provides a new energy station power rapid control device based on the multi-core heterogeneous hardware platform, which is used for realizing the new energy station power rapid control method based on the multi-core heterogeneous hardware platform. The implementation scheme of the device for solving the problem is similar to the implementation scheme recorded in the method, so the specific limitation in the embodiment of the device for quickly controlling the power of the new energy station based on the multi-core heterogeneous hardware platform provided below can be referred to the limitation of the method for quickly controlling the power of the new energy station based on the multi-core heterogeneous hardware platform hereinabove, and the description is omitted here.

In one embodiment, as shown in fig. 6, a new energy station power fast control device based on a multi-core heterogeneous hardware platform is provided, including:

the sending module 602 is specifically configured to send, through the FPGA chip, a calculation result packet to the master chip and the co-chip; the data in the calculation result data packet is obtained by calculating the acquired current and voltage analog signals through the FPGA chip;

the first input module 604 is specifically configured to input, through the main chip, a calculation result packet to an automatic power generation control calculation program loaded on the main chip, obtain a first active output instruction, and send the first active output instruction to the co-chip;

The second input module 606 is specifically configured to input, through the co-chip, the calculation result data packet, the first active output instruction, and a preset primary frequency modulation calculation parameter to a primary frequency modulation calculation program loaded by the co-chip, to obtain a second active output instruction;

the third input module 608 is specifically configured to input, through the co-chip, the calculation result data packet, the second active output instruction, and a preset inertia control calculation parameter to an inertia control calculation program loaded by the co-chip, to obtain a third active output instruction; the third active power output instruction is used for indicating active power distribution to each controlled device in the new energy station.

In one embodiment, the second input module 606 is specifically configured to determine, according to the real-time active power of the new energy station and the grid frequency deviation amount information of the new energy station, whether the current frequency is within the frequency adjustment dead zone range through a primary frequency modulation calculation program; the real-time active power and the power grid frequency deviation amount information are determined according to the calculation result data packet; under the condition that the current frequency exceeds the frequency adjustment dead zone range, determining a primary frequency modulation additional power instruction according to a preset primary frequency modulation calculation parameter by a primary frequency modulation calculation program; and determining a second active output command according to the first active output command and the primary frequency modulation additional power command through a primary frequency modulation calculation program.

In one embodiment, the third input module 608 is specifically configured to determine, according to the real-time active power of the new energy station and the information of the frequency change rate of the power grid of the new energy station, by using an inertia control calculation program, whether the current frequency change rate is within the frequency change rate adjustment dead zone range; the power grid frequency change rate information is determined according to the calculation result data packet; under the condition that the current frequency change rate exceeds the frequency change rate regulation dead zone range, determining an inertia control additional power instruction according to preset inertia control calculation parameters by an inertia control calculation program; and determining a third active output command according to the second active output command and the inertia control additional power command through an inertia control calculation program.

In one embodiment, the apparatus further comprises: the decomposition module is specifically used for decomposing the third active output instruction by the co-chip to obtain an active output instruction corresponding to each controlled device; and sending each active output instruction to corresponding controlled equipment through the co-chip.

In one embodiment, the apparatus further comprises: the acquisition module is specifically used for acquiring current and voltage analog signals of each controlled device and the grid-connected point in the new energy station through the FPGA chip to obtain a sampling result; and inputting the sampling result into a fast Fourier transform calculation program built in an FPGA chip through the FPGA to obtain a calculation result data packet.

In one embodiment, the apparatus further comprises: the fourth input module is specifically used for inputting the calculation result data packet into an automatic voltage control calculation program loaded by the main chip through the main chip to obtain a reactive output total instruction; the reactive power output total instruction is used for indicating reactive power distribution to each controlled device in the new energy station; decomposing the total reactive output command through the main chip to obtain a reactive output command corresponding to each controlled device; and sending each reactive power output instruction to corresponding controlled equipment through the main chip.

In one embodiment, the apparatus further comprises: the acquisition module is specifically used for acquiring the primary frequency modulation calculation parameter and the inertia control calculation parameter through the main chip and sending the primary frequency modulation calculation parameter and the inertia control calculation parameter to the auxiliary chip; and caching the primary frequency modulation calculation parameters and the inertia control calculation parameters through the co-chip.

All or part of the modules in the novel energy station power rapid control device based on the multi-core heterogeneous hardware platform can be realized by software, hardware and a combination thereof. The above modules may be embedded in hardware or may be independent of a processor in the computer device, or may be stored in software in a memory in the computer device, so that the processor may call and execute operations corresponding to the above modules.

In one embodiment, a computer device is provided, which may be a server, the internal structure of which may be as shown in fig. 7. The computer device includes a processor, a memory, and a network interface connected by a system bus. Wherein the processor of the computer device is configured to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system, computer programs, and a database. The internal memory provides an environment for the operation of the operating system and computer programs in the non-volatile storage media. The database of the computer equipment is used for storing the new energy station power quick control data based on the multi-core heterogeneous hardware platform. The network interface of the computer device is used for communicating with an external terminal through a network connection. The computer program is executed by a processor to realize a new energy station power rapid control method based on a multi-core heterogeneous hardware platform.

It will be appreciated by those skilled in the art that the structure shown in FIG. 7 is merely a block diagram of some of the structures associated with the present inventive arrangements and is not limiting of the computer device to which the present inventive arrangements may be applied, and that a particular computer device may include more or fewer components than shown, or may combine some of the components, or have a different arrangement of components.

In one embodiment, a computer device is provided, including a memory and a processor, where the memory stores a computer program, and the computer program when executed by the processor causes the processor to perform the steps of the method for quickly controlling power of a new energy station based on a multi-core heterogeneous hardware platform. The steps of the method for quickly controlling the power of the new energy station based on the multi-core heterogeneous hardware platform may be the steps of the method for quickly controlling the power of the new energy station based on the multi-core heterogeneous hardware platform in the above embodiments.

In one embodiment, a computer readable storage medium is provided, in which a computer program is stored, where the computer program when executed by a processor causes the processor to perform the steps of a new energy station power fast control method based on a multi-core heterogeneous hardware platform. The steps of the method for quickly controlling the power of the new energy station based on the multi-core heterogeneous hardware platform may be the steps of the method for quickly controlling the power of the new energy station based on the multi-core heterogeneous hardware platform in the above embodiments.

In one embodiment, a computer program product is provided, including a computer program, where the computer program when executed by a processor causes the processor to perform the steps of a new energy station power fast control method based on a multi-core heterogeneous hardware platform. The steps of the method for quickly controlling the power of the new energy station based on the multi-core heterogeneous hardware platform may be the steps of the method for quickly controlling the power of the new energy station based on the multi-core heterogeneous hardware platform in the above embodiments.

The user information (including but not limited to user equipment information, user personal information, etc.) and the data (including but not limited to data for analysis, stored data, presented data, etc.) related to the present application are information and data authorized by the user or sufficiently authorized by each party.

Those skilled in the art will appreciate that implementing all or part of the above described methods may be accomplished by way of a computer program stored on a non-transitory computer readable storage medium, which when executed, may comprise the steps of the embodiments of the methods described above. Any reference to memory, database, or other medium used in embodiments provided herein may include at least one of non-volatile and volatile memory. The nonvolatile Memory may include Read-Only Memory (ROM), magnetic tape, floppy disk, flash Memory, optical Memory, high density embedded nonvolatile Memory, resistive random access Memory (ReRAM), magnetic random access Memory (Magnetoresistive Random Access Memory, MRAM), ferroelectric Memory (Ferroelectric Random Access Memory, FRAM), phase change Memory (Phase Change Memory, PCM), graphene Memory, and the like. Volatile memory can include random access memory (Random Access Memory, RAM) or external cache memory, and the like. By way of illustration, and not limitation, RAM can be in the form of a variety of forms, such as Static Random access memory (Static Random access memory AccessMemory, SRAM) or dynamic Random access memory (Dynamic Random Access Memory, DRAM), and the like. The databases referred to in the embodiments provided herein may include at least one of a relational database and a non-relational database. The non-relational database may include, but is not limited to, a blockchain-based distributed database, and the like. The processor referred to in the embodiments provided in the present application may be a general-purpose processor, a central processing unit, a graphics processor, a digital signal processor, a programmable logic unit, a data processing logic unit based on quantum computing, or the like, but is not limited thereto.

The technical features of the above embodiments may be arbitrarily combined, and all possible combinations of the technical features in the above embodiments are not described for brevity of description, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.

The foregoing examples illustrate only a few embodiments of the application and are described in detail herein without thereby limiting the scope of the application. It should be noted that it will be apparent to those skilled in the art that several variations and modifications can be made without departing from the spirit of the application, which are all within the scope of the application. Accordingly, the scope of the application should be assessed as that of the appended claims.

Claims

1. The method is characterized by being applied to a multi-core heterogeneous hardware platform, wherein the multi-core heterogeneous hardware platform comprises an interface board card, a data bus and a CPU board card; the interface board card comprises an on-off board card, a network communication board card, other expansion board cards and an alternating current-direct current sampling board card; the CPU board card is used as a power distribution circuit; the power distribution computing circuit comprises a main chip, a co-chip and an FPGA chip which are communicated through a Mailbox; the main chip is an ARM Cortex-A chip; the co-chip is an ARM Cortex-M chip; the method comprises the following steps:

Sending a calculation result data packet to the main chip and the auxiliary chip through the FPGA chip; the data in the calculation result data packet is obtained by calculating the acquired current and voltage analog signals by the FPGA chip; the sampling frequency of the FPGA chip is 10kHz; sending the calculation result data packet to the main chip and the auxiliary chip once every 50ms through a Mailbox through the FPGA chip; the calculation result data packet comprises 500 sampling calculation results; inputting the acquired sampling result into a fast Fourier transform calculation program through the FPGA chip to obtain 1 group of data of current and voltage effective values; inputting the acquired sampling result into a frequency calculation program through the FPGA chip to obtain frequency data of 1 group of current and voltage waveforms; the main chip is used for running an automatic power generation control calculation program; the co-chip is used for running a primary frequency modulation calculation program and an inertia control calculation program; the running real-time requirement of the automatic power generation control calculation program is lower than that of the primary frequency modulation calculation program and the inertia control calculation program;

inputting the calculation result data packet to the automatic power generation control calculation program loaded by the main chip through the main chip to obtain a first active output instruction, and sending the first active output instruction to the auxiliary chip;

Inputting the calculation result data packet, the first active output instruction and preset primary frequency modulation calculation parameters to the primary frequency modulation calculation program loaded by the auxiliary chip through the auxiliary chip to obtain a second active output instruction;

inputting the calculation result data packet, the second active output instruction and preset inertia control calculation parameters to the inertia control calculation program loaded by the auxiliary chip through the auxiliary chip to obtain a third active output instruction; the inertia control calculation program outputs the three active output instructions according to the data of the 1-group current voltage effective values and the frequency data of the 1-group current voltage waveforms, the second active output instruction and the preset inertia control calculation parameters, which are sent by the FPGA chip through a Mailbox every 50 ms; the inertia control calculation program takes 100ms as a time window, and calculates the inertia control additional power instruction according to the data packet of two adjacent times sent by the FPGA chip and the frequency difference value of two times within 100 ms; after the calculation period is finished, shifting the time window to the right by 50ms, returning to the data packet of the two adjacent times sent by the FPGA chip, and calculating the inertia control additional power instruction by using the two frequency difference values within 100 ms; the third active power output instruction is used for indicating active power distribution to each controlled device in the new energy station; the third active power output instruction is the sum of an inertia control additional power instruction determined by the inertia control calculation program, a primary frequency modulation additional power instruction determined by the primary frequency modulation calculation program and an instruction of the first active power output instruction; and locking the inertia control additional power command and the primary frequency modulation additional power command when the sum of the inertia control additional power command and the primary frequency modulation additional power command is opposite to the control direction of the first active output command.

2. The method of claim 1, wherein the inputting, by the co-chip, the calculation result data packet, the first active output instruction, and a preset chirp calculation parameter to the chirp calculation program loaded by the co-chip, to obtain a second active output instruction includes:

determining whether the current frequency is in a frequency regulation dead zone range or not according to the real-time active power of the new energy station and the power grid frequency deviation amount information of the new energy station through the primary frequency modulation calculation program; the real-time active power and the grid frequency deviation amount information are determined according to the calculation result data packet;

determining a primary frequency modulation additional power instruction according to the preset primary frequency modulation calculation parameter by the primary frequency modulation calculation program under the condition that the current frequency exceeds the frequency adjustment dead zone range;

and determining the second active output command according to the first active output command and the primary frequency modulation additional power command through the primary frequency modulation calculation program.

3. The method of claim 2, wherein the inputting, by the co-chip, the calculation result data packet, the second active output instruction, and a preset inertia control calculation parameter to the inertia control calculation program loaded by the co-chip, to obtain a third active output instruction includes:

Determining whether the current frequency change rate is in the frequency change rate regulation dead zone range according to the real-time active power of the new energy station and the power grid frequency change rate information of the new energy station through the inertia control calculation program; the power grid frequency change rate information is determined according to the calculation result data packet;

under the condition that the current frequency change rate exceeds the frequency change rate adjustment dead zone range, determining an inertia control additional power instruction according to the preset inertia control calculation parameter by the inertia control calculation program;

and determining the third active output command according to the second active output command and the inertia control additional power command through the inertia control calculation program.

4. A method according to claim 3, characterized in that the method further comprises:

decomposing the third active output command through the synergistic chip to obtain an active output command corresponding to each controlled device;

and sending each active force instruction to the corresponding controlled equipment through the co-chip.

5. The method according to claim 1, wherein the method further comprises:

Collecting current-voltage analog signals of each controlled device and the grid-connected point in the new energy station through the FPGA chip to obtain a sampling result;

and inputting the sampling result to a fast Fourier transform calculation program built in the FPGA chip through the FPGA to obtain the calculation result data packet.

6. The method according to claim 1, wherein the method further comprises:

inputting the calculation result data packet into an automatic voltage control calculation program loaded by the main chip through the main chip to obtain a reactive output total instruction; the reactive power output total instruction is used for indicating reactive power distribution to each controlled device in the new energy station;

decomposing the reactive power total instruction through the main chip to obtain reactive power instructions corresponding to the controlled devices;

and sending each reactive power output instruction to the corresponding controlled equipment through the main chip.

7. The method according to claim 1, wherein the method further comprises:

acquiring the primary frequency modulation calculation parameter and the inertia control calculation parameter through the main chip, and sending the primary frequency modulation calculation parameter and the inertia control calculation parameter to the co-chip;

8. The new energy station power rapid control device based on the multi-core heterogeneous hardware platform is characterized by being applied to the multi-core heterogeneous hardware platform, wherein the multi-core heterogeneous hardware platform comprises an interface board card, a data bus and a CPU board card; the interface board card comprises an on-off board card, a network communication board card, other expansion board cards and an alternating current-direct current sampling board card; the CPU board card is used as a power distribution circuit; the power distribution computing circuit comprises a main chip, a co-chip and an FPGA chip which are communicated through a Mailbox; the main chip is an ARM Cortex-A chip; the co-chip is an ARM Cortex-M chip; the device comprises:

the sending module is used for sending a calculation result data packet to the main chip and the auxiliary chip through the FPGA chip; the data in the calculation result data packet is obtained by calculating the acquired current and voltage analog signals by the FPGA chip; the sampling frequency of the FPGA chip is 10kHz; sending the calculation result data packet to the main chip and the auxiliary chip once every 50ms through a Mailbox through the FPGA chip; the calculation result data packet comprises 500 sampling calculation results; inputting the acquired sampling result into a fast Fourier transform calculation program through the FPGA chip to obtain 1 group of data of current and voltage effective values; inputting the acquired sampling result into a frequency calculation program through the FPGA chip to obtain frequency data of 1 group of current and voltage waveforms; the main chip is used for running an automatic power generation control calculation program; the co-chip is used for running a primary frequency modulation calculation program and an inertia control calculation program; the running real-time requirement of the automatic power generation control calculation program is lower than that of the primary frequency modulation calculation program and the inertia control calculation program;

The first input module is used for inputting the calculation result data packet into the automatic power generation control calculation program loaded by the main chip through the main chip to obtain a first active output instruction, and sending the first active output instruction to the auxiliary chip;

the second input module is used for inputting the calculation result data packet, the first active output instruction and preset primary frequency modulation calculation parameters to the primary frequency modulation calculation program loaded by the auxiliary chip through the auxiliary chip to obtain a second active output instruction;

the third input module is used for inputting the calculation result data packet, the second active output instruction and preset inertia control calculation parameters to the inertia control calculation program loaded by the auxiliary chip through the auxiliary chip to obtain a third active output instruction; the inertia control calculation program outputs the three active output instructions according to the data of the 1-group current voltage effective values and the frequency data of the 1-group current voltage waveforms, the second active output instruction and the preset inertia control calculation parameters, which are sent by the FPGA chip through a Mailbox every 50 ms; the inertia control calculation program takes 100ms as a time window, and calculates the inertia control additional power instruction according to the data packet of two adjacent times sent by the FPGA chip and the frequency difference value of two times within 100 ms; after the calculation period is finished, shifting the time window to the right by 50ms, returning to the data packet of the two adjacent times sent by the FPGA chip, and calculating the inertia control additional power instruction by using the two frequency difference values within 100 ms; the third active power output instruction is used for indicating active power distribution to each controlled device in the new energy station; the third active power output instruction is the sum of an inertia control additional power instruction determined by the inertia control calculation program, a primary frequency modulation additional power instruction determined by the primary frequency modulation calculation program and an instruction of the first active power output instruction; and locking the inertia control additional power command and the primary frequency modulation additional power command when the sum of the inertia control additional power command and the primary frequency modulation additional power command is opposite to the control direction of the first active output command.

9. The new energy station power rapid control platform based on the multi-core heterogeneous hardware platform is characterized by comprising an interface board card, a data bus and a CPU board card; the interface board card comprises an on-off board card, a network communication board card, other expansion board cards and an alternating current-direct current sampling board card; the CPU board card is used as a power distribution circuit; the power distribution computing circuit comprises a main chip, a co-chip and an FPGA chip which are communicated through a Mailbox; the main chip is an ARM Cortex-A chip; the co-chip is an ARM Cortex-M chip;

the FPGA chip is used for sending a calculation result data packet to the main chip and the assistant chip; the data in the calculation result data packet is obtained by calculating the acquired current and voltage analog signals by the FPGA chip; the sampling frequency of the FPGA chip is 10kHz; sending the calculation result data packet to the main chip and the auxiliary chip once every 50ms through a Mailbox through the FPGA chip; the calculation result data packet comprises 500 sampling calculation results; inputting the acquired sampling result into a fast Fourier transform calculation program through the FPGA chip to obtain 1 group of data of current and voltage effective values; inputting the acquired sampling result into a frequency calculation program through the FPGA chip to obtain frequency data of 1 group of current and voltage waveforms; the main chip is used for running an automatic power generation control calculation program; the co-chip is used for running a primary frequency modulation calculation program and an inertia control calculation program; the running real-time requirement of the automatic power generation control calculation program is lower than that of the primary frequency modulation calculation program and the inertia control calculation program;

The main chip is used for inputting the calculation result data packet into the automatic power generation control calculation program loaded by the main chip to obtain a first active output instruction, and sending the first active output instruction to the auxiliary chip;

the auxiliary chip is used for inputting the calculation result data packet, the first active output instruction and preset primary frequency modulation calculation parameters into the primary frequency modulation calculation program loaded by the auxiliary chip to obtain a second active output instruction; inputting the calculation result data packet, the second active output instruction and preset inertia control calculation parameters into the inertia control calculation program loaded by the co-chip to obtain a third active output instruction; the inertia control calculation program outputs the three active output instructions according to the data of the 1-group current voltage effective values and the frequency data of the 1-group current voltage waveforms, the second active output instruction and the preset inertia control calculation parameters, which are sent by the FPGA chip through a Mailbox every 50 ms; the inertia control calculation program takes 100ms as a time window, and calculates the inertia control additional power instruction according to the data packet of two adjacent times sent by the FPGA chip and the frequency difference value of two times within 100 ms; after the calculation period is finished, shifting the time window to the right by 50ms, returning to the data packet of the two adjacent times sent by the FPGA chip, and calculating the inertia control additional power instruction by using the two frequency difference values within 100 ms; the third active power output instruction is used for indicating active power distribution to each controlled device in the new energy station; the third active power output instruction is the sum of an inertia control additional power instruction determined by the inertia control calculation program, a primary frequency modulation additional power instruction determined by the primary frequency modulation calculation program and an instruction of the first active power output instruction; and locking the inertia control additional power command and the primary frequency modulation additional power command when the sum of the inertia control additional power command and the primary frequency modulation additional power command is opposite to the control direction of the first active output command.

10. A computer readable storage medium, on which a computer program is stored, characterized in that the computer program, when being executed by a processor, implements the steps of the method of any of claims 1 to 7.