CN116365316A

CN116365316A - Cable device for chip test

Info

Publication number: CN116365316A
Application number: CN202310472022.7A
Authority: CN
Inventors: 廉哲; 罗跃浩; 黄建军; 胡海洋
Original assignee: Suzhou Lianxun Instrument Co ltd
Current assignee: Suzhou Lianxun Instrument Co ltd
Priority date: 2023-02-08
Filing date: 2023-02-08
Publication date: 2023-06-30
Also published as: CN115810954B; CN115810954A

Abstract

The invention provides a cable device for chip testing, and belongs to the technical field of chip testing cables. The cable device for chip testing includes: the adapter comprises an input interface and an output interface, wherein the input interface and the output interface respectively comprise corresponding signal wires and shielding layers arranged outside the signal wires, and the input interface is used for receiving electric signals; and the chip test module comprises a first cable and a test probe connected with the first cable, and one end, far away from the test probe, of the first cable is connected with the output interface. The cable device for chip test can effectively prevent leakage current.

Description

Cable device for chip test

The application is CN202310079205.2, and the application date is 2023, 2, 8 and the division application of the name of a low leakage current cable device.

Technical Field

The invention relates to the technical field of chip test cables, in particular to a cable device for chip test.

Background

Along with the increasing requirements of chip testing, the environment in a production workshop is influenced by peripheral equipment, the electromagnetic environment is complex, the influence on low leakage current testing is large, and most of the current methods are that equipment environments are isolated, such as an independent small room is used for shielding electromagnetic influence.

The problem of low leakage current still exists for the cable for chip test, which affects the chip test precision, so how to prevent the low leakage current at the cable is an important problem for meeting the chip test requirement.

Disclosure of Invention

An object of the present invention is to provide a cable device for chip testing, which can effectively prevent leakage current.

It is a further object of the present invention to facilitate wiring.

It is a further object of the present invention to prevent leakage current in all directions.

In particular, the present invention provides a cable apparatus for chip testing, comprising:

the adapter comprises an input interface and an output interface, wherein the input interface and the output interface respectively comprise corresponding signal wires and shielding layers arranged outside the signal wires, and the input interface is used for receiving electric signals; and

the chip testing module comprises a first cable and a testing probe connected with the first cable, and one end of the first cable, which is far away from the testing probe, is connected with the output interface;

the input interface comprises a test interface and a compensation monitoring interface;

the test interface comprises a test signal input wire, a first shielding layer and a first grounding layer, wherein the first shielding layer is arranged outside the test signal input wire in a wrapping mode, and the first grounding layer is arranged outside the first shielding layer in a wrapping mode;

the compensation monitoring interface comprises a feedback signal input wire, a second shielding layer and a second grounding layer, wherein the second shielding layer is arranged outside the feedback signal input wire in a wrapping mode;

the output interface includes:

the test signal output wire is connected with the test signal input wire;

the feedback signal output layer is wrapped outside the test signal output wire and connected with the feedback signal input wire; and

and the third shielding layer is wrapped outside the feedback signal output layer and is connected with the first shielding layer and the second shielding layer.

Optionally, the input interface and the output interface are connected through a circuit board.

Optionally, the input interface and the output interface are respectively disposed at two opposite ends of the circuit board.

Optionally, the cable device for chip testing further comprises a first protection shell, which comprises a first shielding box for fixing the adapter, wherein a first mounting hole and a second mounting hole for penetrating the input interface and the output interface are respectively arranged at the first shielding box.

Optionally, the first protection shell further comprises an insulating isolation plate, the isolation plate is fixed on the connection side of the first shielding box and the output interface, and a third mounting hole for penetrating through the output interface is formed in the isolation plate.

Optionally, the number of the adapters and the number of the chip test modules are multiple, and the multiple adapters are all arranged in the first shielding box;

the first shielding box is internally provided with a plurality of shielding clapboards which are used for separating a plurality of chambers, and each chamber is used for placing one adapter.

Optionally, the first shielding box comprises a cover plate and a shielding cover with an opening, and the cover plate covers the opening of the shielding cover to form a closed space.

Optionally, the chip test module further includes a second protective case, where the second protective case includes:

a second shielding box for fixing the first cable and the test probe; and

and the low-leakage protective cover is arranged at the outer surface of the second shielding box and used for preventing leakage.

According to one embodiment of the present invention, by providing shielding layers outside the signal conductors of both the input interface and the output interface of the adapter, it is possible to prevent the connector from generating leakage currents at the input interface and the output interface.

According to one embodiment of the present invention, by arranging the connection of the respective wires inside the adapter, it is possible to smoothly transmit and receive signals while maximally preventing occurrence of leakage current.

According to one embodiment of the present invention, by providing a plurality of shielding partitions in the first shielding case, the respective adapters can be effectively isolated from each other, preventing mutual electromagnetic interference.

According to the embodiment of the invention, the leakage current at the chip test module can be further prevented by arranging the low-leakage protection cover.

According to the embodiment of the invention, the shielding layers are arranged at the positions of the wires inside the adapter, the first shielding box and the isolation plate are arranged outside the adapter, the second shielding box and the low-leakage protection cover are arranged at the position of the chip test module, so that shielding and isolation can be carried out at all nodes of the cable device until the test probe end, and leakage current can be prevented in all directions.

The above, as well as additional objectives, advantages, and features of the present invention will become apparent to those skilled in the art from the following detailed description of a specific embodiment of the present invention when read in conjunction with the accompanying drawings.

Drawings

Some specific embodiments of the invention will be described in detail hereinafter by way of example and not by way of limitation with reference to the accompanying drawings. The same reference numbers will be used throughout the drawings to refer to the same or like parts or portions. It will be appreciated by those skilled in the art that the drawings are not necessarily drawn to scale. In the accompanying drawings:

FIG. 1 is a schematic diagram of a cable assembly for chip testing according to one embodiment of the invention;

FIG. 2 is a schematic diagram of a cable assembly for chip testing according to one embodiment of the invention;

FIG. 3 is a schematic diagram of a cable assembly for chip testing according to another embodiment of the present invention;

FIG. 4 is an exploded schematic view of a first protective housing of a cable plant for chip testing, according to one embodiment of the invention;

FIG. 5 is a cross-sectional view of an adapter of a cable arrangement for chip testing according to one embodiment of the invention;

FIG. 6 is a schematic diagram of a chip test module of a cable device for chip testing according to one embodiment of the invention;

fig. 7 is a leakage current test data diagram of a cable apparatus for chip testing according to an embodiment of the present invention.

Reference numerals:

100-cable assembly, 10-adapter, 11-input interface, 111-test interface, 101-test signal input wire, 102-first shield layer, 103-first ground layer, 112-compensation monitor interface, 104-feedback signal input wire, 105-second shield layer, 106-second ground layer, 12-output interface, 121-test signal output wire, 122-feedback signal output layer, 123-third shield layer, 13-wiring board, 20-chip test module, 21-first cable, 22-test probe, 23-second protective shell, 231-second shield box, 232-low leakage protective cover, 30-first protective cover, 31-first shield box, 311-second mounting hole, 312-shield spacer, 301-cover plate, 302-shield cover, 32-spacer plate, 321-third mounting hole, 40-second cable.

Detailed Description

Fig. 1 is a schematic structural view of a cable apparatus 100 for chip testing according to an embodiment of the present invention. Fig. 2 is a schematic diagram of a cable device 100 for chip testing according to one embodiment of the invention. As shown in fig. 1, in one embodiment, a cable apparatus 100 for chip testing includes an adapter 10 and a chip testing module 20. The adapter 10 includes an input interface 11 and an output interface 12, signal conductors corresponding to the input interface 11 and the output interface 12, and shielding layers (see 102, 104, and 123 in fig. 2) provided outside the signal conductors. As shown in fig. 1, the input interface 11 and the output interface 12 further include a first metal sleeve and a second metal sleeve provided at the outermost layers, the interiors of which are used for providing wires. The input interface 11 is configured to receive an electrical signal, for example, a second cable 40 is connected to the input interface 11 in fig. 1, and the other end of the second cable 40 may be connected to the source meter, so as to receive an electrical signal sent by the source meter, which may be a voltage signal. The test interface 111 the chip test module 20 comprises a first cable 21 and a test probe 22 connected to the first cable 21, the end of the first cable 21 remote from the test probe 22 being connected to the output interface 12.

In this embodiment, by providing shielding layers outside the signal wires of the input interface 11 and the output interface 12 of the adapter 10, leakage current generated at the input interface 11 and the output interface 12 by the connector can be prevented.

In one embodiment, as shown in FIG. 1, input interface 11 includes a test interface 111 and a compensation monitor interface 112. As shown in fig. 2, the test interface 111 includes a test signal input wire 101, a first shielding layer 102 disposed outside the test signal input wire 101, and a first ground layer 103 disposed outside the first shielding layer 102. The compensation monitor interface 112 includes a feedback signal input wire 104, a second shielding layer 105 disposed outside the feedback signal input wire 104, and a second ground layer 106 disposed outside the second shielding layer 105. The first ground layer 103 and the second ground layer 106 are both grounded. The output interface 12 includes a test signal output wire 121, a feedback signal output layer 122, and a third shielding layer 123. Test signal output conductor 121 is connected to test signal input conductor 101. The feedback signal output layer 122 is disposed outside the test signal output wire 121 and connected to the feedback signal input wire 104. The third shielding layer 123 is disposed outside the feedback signal output layer 122, and the third shielding layer 123 is connected to both the first shielding layer 102 and the second shielding layer 105.

Correspondingly, three wires are also arranged in the first cable 21 and are respectively connected with the test signal output wire 121, the feedback signal output layer 122 and the third shielding layer 123, one end of the three wires in the first cable 21, which is far away from the output interface 12 of the adapter 10, is respectively provided with a test probe 22, a compensation monitoring probe and a shielding probe which are connected with the three wires, and the three probes can be guided by the probe card and then are connected with the test chip so as to test the test chip.

Of course, insulating layers are respectively disposed between the test signal input wire 101, the first shielding layer 102 and the first ground layer 103, insulating layers are also disposed between the feedback signal input wire 104, the second shielding layer 105 and the second ground layer 106, and insulating layers are also disposed between the test signal output wire 121, the feedback signal output layer 122 and the third shielding layer 123.

When testing is performed, the source meter may be connected to the test interface 111 and the compensation monitor interface 112 through two second cables 40, where the source meter provides an input test electrical signal for the test interface 111, and is further configured to receive a feedback electrical signal fed back from the compensation monitor interface 112. When the chip test is performed, the second cable 40 is connected with the source meter, the test probe 22 of the chip test module 20 is connected with the chip to be tested, one end of the chip to be tested far away from the chip test module 20 is grounded to form a loop, the test electric signal can be corrected by the feedback electric signal, the test electric signal required by the chip to be tested is assumed to be 5V, the feedback electric signal received by the source meter is 4.5V, and the source meter can be controlled to give the test electric signal of 5.5V at the moment.

According to the embodiment, through the connection of all wires inside the arrangement adapter 10, the outside of the test signal input wire 101 of the test interface 111 and the feedback signal input wire 104 of the compensation monitoring interface 112 are sequentially provided with the shielding layer and the grounding layer, the wires at the connection part of the input interface 11 and the circuit board of the adapter 10 can be protected from being interfered, meanwhile, the outermost layer at the output interface 12 is set to be the third shielding layer 123, and the wires at the output interface 12 and the chip test module 20 can be protected from being interfered, so that the adapter 10 comprising the test interface 111 and the compensation monitoring interface 112 on the input interface 11 is subjected to comprehensive anti-electromagnetic interference protection, and leakage current can be prevented to the greatest extent while signals can be successfully transmitted and received.

Further, by setting the adaptor 10 and the compensation monitoring interface 112 and setting the circuits related to the compensation monitoring interface 112, the cable device 100 can have a feedback correction function of the electrical signal, so that an accurate test electrical signal can be obtained when the test is performed, and the accuracy of the chip test is ensured.

As shown in fig. 1, in one embodiment, the input interface 11 and the output interface 12 are connected by a circuit board 13 (PCB).

In a further embodiment, the input interface 11 and the output interface 12 are respectively disposed at opposite ends of the circuit board 13.

The input interface 11 and the output interface 12 are respectively arranged at two opposite ends of the circuit board 13, so that subsequent wiring can be facilitated.

Fig. 3 is a schematic structural diagram of a cable apparatus 100 for chip testing according to another embodiment of the present invention. Fig. 4 is an exploded schematic view of the first protective case 30 of the cable apparatus 100 for chip test according to one embodiment of the present invention. As shown in fig. 3, in one embodiment, the cable apparatus 100 for chip testing further includes a first protective case 30 including a first shielding case 31 for fixing the adaptor 10, and first and second mounting holes (not shown) and 311 (see fig. 4) for passing through the input and

output interfaces

11 and 12, respectively, are provided at the first shielding case 31. For example, in one embodiment, as shown in fig. 4, the first shielding box 31 includes a cover plate 301 and a shielding case 302 with an opening, where the cover plate 301 covers the opening of the shielding case 302 to form a closed space. The first shielding case 31 may be made of a metal material, and functions as a shield.

As shown in fig. 3, in a further embodiment, the first protection shell 30 further includes an insulating isolation plate 32, fixed to the connection side of the first shielding case 31 and the output port 12, and a third mounting hole 321 for passing through the output port 12 is provided on the isolation plate 32.

In the present embodiment, the output interfaces 12 of the respective adapters 10 can be isolated from each other by providing the isolation plate 32 on the connection side of the first shield case 31 and the output interface 12, thereby further preventing leakage current.

Fig. 5 is a cross-sectional view of the adapter 10 of the cable assembly 100 for chip testing according to one embodiment of the invention. As shown in fig. 3, in one embodiment, the number of adapters 10 and chip test modules 20 is plural, and plural adapters 10 are disposed in the first shielding box 31. As shown in fig. 5, as well as referring to fig. 4, a plurality of shielding partitions 312 are provided in the first shielding case 31 to partition a plurality of chambers each for accommodating one adapter 10.

The present embodiment can effectively isolate the respective adapters 10 from each other by providing the plurality of shielding separators 312 in the first shielding case 31.

Fig. 6 is a schematic structural view of the chip test module 20 of the cable apparatus 100 for chip test according to one embodiment of the present invention. In one embodiment, as shown in fig. 6, the chip test module 20 further includes a second protective case 23, and the second protective case 23 includes a second shielding case 231 and a low leakage protection cover 232. The second shield case 231 is used to fix the first cable 21 and the test probe 22. A low leakage protection cover 232 is provided at an outer surface of the second shield case 231 for preventing leakage.

The present embodiment can further prevent leakage current at the chip test module 20 by providing a low leakage protection cover.

In combination with the above embodiments, in this embodiment, by providing a shielding layer at each wire inside the adapter 10, and further providing the first shielding box 31 and the isolation board 32 outside the adapter 10, and providing the second shielding box 231 and the low leakage protection cover 232 at the chip test module 20, shielding isolation can be performed at each node of the cable device 100 up to the test probe 22 end, and leakage current can be prevented in all directions.

Fig. 7 is a diagram of leakage current test data of a cable apparatus 100 for chip test according to an embodiment of the present invention, the abscissa in fig. 7 is a measurement time, the ordinate is leakage current, and the unit is pA (1 pa=10 ^-12 A) Channel 0n represents the maximum leakage current on the line formed by the nth connected adapter 10 and chip test module 20. As shown in fig. 7, in one embodiment, the cable device 100 includes 6 switchesThe individual nodes of the cable assembly 100 are provided with all the shielding isolation measures of the above-described embodiments, with the 10 and 6 chip test modules 20. The cable device 100 is tested for leakage current, and the input interface 11 of the cable device 100 is connected with test voltages of 5V, 10V, 15V and 20V, and the typical value of the measured leakage current is not more than 2pA, whereas the leakage current of the cable device without the shielding and isolation measures in the above embodiment in the prior art is generally greater than 50pA. Therefore, the cable device 100 of the present embodiment can significantly reduce leakage current.

By now it should be appreciated by those skilled in the art that while a number of exemplary embodiments of the invention have been shown and described herein in detail, many other variations or modifications of the invention consistent with the principles of the invention may be directly ascertained or inferred from the present disclosure without departing from the spirit and scope of the invention. Accordingly, the scope of the present invention should be understood and deemed to cover all such other variations or modifications.

Claims

1. A cable apparatus for chip testing, comprising:

the adapter comprises an input interface and an output interface, wherein the input interface and the output interface respectively comprise corresponding signal wires and shielding layers arranged outside the signal wires, the input interface is used for receiving electric signals, the input interface and the output interface also comprise a first metal sleeve and a second metal sleeve which are arranged on the outermost layer, and the interiors of the first metal sleeve and the second metal sleeve are used for arranging the wires; and

the output interface includes:

the test signal output wire is connected with the test signal input wire;

the third shielding layer is wrapped outside the feedback signal output layer and is connected with the first shielding layer and the second shielding layer;

the input interface is connected with a second cable, and the other end of the second cable is connected with a source meter;

and three wires are arranged in the first cable and are respectively connected with the test signal output wire, the feedback signal output layer and the third shielding layer.

2. The cable arrangement of claim 1, wherein,

the input interface is connected with the output interface through a circuit board.

3. The cable arrangement of claim 2, wherein,

the input interface and the output interface are respectively arranged at two opposite ends of the circuit board.

4. A cable arrangement according to any one of claims 1-3, further comprising a first protective housing comprising a first shielding cage for securing the adapter, the first shielding cage being provided with a first mounting hole and a second mounting hole for passing through the input interface and the output interface, respectively.

5. The cable apparatus of claim 4, wherein the first protective case further comprises an insulating partition plate fixed to a connection side of the first shield case and the output port, and the partition plate is provided with a third mounting hole for passing through the output port.

6. The cable arrangement of claim 5, wherein,

the number of the adapters and the number of the chip test modules are multiple, and the multiple adapters are arranged in the first shielding box;

7. The cable arrangement of claim 4, wherein,

the first shielding box comprises a cover plate and a shielding cover with an opening, and the cover plate covers the opening of the shielding cover to form a closed space.

8. A cable arrangement according to any of claims 1-3, wherein the chip test module further comprises a second protective casing comprising:

a second shielding box for fixing the first cable and the test probe; and