CN116360234A - Timing circuit, control method and timing equipment - Google Patents
Timing circuit, control method and timing equipment Download PDFInfo
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Abstract
The application provides a timing circuit, a control method and timing equipment, wherein the timing circuit comprises a long-term evolution receiving module and a time conversion module; the long-term evolution receiving module is electrically connected with the time conversion module; the long-term evolution receiving module is configured to receive standard time sent by the base station and output the standard time according to the time request signal; the time conversion module is configured to generate a time request signal and convert the standard time into greenwich mean time. According to the timing circuit, the standard time sent by the base station is received through the long-term evolution receiving module, the standard time is converted into Greenwich standard time through the time conversion module so as to be used for timing instrument correction, the whole circuit does not need to lead an antenna outdoors, a receiving signal is not influenced by time, place, weather and the like, the receiving speed is high, the receiving time is short, and the timing circuit can be more suitable for the development direction of 4G/5G in the future.
Description
Technical Field
The application belongs to the technical field of standard time calibration, and particularly relates to a timing circuit, a control method and timing equipment.
Background
Currently, most of timing instruments with timing function adopt quartz crystals as clock sources, and the oscillation frequency is affected by voltage, temperature, self-processing precision and the like, so that very high precision cannot be achieved, and accumulated errors are generated after a period of time, and timing correction is needed. Existing clock correction methods generally include global positioning system/Beidou system (Global Positioning System/Beidou system, GPS/BD), long wave time service system, and code division multiple access (Code Division Multiple Access, CDMA). The GPS/Beidou system time correction needs to lead the antenna out of the room, and a shielding object cannot exist nearby, so that the receiving time is long and the reaction is slow; the time correction of the long wave time service system has the problems of unstable received signals, incomplete signal coverage, larger influence of weather and the like; the CDMA timing can only be applied to 2G/3G technology generally, and is not suitable for the development trend of 4G/5G in the future.
Disclosure of Invention
The purpose of the application is to provide a timing circuit, a control method and timing equipment, and aims to solve the problems that the traditional timing circuit is long in receiving time, greatly influenced by environment and not suitable for future network development.
In order to achieve the above object, in a first aspect, an embodiment of the present application provides a timing circuit, including a long term evolution receiving module and a time conversion module;
the long-term evolution receiving module is electrically connected with the time conversion module;
the long-term evolution receiving module is configured to receive standard time sent by a base station and output the standard time according to a time request signal;
the time conversion module is configured to generate the time request signal and convert the standard time to greenwich mean time.
In another possible implementation manner of the first aspect, the timing circuit further includes a second signal source module;
the second signal source module is electrically connected with the time conversion module;
the second signal source module is configured to send a second signal source to the time conversion module when the long-term evolution receiving module fails;
the time conversion module is further configured to convert the second signal source into the greenwich mean time.
In another possible implementation manner of the first aspect, the timing circuit further includes a power supply module;
the power module is respectively and electrically connected with the long-term evolution receiving module and the time conversion module;
the power module is configured to supply power to the long term evolution receiving module and the time conversion module.
In another possible implementation manner of the first aspect, the long term evolution receiving module includes a first chip, a first capacitor, a second capacitor, a first resistor, and a first antenna;
the antenna pin of first chip respectively with the one end of first electric capacity with the one end electricity of first resistance is connected, the other end of first resistance respectively with the one end of second electric capacity with the one end electricity of first antenna is connected, the other end of first electric capacity, the other end of second electric capacity with the other end of first antenna is all grounded, the transmitting pin of first chip with the receiving pin of first chip all with the time conversion module electricity is connected.
In another possible implementation manner of the first aspect, the time conversion module includes a second chip, a second resistor, and a third resistor;
the transmitting pin of the second chip is electrically connected with one end of the second resistor, the other end of the second resistor is electrically connected with the long-term evolution receiving module, the receiving pin of the second chip is electrically connected with one end of the third resistor, and the other end of the third resistor is electrically connected with the long-term evolution receiving module.
In another possible implementation manner of the first aspect, the second signal source module includes a third chip, a sixth tunable capacitor, a seventh capacitor, and a second crystal oscillator;
the oscillator input pin of the third chip is respectively and electrically connected with one end of the second crystal oscillator and one end of the sixth adjustable capacitor, the oscillator output pin of the third chip is respectively and electrically connected with the other end of the second crystal oscillator and one end of the seventh capacitor, the other end of the sixth adjustable capacitor and the other end of the seventh capacitor are grounded, and the output pin of the third chip is electrically connected with the time conversion module.
In another possible implementation manner of the first aspect, the power supply module includes a fourth chip, an eighth capacitor, a ninth electrolytic capacitor, a tenth electrolytic capacitor, an eleventh capacitor, a first diode, and a second diode;
the input pin of the fourth chip is electrically connected with a power supply, one end of the eighth capacitor, the positive electrode of the ninth capacitor and the negative electrode of the first diode respectively, the output pin of the fourth chip is electrically connected with the positive electrode of the tenth capacitor, one end of the eleventh capacitor and the negative electrode of the second diode respectively, and the other end of the eighth capacitor, the negative electrode of the ninth capacitor, the negative electrode of the tenth capacitor, the other end of the eleventh capacitor, the positive electrode of the first diode and the positive electrode of the second diode are grounded.
In a second aspect, an embodiment of the present application provides a method for controlling a timing circuit, including the following steps:
acquiring standard time sent by a base station;
the hot start, cold start and/or the acquisition of network standard time from the network time server are performed at fixed time intervals.
In another possible implementation manner of the second aspect, the performing the hot start, the cold start and/or the obtaining the network standard time from the network time server at fixed intervals includes:
the first fixed time is spaced, and the network standard time is acquired from the network time server;
and/or performing the warm start at intervals of a second fixed time;
and/or, performing the cold start at intervals of a third fixed time.
In a third aspect, an embodiment of the present application provides a timing device, including the timing circuit.
Compared with the prior art, the embodiment of the application has the beneficial effects that: according to the timing circuit, the standard time sent by the base station is received through the long-term evolution receiving module, the standard time is converted into the Greenwich standard time through the time conversion module so as to be used for timing instrument correction, the whole circuit does not need to lead an antenna out of the room, the receiving signal is not influenced by time, place, weather and the like, the receiving speed is high, the receiving time is short, and the timing circuit can be more suitable for the development direction of 4G/5G in the future.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following description will briefly introduce the drawings that are needed in the embodiments or the description of the prior art, it is obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram of a timing circuit according to an embodiment of the present disclosure;
fig. 2 is a circuit diagram of a long term evolution receiving module of a timing circuit according to an embodiment of the present application;
FIG. 3 is a circuit diagram of a time conversion module of a timing circuit according to an embodiment of the present disclosure;
FIG. 4 is a circuit diagram of a second signal source module of the timing circuit according to an embodiment of the present disclosure;
FIG. 5 is a circuit diagram of a power module of the timing circuit provided in an embodiment of the present application;
FIG. 6 is a first flowchart of a control method of the timing circuit according to the embodiment of the present application;
fig. 7 is a second flowchart of a control method of the timing circuit according to the embodiment of the present application.
Description of the reference numerals
The system comprises a 1-long-term evolution receiving module, a 2-time conversion module, a 3-second signal source module and a 4-power module.
Detailed Description
In order to make the technical problems, technical schemes and beneficial effects to be solved by the present application more clear, the present application is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the present application.
Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature. In the description of the present application, the meaning of "a plurality" is two or more, unless explicitly defined otherwise.
The existing clock correction method generally adopts a global positioning system/Beidou system (Global Positioning System/Beidou system, GPS/BD), a long wave time service system, code division multiple access (Code Division Multiple Access, CDMA) and the like. However, the GPS/Beidou system time correction needs to lead the antenna out of the room, and a shielding object cannot be arranged nearby, so that the receiving time is long and the reaction is slow; the time correction of the long wave time service system has the problems of unstable received signals, incomplete signal coverage, larger influence of weather and the like; the CDMA timing can only be applied to 2G/3G technology generally, and is not suitable for the development trend of 4G/5G in the future.
Therefore, the time correction circuit receives the standard time sent by the base station through the long-term evolution receiving module, converts the standard time into Greenwich mean time through the time conversion module so as to be used for correction of a timing instrument, the whole circuit does not need to lead an antenna out of the room, the receiving signal is not influenced by time, place, weather and the like, the receiving speed is high, the receiving time is short, and the time correction circuit can be more suitable for the development direction of 4G/5G in the future.
The timing circuit provided in the present application is described below by way of example with reference to the accompanying drawings.
Fig. 1 is a schematic diagram of a first configuration of a timing circuit according to an embodiment of the present application. Referring to fig. 1, illustratively, a timing circuit 100 includes a long term evolution (Long Term Evolution, LTE) receiving module 1 and a time conversion module 2; the long term evolution receiving module 1 is electrically connected with the time conversion module 2.
The long term evolution receiving module 1 is configured to receive standard time sent by a base station and output the standard time according to a time request signal.
The time conversion module 2 is configured to generate a time request signal and convert a standard time into greenwich mean time.
In the embodiment of the application, the long-term evolution receiving module 1 receives the standard time sent by the 4G base station or the 5G base station in real time, when the timing instrument connected with the time conversion module 2 needs to correct the time, the time conversion module 2 sends a time request signal to the long-term evolution receiving module 1, the long-term evolution receiving module 1 sends the internally stored standard time to the time conversion module 2 according to the time request signal, and the time conversion module 2 converts the standard time into greenwich mean time. The greenwich mean time adopts international oceanic electronic association (National Marine Electronics Association, NMEA) format, and includes a plurality of data contents such as positioning time, latitude, longitude, altitude, satellite number for positioning, correction period and speed. The NMEA format is adopted, so that the output format of the GPS can be compatible, a timing instrument for receiving calibration can not only receive GPS signals, but also receive the signals of the radio, and the circuit interfaces are completely the same, so that the application range of the radio is wide. Meanwhile, the signal received by the long-term evolution receiving module 1 comes from a 4G base station or a 5G base station, and the signal strength is much stronger than the GPS signal from a satellite and the long-wave signal transmitted from a remote time service center, so that the receiving antenna is prevented from extending to the roof, and the receiving speed is high, the receiving reliability is good, and the whole structure is simple.
As shown in fig. 1, the timing circuit 100 further includes a second signal source module 3, illustratively; the second signal source module 3 is electrically connected with the time conversion module 2.
The second signal source module 3 is configured to send a second signal source to the time conversion module when the long term evolution receiving module 1 fails.
The time conversion module 2 is further configured to convert the second signal source into greenwich mean time.
In this embodiment of the present application, in general, the long term evolution receiving module 1 receives the standard time sent by the base station and sends the standard time to the time conversion module 2 for the time meter to calibrate. When the long term evolution receiving module 1 fails and cannot normally receive standard time, a second signal source can be sent to the time conversion module 2 through the second signal source module 3 to provide a time reference for self-timing of the time conversion module 2, so that the time conversion module 2 can continue to time with high precision according to the time reference, and correction standard time is provided for a timing instrument. The second signal source module 3 is a 1 second Pulse Per Second (PPS) signal time source.
Illustratively, as shown in FIG. 1, the timing circuit 100 also includes a power module 4; the power module 4 is electrically connected to the long term evolution receiving module 1 and the time conversion module 2, respectively.
A power module 4 configured to supply power to the long term evolution receiving module 1 and the time converting module 2.
In this embodiment of the present application, the power supply module 4 may supply power to not only the long term evolution receiving module 1 and the time conversion module 2, but also the second signal source module 3, so that the long term evolution receiving module 1, the time conversion module 2 and the second signal source module 3 work normally.
Fig. 2 is a circuit diagram of a long term evolution receiving module of a timing circuit according to an embodiment of the present application. Illustratively, as shown in fig. 2, the long term evolution receiving module 1 includes a first chip U1, a first capacitor C1, a second capacitor C2, a first resistor R1, and a first antenna ANT1.
The antenna pin ANT_MAIN of the first chip U1 is electrically connected with one end of a first capacitor C1 and one end of a first resistor R1 respectively, the other end of the first resistor R1 is electrically connected with one end of a second capacitor C2 and one end of the first antenna ANT1 respectively, the other end of the first capacitor C1, the other end of the second capacitor C2 and the other end of the first antenna ANT1 are grounded, and the transmitting pin MAIN_TXD of the first chip U1 and the receiving pin MAIN_RXD of the first chip U1 are electrically connected with the time conversion module 2.
In this embodiment of the present application, the network impedance is formed by the first capacitor C1, the second capacitor C2 and the first resistor R1, the requirement of the first antenna ANT1 is matched, the standard time sent by the external base station is received by the first antenna ANT1, and the obtained standard time is sent to the time conversion module 2 by the first chip U1. The first chip U1 is an EC600N type chip.
Fig. 3 is a circuit diagram of a time conversion module of the timing circuit according to an embodiment of the present application. Illustratively, as shown in fig. 3, the time conversion module 2 includes a second chip U2, a second resistor R2, and a third resistor R3.
The transmitting pin TXD of the second chip U2 is electrically connected with one end of a second resistor R2, the other end of the second resistor R2 is electrically connected with a long-term evolution receiving module 1, the receiving pin RXD of the second chip U2 is electrically connected with one end of a third resistor R3, and the other end of the third resistor R3 is electrically connected with the long-term evolution receiving module 1.
The time conversion module 2 further includes a fourth resistor R4, a third capacitor C3, a fourth capacitor C4, a fifth capacitor C5, a first crystal oscillator Y1, and a first plug-in unit P1.
One end of the third capacitor C3 is electrically connected with the power supply VCC, the other end of the third capacitor C3 is electrically connected with one end of the fourth resistor R4 and the reset pin RST of the second chip U2 respectively, one end of the fifth capacitor C5 and one end of the first crystal oscillator Y1 are electrically connected with the first crystal oscillator pin XTAL1 of the second chip U2, one end of the fourth capacitor C4 and the other end of the first crystal oscillator Y1 are electrically connected with the second crystal oscillator pin XTAL2 of the second chip U2, and the other end of the fourth resistor R4, the other end of the fourth capacitor C4 and the other end of the fifth capacitor C5 are grounded. The second chip U2 is further electrically connected to the first plug-in P1 for electrically connecting to the long term evolution receiving module 1 through the first plug-in P1.
In this embodiment of the present application, the second resistor R2 and the third resistor R3 play an isolation role during programming, and send a time request signal to the long term evolution receiving module 1, receive the standard time sent by the long term evolution receiving module 1, convert the received standard time into greenwich mean time, and calculate the standard time information of week, month, day, etc. And a reset circuit is formed by the third capacitor C3 and the fourth resistor R4 so as to be used for resetting and restarting the second chip U2. And an oscillation circuit is formed by the fourth capacitor C4 and the fifth capacitor C5, and a crystal oscillator starting signal is provided for the first crystal oscillator Y1. The second chip U2 may be an STC12C5a60S2 type chip.
Fig. 4 is a circuit diagram of a second signal source module of the timing circuit according to an embodiment of the present application. Illustratively, as shown in fig. 4, the second signal source module 3 includes a third chip U3, a sixth tunable capacitor C6, a seventh capacitor C7, and a second crystal Y2.
The oscillator input pin OSCI of the third chip U3 is electrically connected to one end of the second crystal oscillator Y2 and one end of the sixth adjustable capacitor C6, the oscillator output pin OSCO of the third chip U3 is electrically connected to the other end of the second crystal oscillator Y2 and one end of the seventh capacitor C7, the other end of the sixth adjustable capacitor C6 and the other end of the seventh capacitor C7 are both grounded, and the output pin OI of the third chip U3 is electrically connected to the time conversion module 2.
In the embodiment of the application, the third chip U3 provides a second signal source for the time conversion module 2, so that the time conversion module 2 converts the second signal source into greenwich mean time for the time meter to calibrate. And a crystal oscillator starting signal is provided for the second crystal oscillator Y2 through a sixth adjustable capacitor C6 and a seventh capacitor C7 to form an oscillation loop. The number of second pulses output by the output pin OI of the third chip U3 can be correspondingly adjusted by the capacitance of the sixth adjustable capacitor C6. In addition, in the embodiment of the present application, the frequency of the second crystal oscillator Y2 is 4.194304MHz. The signal of the third chip U3 is a wide temperature range chip of BY832 type, the 1PPS signal precision generated BY the BY832 chip is far higher than that of the low-frequency crystal, the daily difference is 0.1 second, and the daily difference of the common 32768Hz signal is 2 seconds and is in different orders of magnitude, so in the second signal source module 3, the BY832 chip can reach very high time precision.
In addition, in the conventional timing circuit, when the 4G signal or the 5G signal is not received stably, the timing circuit stops timing and continues to run by its own time source, thereby generating an accumulated error. However, after the time error reaches a certain degree, even if the 4G signal or the 5G signal is recovered, normal calibration of the clock cannot be achieved, so that the continuous timing of the device is inaccurate. However, for the BY832 chip in the second signal source module 3 in the embodiment of the present application, since the clock running with high precision can be ensured, the error is very small and is only 0.1 seconds, even if the 4G signal or the 5G signal is not received for a long time, once the reception is restored, the normal time calibration can be ensured, and the normal timing of the device can be maintained.
Fig. 5 is a circuit diagram of a power module of the timing circuit according to an embodiment of the present application. As shown in fig. 5, the power module 4 exemplarily includes a fourth chip U4, an eighth capacitor C8, a ninth electrolytic capacitor C9, a tenth electrolytic capacitor C10, an eleventh capacitor C11, a first diode D1, and a second diode D2.
The input pin Vin of the fourth chip U4 is electrically connected to the power source Vin, one end of the eighth capacitor C8, the positive electrode of the ninth electrolytic capacitor and the negative electrode of the first diode D1, and the output pin Vout of the fourth chip U4 is electrically connected to the positive electrode of the tenth electrolytic capacitor, one end of the eleventh capacitor C11 and the negative electrode of the second diode D2, respectively, and the other end of the eighth capacitor C8, the negative electrode of the ninth electrolytic capacitor C9, the negative electrode of the tenth electrolytic capacitor C10, the other end of the eleventh capacitor C11, the positive electrode of the first diode D1 and the positive electrode of the second diode D2 are all grounded.
In the embodiment of the application, the fourth chip U4 converts the power supply voltage into 5V voltage and supplies power to the long term evolution receiving module 1, the time conversion module 2 and the second signal source module 3, so that the long term evolution receiving module 1, the time conversion module 2 and the second signal source module 3 can work normally. The input voltage is subjected to high-frequency filtering through an eighth capacitor C8, is subjected to low-frequency filtering through a ninth electrolytic capacitor C9, plays a role in reverse protection through a first diode D1, is subjected to high-frequency filtering through an eleventh capacitor C11, is subjected to low-frequency filtering through a tenth electrolytic capacitor C10, and plays a role in reverse protection through a second diode D2. The fourth chip U4 is a chip of AS1117-5V type.
According to the timing circuit, the standard time sent by the base station is received through the long-term evolution receiving module, the standard time is converted into Greenwich standard time through the time conversion module so as to be used for timing instrument correction, the whole circuit does not need to lead an antenna outdoors, a receiving signal is not influenced by time, place, weather and the like, the receiving speed is high, the receiving time is short, and the timing circuit can be more suitable for the development direction of 4G/5G in the future.
Based on the timing circuit provided in the above-described embodiment, a control method of the timing circuit will be specifically described below, respectively.
Illustratively, fig. 6 is a first flowchart of a control method of the timing circuit according to the embodiment of the present application. As shown in fig. 6, a control method of the timing circuit includes the following steps:
s100, the long-term evolution receiving module 1 acquires standard time sent by a base station.
And S200, performing hot start and cold start at fixed time intervals and/or acquiring network standard time from a network time server by the long-term evolution receiving module 1.
In the embodiment of the present application, the long term evolution receiving module 1 normally acquires the standard time sent by the 4G base station or the 5G base station in a general case. However, when the long term evolution receiving module 1 runs out and fails to normally receive the dead halt condition of the signal during the running process, the long term evolution receiving module 1 cannot provide the correct standard time for the time conversion module 2, and once the long term evolution receiving module 1 fails to halt condition, the long term evolution receiving module cannot automatically recover to the normal state. Therefore, the long-term evolution receiving module 1 is enabled to be subjected to hot start and cold start at fixed time intervals and/or network standard time is acquired from the network time server, so that the long-term evolution receiving module 1 has a plurality of standard time sources and is not in a halt state for a long time, and reliability and accuracy of the standard time provided by the whole timing circuit are ensured.
Fig. 7 is a second flowchart of a control method of the timing circuit according to the embodiment of the present application. As shown in fig. 7, the method specifically includes the following steps:
performing a hot start, a cold start, and/or obtaining a network standard time from a network time server at regular intervals, comprising:
and acquiring the network standard time from the network time server at intervals of a first fixed time.
And/or, performing a hot start at intervals of a second fixed time.
And/or, performing cold start at intervals of a third fixed time.
In the embodiment of the present application, the following steps may be adopted:
s100, normally acquiring standard time from the base station.
S201, judging whether the first fixed time is spaced, if so, acquiring network standard time from a network time server, and if not, performing the next step.
S202, judging whether a second fixed time is spaced, if so, performing hot start, and if not, performing the next step.
S203, judging whether a third fixed time is spaced, if so, performing cold start, and if not, returning to S100.
Through the three modes, the reliability of the long-term evolution receiving module 1 in acquiring standard time can be effectively ensured, and the long-term evolution receiving module 1 is prevented from being in a dead state all the time. In addition, the values of the first fixed time, the second fixed time, and the third fixed time may be set in advance.
Illustratively, embodiments of the present application provide a timing apparatus, including a timing circuit 100.
The time correction circuit 100 is installed in time correction equipment, receives standard time sent by a base station through a long-term evolution receiving module, converts the standard time into Greenwich standard time through a time conversion module, and is used for correcting a timing instrument.
It should be understood that the sequence number of each step in the foregoing embodiment does not mean that the execution sequence of each process should be determined by the function and the internal logic of each process, and should not limit the implementation process of the embodiment of the present application in any way.
It will be apparent to those skilled in the art that, for convenience and brevity of description, only the above-described division of the functional units and modules is illustrated, and in practical application, the above-described functional distribution may be performed by different functional units and modules according to needs, i.e. the internal structure of the apparatus is divided into different functional units or modules to perform all or part of the above-described functions. The functional units and modules in the embodiment may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one unit, where the integrated units may be implemented in a form of hardware or a form of a software functional unit. In addition, specific identification information of each functional unit and each module is only for convenience of distinguishing each other, and is not used for limiting the protection scope of the application. The specific working process of the units and modules in the above system may refer to the corresponding process in the foregoing embodiment, which is not described herein again.
In the foregoing embodiments, the descriptions of the embodiments are emphasized, and in part, not described or illustrated in any particular embodiment, reference is made to the related descriptions of other embodiments.
Those of ordinary skill in the art will appreciate that the elements of the examples described in connection with the embodiments disclosed herein can be implemented as electronic hardware, or as a combination of computer software and electronic hardware. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the solution. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application.
In the embodiments provided in the present application, it should be understood that the disclosed control method of the space location may be implemented in other manners. For example, the above-described embodiments of a control method for a space location are merely exemplary, for example, the division of modules or units is merely a logical function division, and there may be other manners of division in actual implementation, for example, multiple units or components may be combined or integrated into another system, or some features may be omitted, or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed with each other may be through some multi-interface system, device or unit indirect coupling or communication connection, which may be in electrical, mechanical or other form.
The units described as separate units may or may not be physically separate, and units shown as units may or may not be physical units, may be located in one place, or may be distributed over a plurality of network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.
In addition, each functional unit in each embodiment of the present application may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one unit. The integrated units may be implemented in hardware or in software functional units.
The above embodiments are only for illustrating the technical solution of the present application, and are not limiting thereof; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present application, and are intended to be included in the scope of the present application.
Claims (10)
1. The timing circuit is characterized by comprising a long-term evolution receiving module and a time conversion module;
the long-term evolution receiving module is electrically connected with the time conversion module;
the long-term evolution receiving module is configured to receive standard time sent by a base station and output the standard time according to a time request signal;
the time conversion module is configured to generate the time request signal and convert the standard time to greenwich mean time.
2. The circuit of claim 1, wherein the timing circuit further comprises a second signal source module;
the second signal source module is electrically connected with the time conversion module;
the second signal source module is configured to send a second signal source to the time conversion module when the long-term evolution receiving module fails;
the time conversion module is further configured to convert the second signal source into the greenwich mean time.
3. The circuit of claim 1 or 2, wherein the timing circuit further comprises a power supply module;
the power module is respectively and electrically connected with the long-term evolution receiving module and the time conversion module;
the power module is configured to supply power to the long term evolution receiving module and the time conversion module.
4. The circuit of claim 1, wherein the long term evolution receive module comprises a first chip, a first capacitor, a second capacitor, a first resistor, and a first antenna;
the antenna pin of first chip respectively with the one end of first electric capacity with the one end electricity of first resistance is connected, the other end of first resistance respectively with the one end of second electric capacity with the one end electricity of first antenna is connected, the other end of first electric capacity, the other end of second electric capacity with the other end of first antenna is all grounded, the transmitting pin of first chip with the receiving pin of first chip all with the time conversion module electricity is connected.
5. The circuit of claim 1, wherein the time conversion module comprises a second chip, a second resistor, and a third resistor;
the transmitting pin of the second chip is electrically connected with one end of the second resistor, the other end of the second resistor is electrically connected with the long-term evolution receiving module, the receiving pin of the second chip is electrically connected with one end of the third resistor, and the other end of the third resistor is electrically connected with the long-term evolution receiving module.
6. The circuit of claim 2, wherein the second signal source module comprises a third chip, a sixth tunable capacitor, a seventh capacitor, and a second crystal;
the oscillator input pin of the third chip is respectively and electrically connected with one end of the second crystal oscillator and one end of the sixth adjustable capacitor, the oscillator output pin of the third chip is respectively and electrically connected with the other end of the second crystal oscillator and one end of the seventh capacitor, the other end of the sixth adjustable capacitor and the other end of the seventh capacitor are grounded, and the output pin of the third chip is electrically connected with the time conversion module.
7. The circuit of claim 3, wherein the power module comprises a fourth chip, an eighth capacitor, a ninth electrolytic capacitor, a tenth electrolytic capacitor, an eleventh capacitor, a first diode, and a second diode;
the input pin of the fourth chip is electrically connected with a power supply, one end of the eighth capacitor, the positive electrode of the ninth capacitor and the negative electrode of the first diode respectively, the output pin of the fourth chip is electrically connected with the positive electrode of the tenth capacitor, one end of the eleventh capacitor and the negative electrode of the second diode respectively, and the other end of the eighth capacitor, the negative electrode of the ninth capacitor, the negative electrode of the tenth capacitor, the other end of the eleventh capacitor, the positive electrode of the first diode and the positive electrode of the second diode are grounded.
8. A control method based on a timing circuit according to any one of claims 1-7, characterized by the steps of:
acquiring standard time sent by a base station;
the hot start, cold start and/or the acquisition of network standard time from the network time server are performed at fixed time intervals.
9. The method of claim 8, wherein the performing a hot start, a cold start, and/or obtaining a network standard time from a network time server at fixed intervals comprises:
the first fixed time is spaced, and the network standard time is acquired from the network time server;
and/or performing the warm start at intervals of a second fixed time;
and/or, performing the cold start at intervals of a third fixed time.
10. A timing device comprising a timing circuit as claimed in any one of claims 1 to 7.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202310157135.8A CN116360234A (en) | 2023-02-15 | 2023-02-15 | Timing circuit, control method and timing equipment |
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| CN202310157135.8A CN116360234A (en) | 2023-02-15 | 2023-02-15 | Timing circuit, control method and timing equipment |
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